JPH02201695A - System for developing parallel processor - Google Patents

Abstract

PURPOSE:To efficiently execute debugging at high speed by inputting input data for processing from a control computer to a processor at high speed corresponding to a really applied speed and tracing a transfer condition by a tracer part. CONSTITUTION:A data packet 10 for processing execution is inputted from a control computer 31 through an interface part 40 to a processing element 10 of the parallel processor. The data packet incoming to trace ports is traced by plural tracer parts 60, for which the trace ports are connected to the plural terminals of the processing element 60, together with common time information synchronously with the internal clock of the system. Further, traced results stored in the trace memories of the plural tracer parts 60 are collected and formed as a file. Then, the results are formed as a data flow graph and displayed. Thus, the debugging of a hardware or a software can be made easy and speedy in the development of the parallel processor.

Description

[Detailed Description of the Invention] [Industrial Application Field] The present invention relates to a parallel processing device development system, and particularly to a system that can facilitate and speed up debugging of hardware and software in the development of data-driven (data flow) processors. The present invention relates to a parallel processing device development system having a development support environment (development support tool).

[Conventional technology]

FIG. 11 is a diagram showing the configuration of a conventional data-driven processor development system. In the figure, 90 is a host personal computer, 91 is a timer, 92 is a memory address generator, 93 is a data-driven processor, and 94 is a graphic processor. 95 is an image memory, 96 is a CRT 197 is a system bus, and 98 is an image memory bus.

In this configuration, initialization, setting breakpoints,
Performs dump display, loading, setting movement, input, output, object program loading, etc. of each part of memory.

Next, the operation will be explained.

Initialization, object loading, setting/loading of each section's memory, etc. are performed by writing data from the host computer 90 to each section based on commands from the host computer 90. Conversely, dump display is performed by reading data from each part to the host computer 90,
Movement is performed by a combination of these. Data for calculation can also be input from the host computer 90.

[Problem to be solved by the invention]

Conventional parallel processing device development systems are configured as described above, and perform the above processing in response to commands from the host computer, but they can only display memory values during execution or at the end of execution, which is difficult for data-driven processors. It is not a development support environment that can trace processing and use the results to streamline debugging in the development of application systems using data-driven processors, but rather it is The problem was that it couldn't be done.

This invention was made to solve the above problems, and is a parallel processing device development system having a development support environment that enables efficient and high-speed debugging of hardware and software in the development of application systems for data-driven processors. The purpose is to obtain.

[Means to solve the problem]

The parallel processing device development system according to this invention is 1111
1. A data input unit equipped with a dedicated input packet memory that inputs processing input data from a wholesale computer to a multiprocessor parallel processing device at high speed corresponding to the processing speed of the actual application of the parallel processing device; It is equipped with a trace unit equipped with a trace memory that traces the data transfer status of the functional unit name part of the processing device along with time information in the processing execution state, and also converts the trace results by the trace unit into a file to create and display a data flow graph. It was designed to do so.

[Effect]

In this invention, a data input unit equipped with a dedicated input packet memory inputs input data for processing at a high speed corresponding to the processing speed of practical applications, and a tracer equipped with a trace memory inputs input data for each processor function. Since the transfer status is traced while it is being executed, and the trace results are converted into a file and converted into a data flow graph, debugging of hardware and software in the development of a parallel processing device can be carried out efficiently and at high speed.

C Example] An embodiment of the present invention will be described below with reference to the drawings.

FIG. 1 is a diagram showing the configuration of a parallel processing device development system according to an embodiment of the present invention.

In the figure, 1 is a development support environment, and 10 is a processing element (PE) including a data-driven processor.
, 20 is a data-driven processor main unit, and 21 is an extended program storage unit (Extended Program S).
tore: EP S ), 2 2 is an extended data storage unit, (Extended Data Store: E
DS), 2 3 is an external color/stack processing unit (
External Color/Stack Proc
ess: ECS), 3 1 is a control computer such as a personal computer, 40 is an interface section, and 60 is a tracer section.

FIG. 2 is a diagram showing the configuration of the processing element 10. In the figure, 11 is a cache program storage (Cache program storage).
he Program Store: CPS)
, 1 2 is the firing process (Firing Control:
FC), 1 3 is arithmetic processing (Functiona)
l Process: F P), 14 is a junction & Branct+: J
&B), 1 5 is a Cuban sofa (Queuin
g Buffer: QB).

FIG. 3 is a diagram showing a packet of a data-driven processor, and in the figure, each field has a function as shown in the figure.

FIG. 4 is a configuration diagram of the interface section 40, 41
is a conventional (Neumann) microprocessor unit that manages the interface unit 40 and tracer unit 60; 42 is a ROM and RAM that stores programs and data for the microprocessor unit 41; and 43 is a serial I10 controller that connects to the control computer 31. ,
44 is an output port for inputting data packets to the data-driven processor of the processing element 10;
45 is a write address counter for writing data into the input packet memory; 46 is a read address counter for reading data from the input packet memory;
Reference numeral 47 indicates a stop address latch for stopping the packet output, which is used when ending the output of data packets from the output port 44, 48a indicates an address multiplexer for input packet memory, 48b indicates a data multiplexer for input packet memory, and 49 indicates an output. Port output driver, 50 is 4k x 64 bits input packet memory,
51 is an input packet memory 50 when inputting a data packet.
52 is a flip-flop that indicates the data packet input state, 53 is a data packet input start trigger generator, and 54 stores the packet interval when data packets are input. An input interval latch 55 is an input interval counter for measuring the data packet input interval, and 56 is an output control unit for inputting data packets.

FIG. 5 is a configuration diagram of the tracer section 60, and in the figure,
61 is a trace port, 62 is a timer, 63 is an input latch, 64 is a synchronization circuit, 65 is a demultiplexer, 66
is a mode control unit, 67 is an address counter, and 68 is a 4k
x96-bit trace memory, 69 a read/write controller, 70 a breakpoint latch, 71 a comparator, and 72 a breakpoint address launch.

Next, the operation of this embodiment will be explained.

The data driven processor 10 is CPSII, FCl2, F
P13 is the basic element, and J&B14 and QB15 are combined to form a cyclic pipeline as shown in FIG. E
PS21 is a functional unit that stores a CPSIIO external extension program, EDS22 is a functional unit that stores array data, etc., and EC323 is a functional unit that handles color management and external queues.

The input packet with the format shown in Figure 3 is J
The signal is input to CPSll through the confluence section of &B14. C
The PSII has an EPS 21, and, triggered by the next destination of the packet that has passed through the FCl2, extracts the next required program data from the EPS and stores it in the CPSII.

In the case of a unary operation, it is output as is, and in the case of a binary operation, it is output from the FCl2 after forming an operand pair. This calculation packet is sent to the FP13 and the instruction code (OPC:
0operation Code), and J&
It is determined whether or not to output by the branch function of B14,
If it is not output, the process returns to CPSII again and the same process is repeated.

It is assumed that the program is basically executed from the lowest node number, except for loops, and the matching memory of FCl2 is hashed, and when there is a hash collision in the matching memory, the one with the smaller generation or the one with the smaller node number It is possible to execute processing without overflowing the cyclic pipeline in the chip by saving the cyclic pipeline in the chip and sending the other ones to the cyclic pipeline or EC323, and always executing the processing in order of priority. It is something to do.

Furthermore, there are two data buses for other parts of the cyclic pipeline between CPSII and FCl2, so that there is no bottleneck in the data transfer path even during C0PY processing in CPSII.

The operation of the development support environment 1 is controlled by a control computer 31. The hardware includes a minimum of six pieces including an interface section 40 and a tracer section 60.

Among them, the processing element 10 including a data-driven processor includes a data-driven processor main unit 20, an extended processor storage unit EPS21, an extended data storage unit EDS22, and an external color stack processing unit EC32.
It consists of 4 pieces of 3.

The entire development support environment 1 is controlled by a control computer 31. Data is input and collected by the development support environment control program of the control computer 31.

The processing functions of the control program are shown below.

■ Input mode Load program/data, load input data packets, set number of input data packets, input input data packets, input dump bucket.

■ Collection mode Set breakpoint comparison value, set breakpoint mask value, start tracer to start tracing, preset trace address counter, write trace memory to file, read breakpoint generation address.

Memory dump is performed by PE# of processing element 10.
Every EDS21. FCl2. A tracer collects dump buckets output from each memory by specifying a start address and an end address for the EPS 21. In addition to this,
It is possible to return from the control program.

FIGS. 4 and 5 are functional configuration diagrams of the interface section and the toss section, respectively. Control computer: 31
Transfers between the data and the development support environment 1 including the data-driven processor are performed via the interface unit 40.

The operations of both functional units will be explained in detail below. The interface unit 40 has serial ports 1 to 43 and is connected to the control computer 31. , MPU41 is serial baud I.
The above-mentioned input mode and collection mode functions are executed by commands from 43. The interface unit 40 initializes the entire development support environment 2 at the same time as supplying power.
After that, wait for command 4 from the control computer. To load programs and data, the tag area and 32 bits of data as shown in FIG. This is done by Since it is essential to input data packets at high speed, an input bucket memory 50 is used. The input bucket memory 50 has a write address counter 45
After loading up to 4 words using the input data packet number and setting information corresponding to the number of input data packets in the stop address latch 47, the read address counter 46 is set in the stop address latch 47 by an input command that specifies the input interval. Pour in all at once until it matches the specified value.

Further, the address/data bus of the interface section 40 is connected to the tracer section 60, and the tracer section 60 is also controlled.

The tracer section 60 has a 4k x 95 bit trace memory 6.
8, and can be connected to any terminal of the processing element 10 for tracing. The tracer section 60 is connected to the address/data bus of the interface section 40 and is directly controlled by the interface section 40. If necessary, it is possible to set breakpoint comparison values and mask data. After setting the tracer number and trace mode, the interface unit 40 instructs to start tracing. Thereafter, the tracer section 60 synchronizes the data packets coming in from the trace port 61 with the internal clock, launches them, and stores them in the trace memory 68 along with time information. When setting a breakpoint on breakpoint launch 70,
It stops after detecting a matching bucket in the output of the comparator 71, but there are three trace modes: stop immediately, stop after tracing 1/2 of the memory capacity, and stop after tracing the memory capacity. can be selected and the trace history can be effectively stored.

After tracing, breakpoint address latch 72
The breakpoint generation address can be read from , and valid data can be determined from the trace mode and address counter 6 value.

The trace results in the trace memory 68 can be dumped and converted into a file by the interface unit 40, and this file can be displayed as a list.

A plurality of trace sections 60 can be connected, and 15 trace sections 60 can be used per one interface section 40 to simultaneously measure 15 points. Tracing is performed at connection points with functional units such as calculation packets and result packets, and the operation of the entire system can be captured along with the trace time information stored at the same time.

In this embodiment, it is possible to display data of each part of the processing element 10 collected by the tracer unit 60. FIG. 6 is a diagram showing an example of how trace results are displayed. FIG. 6 fa) shows an FP13 output display, and FIG. 6B shows an EC323 output display.

The data-driven processor is developed in conjunction with the language processing system, but the language processing system's compiler output format file,
For the object code output from Matsupa and the execution trace results, tools are provided to graphically represent and modify the program. This allows graphical display of object code and execution trace results for each processor even in a multiprocessor execution environment. By comparing these, unprocessed nodes, uninput data packets, unaccessed memory, etc. can be found extremely easily, making it easy to debug multiprocessors. Maximum degree of parallelism, average degree of parallelism, number of execution ranks, execution time, etc. during execution can be displayed along with time information, and operation rates can be easily evaluated in the same way as simulator execution results.

For this display, for example, Japanese Patent Application No. 6.2-5440
6 "Associative memory devices and data-driven computers" The results of the rank analysis necessary for assigning node numbers in the data replacement method described in 6. Improving.

A graphical display of a compiler output format file can be performed on a function-by-function basis, and is generally easier to see than a graphical display of Matsupa output (object code) in which multiple functions are expanded.

FIG. 7 is a diagram showing a graph ink display example of the mapper output of the data flow graph of the cubic polynomial calculation program, and FIG. 8 is a diagram showing a display example of the trace result.

In this way, in this embodiment, the control computer 3
A plurality of tracers each having a trace memory 68 and having trace ports connected to a plurality of terminals of the processing element 10 input data packets for processing execution from 1 to the processing element 10 of the parallel processing device at high speed. The unit 60 traces data packets entering the trace port in synchronization with the internal clock of the system together with common time information, and further collects the trace results stored in the trace memories of the plurality of tracer units 60 and files them. Since the data flow graph is displayed in the form of a data flow graph, debugging of hardware or software in the development of a parallel processing device can be extremely facilitated and speeded up.

Although the above embodiment has been described as a development support environment for a data-driven processor, it can also be implemented in a similar manner in other parallel processing computers or processors.

In addition, in the embodiment shown in FIG.
Various other connections are possible, such as a shirt-full net connection, as shown, or a daisy-chain connection, as shown in FIG.

〔Effect of the invention〕

As described above, according to the present invention, input data for processing is inputted from the control computer to the processor at high speed corresponding to the processing speed of the actual application via the data input unit equipped with a dedicated input packet memory, and A tracer section equipped with a trace memory traces the data transfer status of each functional section of the processor along with time information while in the execution state, and the trace results are converted into a file and displayed as a data flow graph.
This has the effect of enabling efficient and high-speed debugging of hardware and software in the development of parallel processing devices.

[Brief explanation of the drawing]

FIG. 1 is a diagram showing the configuration of a parallel processing device development system according to an embodiment of the present invention, FIG. 2 is a diagram showing the configuration of processing elements, FIG. 3 is a diagram showing buckets of a data-driven processor, and FIG. Figure 5 is a configuration diagram of the interface section, Figure 5 is a configuration diagram of the tracer unit, Figure 6 is a diagram showing an example of a trace result, Figure 7 is a diagram showing an example of graph ink display of Matupa output which is a data flow graph, FIG. 8 is a diagram showing a display example of trace results, FIG. 9 is a diagram showing a shirtful net connection of data-driven processors, FIG. 10 is a diagram showing a daisy-chain connection of data-driven processors, and FIG. 1 is a diagram showing the configuration of a conventional parallel processing device development system. 1 is a development support environment, 10 is a processing element consisting of a data-driven processor, 20 is a data-driven processor main body, 40 is an interface section, and 60 is a tracer section. Note that the same reference numerals in the figures indicate the same or equivalent parts.

Claims (1)

[Claims] (1) A parallel processing device consisting of one or more multiprocessors, a control computer for driving the parallel processing device, memory means for storing a plurality of packets for processing execution from the control computer, and a data packet input section comprising a measuring means for inputting the packets stored in the memory means to the multiprocessor of the parallel processing device at settable input intervals; and a desired location of the plurality of functional sections of the multiprocessor. a tracer unit connected to an input/output port and a data transfer port provided in the controller, and equipped with an internal trace memory in which data packets from the ports are captured and stored in synchronization with an internal clock along with common time information. , and a function of displaying data packets that are processing execution results captured in the trace memory of the tracer unit in the order of processing;
A parallel processing device development system characterized by having a function of comparing this with an execution program.