JPH0739243Y2 - Lead frame - Google Patents
Lead frameInfo
- Publication number
- JPH0739243Y2 JPH0739243Y2 JP1987079211U JP7921187U JPH0739243Y2 JP H0739243 Y2 JPH0739243 Y2 JP H0739243Y2 JP 1987079211 U JP1987079211 U JP 1987079211U JP 7921187 U JP7921187 U JP 7921187U JP H0739243 Y2 JPH0739243 Y2 JP H0739243Y2
- Authority
- JP
- Japan
- Prior art keywords
- lead frame
- lead
- inner lead
- group inner
- wire
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Lifetime
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/02—Bonding areas ; Manufacturing methods related thereto
- H01L24/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L24/06—Structure, shape, material or disposition of the bonding areas prior to the connecting process of a plurality of bonding areas
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
- H01L2224/0554—External layer
- H01L2224/0555—Shape
- H01L2224/05552—Shape in top view
- H01L2224/05554—Shape in top view being square
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4805—Shape
- H01L2224/4809—Loop shape
- H01L2224/48091—Arched
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
- H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
- H01L2224/491—Disposition
- H01L2224/49105—Connecting at different heights
- H01L2224/49109—Connecting at different heights outside the semiconductor or solid-state body
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
- H01L2224/491—Disposition
- H01L2224/4912—Layout
- H01L2224/49171—Fan-out arrangements
Landscapes
- Engineering & Computer Science (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Wire Bonding (AREA)
- Lead Frames For Integrated Circuits (AREA)
Description
【考案の詳細な説明】 〔産業上の利用分野〕 本考案は、半導体素子を搭載し、かつ、該半導体素子と
ワイヤボンディングにより接続されるリードフレームに
関する。DETAILED DESCRIPTION OF THE INVENTION [Industrial application] The present invention relates to a lead frame on which a semiconductor element is mounted and which is connected to the semiconductor element by wire bonding.
Niを42％含有するNiとFeの合金である42アロイ等の板材
をエッチング又はプレス等によって、配線等を形成した
リードフレームは、半導体産業を中心に広範囲に用いら
れている。Lead frames in which wiring and the like are formed by etching or pressing a plate material such as 42 alloy, which is an alloy of Ni and Fe containing 42% of Ni, are widely used mainly in the semiconductor industry.
この種のリードフレームは半導体素子に設けられた微細
な電極と外部機器等との接続を容易にし、また半導体素
子の取り扱いを容易にするという利点を持つ反面、半導
体素子上の接続電極に対するインナーリードの高さが一
定であるため、リードピッチが狭くなる程、ワイヤ相互
の接触等によるボンディング不良が発生し易くなるとい
う問題があった。This type of lead frame has the advantage of facilitating the connection between the fine electrodes provided on the semiconductor element and external equipment and facilitating the handling of the semiconductor element. Since the height of the wire is constant, there is a problem that as the lead pitch becomes narrower, defective bonding is more likely to occur due to contact between wires or the like.
第２図は従来構造のリードフレームと半導体素子とをワ
イヤボンディングした断面図を示し、リードフレーム
の、アイランド６に接着固定した半導体素子５の上面に
設けた接続電極４とリードフレームのインナーリード７
とをAu又はAl又はCu等より成る極細線のワイヤ３で接続
したものである。FIG. 2 is a cross-sectional view of a conventional lead frame and a semiconductor element wire-bonded to each other. The connection electrode 4 and the inner lead 7 of the lead frame provided on the upper surface of the semiconductor element 5 adhered and fixed to the island 6 of the lead frame are shown.
And are connected by an ultrafine wire 3 made of Au, Al, Cu or the like.
このような従来構造のリードフレームによれば、インナ
ーリード７の高さは全て同一となっているため、近年の
小型で高密度多端子の接続に伴い、インナーリード数が
増加し、リードピッチが縮小してくると、ボンディング
時にキャピラリー等が接触して起るワイヤ相互の短絡、
及び樹脂パッケージを行なうトランスファモールド工程
に於けるワイヤ流れによって発生するワイヤ相互の短絡
等が問題となっていた。According to the lead frame having such a conventional structure, since the heights of the inner leads 7 are all the same, the number of inner leads is increased and the lead pitch is increased with the recent connection of small size and high density multi-terminals. When shrinking, short circuits between wires caused by contact with capillaries during bonding,
Also, there has been a problem such as a short circuit between wires which is caused by a wire flow in a transfer molding process for resin packaging.
しかしながら近年のパッケージに対する小型化、多端子
化の要求は高まる一方であり、その結果、インナーリー
ドのピッチはますます微細化し、上記従来の問題が不可
避となっている。すなわち、ワイヤボンディングに際
し、ワイヤ間隔が狭くなるとボンディングツールである
キャピラリー等の接触によってワイヤ相互の接触による
短絡が起こり易く、またパッケージ樹脂を加圧成形して
行なうモールド工程に於いても、ワイヤ流れによるワイ
ヤ相互の接触が生じ易くなるという問題があった。However, in recent years, there has been an increasing demand for miniaturization and multi-terminals in packages, and as a result, the pitch of the inner leads has become finer, and the above-mentioned conventional problems are unavoidable. That is, during wire bonding, when the wire spacing becomes narrow, a short circuit easily occurs due to contact between wires due to contact with a bonding tool such as a capillary. There is a problem that the wires are likely to come into contact with each other.
本考案は上記従来の課題に鑑みなされたものであり、多
端子化によるインナーリードの微細ピッチ化に充分対応
したワイヤボンディングを可能とし、かつモールド工程
に於けるワイヤ流れにより生じる短絡の発生を大巾に低
減することが可能な改良されたリードフレームを提供す
ることを目的とする。The present invention has been made in view of the above-mentioned conventional problems, and enables wire bonding sufficiently corresponding to a fine pitch of inner leads due to the increase in the number of terminals, and the occurrence of short circuits caused by wire flow in the molding process is large. It is an object to provide an improved lead frame that can be reduced in width.
上記目的を達成するために、本考案は、ワイヤボンダー
が高さの異なる２点間のボンディングを容易に行なえる
ことに着目し、リードフレームのインナーリードの先端
部を一本おきに折り曲げて段差をつけ、隣接するインナ
ーリードの先端部を立体的に分離したことを特徴とす
る。In order to achieve the above object, the present invention focuses on the fact that a wire bonder can easily bond two points having different heights, and bends every other tip of the inner lead of the lead frame to form a step. And the tip of the adjacent inner lead is three-dimensionally separated.
本考案によれば、同一高さにあるインナーリードの間隔
は少なくとも従来の２倍となっており、インナーリード
が立体的に位置しているので、従来のようなキャピラリ
ー等の接触によるボンディング不良の発生及び、モール
ド工程に於けるワイヤ流れによる短絡不良の大巾な低減
が可能となる。According to the present invention, the distance between the inner leads at the same height is at least twice as large as that of the conventional one, and the inner leads are three-dimensionally positioned. It is possible to drastically reduce the occurrence and short circuit defects due to the wire flow in the molding process.
以下図面に基づいて本考案の好適な実施例を説明する。 A preferred embodiment of the present invention will be described below with reference to the drawings.
第１図は本考案によるリードフレームの一実施例の断面
図であり、従来構造と同じ高さを持つ第１群インナーリ
ード２の隣に、高さの異なる第２群インナーリード１を
設け、半導体素子５に設けた接続電極４と第１群インナ
ーリード及び第２群インナーリードとをAu又はAl、又は
Cu等より成る極細線のワイヤ３で接続したものである。FIG. 1 is a sectional view of an embodiment of a lead frame according to the present invention, in which a second group inner lead 1 having a different height is provided next to a first group inner lead 2 having the same height as the conventional structure. The connection electrode 4 provided on the semiconductor element 5 and the first group inner lead and the second group inner lead are Au or Al, or
It is connected by an ultrafine wire 3 made of Cu or the like.
本考案によるリードフレーム構造によれば、第１群イン
ナーリードと第２群インナーリードとは１本毎に互いに
上下に位置しているため、接続されたワイヤ３もインナ
ーリード側で上下に位置することになり、ボンディング
時に於けるキャピラリー等の接触、或いはトランスファ
モールド工程に於けるワイヤ流れ等によるワイヤの短絡
不良等の問題を大巾に改善することが可能である。According to the lead frame structure of the present invention, since the first group inner leads and the second group inner leads are located above and below each other, the connected wires 3 are also located above and below the inner leads. Therefore, it is possible to greatly improve the problems such as the contact of the capillaries or the like during the bonding, or the short circuit of the wires due to the wire flow in the transfer molding process.
また第３図は本考案によるリードフレームの一実施例の
上面図で、半導体素子５の上面外周に沿って接続電極４
を２列に配置した半導体素子をワイヤボンディングした
ものであり、本考案によるリードフレーム構造によれ
ば、従来の半導体素子には実用困難であった高密度に配
置された外部電極に対しても、ワイヤボンディングを容
易に行なうことが可能となった。FIG. 3 is a top view of an embodiment of the lead frame according to the present invention, in which the connection electrode 4 is formed along the outer periphery of the top surface of the semiconductor element 5.
The semiconductor elements arranged in two rows are wire-bonded to each other. According to the lead frame structure of the present invention, the external electrodes arranged at a high density, which are difficult to practically use in the conventional semiconductor element, It became possible to easily perform wire bonding.
第４図は本考案によるリードフレームの第２群インナー
リードを形成する工程を示した断面図で、第２群インナ
ーリードの位置に対応した突起12を設けた下パンチ11と
該突起に対応した位置に凹み10を設けた上パンチ９との
間に従来法で配線を形成したリードフレーム８を位置合
せし、油圧プレス等によって曲げ加工を施すものであ
る。FIG. 4 is a cross-sectional view showing a process of forming the second group inner lead of the lead frame according to the present invention, which corresponds to the lower punch 11 having the protrusion 12 corresponding to the position of the second group inner lead and the protrusion. The lead frame 8 on which wiring is formed by the conventional method is aligned with the upper punch 9 having the recess 10 at the position, and is bent by a hydraulic press or the like.
また第５図は本考案によるリードフレームをワイヤボン
ディングする際の第２群インナーリードを裏打ちする方
法の一実施例の断面図で、第２群インナーリードに適応
した位置と形状を持つ突起14を設けたヒートコマ13を、
ボンディングに際しリードフレームを加熱するヒートブ
ロック15に装着したもので、８はリードフレームであ
る。FIG. 5 is a sectional view showing an embodiment of a method for lining the second group inner leads when wire-bonding the lead frame according to the present invention, in which a protrusion 14 having a position and shape adapted to the second group inner leads is formed. The provided heat piece 13
The lead frame 8 is mounted on a heat block 15 for heating the lead frame during bonding.
本考案によるリードフレームはボンディングされたワイ
ヤを、従来のような平面的な分離に加え立体的に分離す
るので、ボンディング時に於けるワイヤ相互の接触及び
モールド工程に於けるワイヤ流れによるワイヤ相互の接
触等を大巾に改善出来るリードフレーム構造を提供出来
たものである。Since the lead frame according to the present invention three-dimensionally separates the bonded wires in addition to the conventional planar separation, the mutual contact of the wires during bonding and the mutual contact of the wires due to the wire flow during the molding process. It was possible to provide a lead frame structure that can greatly improve the above.
以上説明したように、本考案によれば、インナーリード
側に於けるワイヤ間隔を少なくとも２倍とれ、かつ上下
に分離していることから、ワイヤ相互の接触による不良
発生を大巾に減少出来、また高密度なワイヤボンディン
グが可能となる。As described above, according to the present invention, since the wire spacing on the inner lead side can be at least doubled and separated vertically, the occurrence of defects due to mutual contact of wires can be greatly reduced. In addition, high-density wire bonding becomes possible.
第１図は本考案によるリードフレームの一実施例の断面
図、第２図は従来構造のリードフレームを示す断面図、
第３図は本考案によるリードフレームの上面図、第４図
は本考案によるリードフレームの第２群インナーリード
を立体形成する工程を示した断面図、第５図は本考案に
よるリードフレームの第２群インナーリードをワイヤボ
ンディングに際し、裏打ちする方法の一実施例の断面図
である。 １……第２群インナーリード、２……第１群インナーリ
ード、３……ワイヤ、４……接続電極、５……半導体素
子、６……アイランド、７……インナーリード、８……
リードフレーム。FIG. 1 is a sectional view of an embodiment of a lead frame according to the present invention, and FIG. 2 is a sectional view showing a lead frame having a conventional structure,
FIG. 3 is a top view of the lead frame according to the present invention, FIG. 4 is a sectional view showing a process of three-dimensionally forming the second group inner leads of the lead frame according to the present invention, and FIG. 5 is a sectional view of the lead frame according to the present invention. FIG. 6 is a cross-sectional view of an example of a method of lining a second group inner lead during wire bonding. 1 ... 2nd group inner lead, 2 ... 1st group inner lead, 3 ... wire, 4 ... connection electrode, 5 ... semiconductor element, 6 ... island, 7 ... inner lead, 8 ...
Lead frame.
Claims (1)
を接着固定し、半導体素子の接続電極とインナーリード
とをワイヤを用いて接続するリードフレームにおいて、 インナーリードは第１群インナーリードと第２群インナ
ーリードとからなり、第２群インナーリードは第１群イ
ンナーリードより高さが高く、かつ第２群インナーリー
ド先端位置は第１群インナーリード先端位置より後退し
た位置にあり、 接続電極は半導体素子の外周部に２列に設け、最外周の
接続電極と第１群インナーリード先端とを接続し、最外
周の接続電極の内側の接続電極と第２群インナーリード
先端とを接続することを特徴とするリードフレーム。1. A lead frame in which a semiconductor element is adhesively fixed to an island of a lead frame and a connecting electrode of the semiconductor element and an inner lead are connected by a wire, wherein the inner lead is a first group inner lead and a second group inner The second group inner lead is higher in height than the first group inner lead, the second group inner lead tip position is set back from the first group inner lead tip position, and the connection electrode is a semiconductor element. Are provided in two rows on the outer peripheral portion, and the outermost peripheral connection electrode and the first group inner lead tip are connected, and the connection electrode inside the outermost connection electrode and the second group inner lead tip are connected. And lead frame.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP1987079211U JPH0739243Y2 (en) | 1987-05-26 | 1987-05-26 | Lead frame |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP1987079211U JPH0739243Y2 (en) | 1987-05-26 | 1987-05-26 | Lead frame |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS63187352U JPS63187352U (en) | 1988-11-30 |
| JPH0739243Y2 true JPH0739243Y2 (en) | 1995-09-06 |
Family
ID=30928861
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP1987079211U Expired - Lifetime JPH0739243Y2 (en) | 1987-05-26 | 1987-05-26 | Lead frame |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH0739243Y2 (en) |
Families Citing this family (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| WO2007015435A1 (en) * | 2005-08-01 | 2007-02-08 | Matsushita Electric Industrial Co., Ltd. | Semiconductor device |
Family Cites Families (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US3766852A (en) * | 1972-05-15 | 1973-10-23 | Gen Electric | Rebound motion controlling apparatus |
| JPS5019404U (en) * | 1973-06-15 | 1975-03-05 | ||
| JPS5198963A (en) * | 1975-02-26 | 1976-08-31 |
-
1987
- 1987-05-26 JP JP1987079211U patent/JPH0739243Y2/en not_active Expired - Lifetime
Also Published As
| Publication number | Publication date |
|---|---|
| JPS63187352U (en) | 1988-11-30 |
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