JPH0738435A - Delay circuit - Google Patents

Abstract

PURPOSE:To make a time constant of a variable integration circuit of an A/D converter coincident with that of a D/A converter. CONSTITUTION:An adder circuit 20, a quantization circuit 22 and a variable integration circuit 24 make A/D conversion and the result is stored in a memory 12. Then the time constant of the variable integration circuit is controlled by a control circuit 26. On the other hand, data from the memory are integrated by a variable integration circuit 28 to obtain an analog signal. In this case, control data from the control circuit 26 are sent to a control circuit 34 via a memory 32 and the control circuit 34 uses control data to be sent to control a time constant of the variable integration circuit 28.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an A / D converter, a memory and a delay circuit using a D / A converter used for generating surround sound of an audio device.

[0002]

2. Description of the Related Art Conventionally, a surround sound of an audio device is generated by delaying a reproduced sound for a predetermined time and attenuating it. Then, there are a stadium mode, a church mode, etc. as a mode at the time of reproducing, and the reproduced sound delayed by different methods is superimposed.

As a delay circuit used for such a purpose, there is a delay circuit as shown in FIG. In this circuit, the analog reproduction signal is once converted into digital data by the A / D converter 10 and stored in the memory 12. In addition, the data read from the memory 12 is stored in the D / A converter 1
In 4, it is converted back into analog data. Then, in this circuit, the write time and the read time to the memory 12 are made different, and this difference becomes the delay time.

The A / D converter 10 shown in FIG.
The one shown in 0 is used. That is, this A /
The D converter 10 includes an adder 20, a quantizer 22, a variable integration circuit 24, and a control circuit 26, and the analog output of the variable integration circuit 24 is fed back to the adder 20 to which an analog signal is input. The quantizer 22 is composed of a comparator 22a that outputs H or L according to the voltage of an input signal and a latch circuit 22b that latches the output of the comparator 22a according to a predetermined clock. Convert to signal. The variable integrator circuit 24 integrates the output from the quantizer 22 to obtain an analog signal corresponding to the input signal. Then, the variable integration circuit 2
Since the output of 4 is fed back to the adder 20,
When the difference between the two signals is taken in the adder 20 and the input signal is unchanged, the output of the quantizer 22 becomes a signal in which H and L are alternately repeated.

On the other hand, the control unit 26 changes the time constant in the variable integration circuit 24 according to the output state of the quantizer 22. That is, when the output level of the adder 20 is high and the output of the quantizer 22 is biased to "0" or "1", the time constant of the variable integrator circuit 24 is decreased and the adder 2
When the output level of 0 is small and "0" and "1" are balanced in the output of the quantizer 22, the variable integration circuit 24
Increase the time constant of. With such control, it is possible to increase the time constant during silence and suppress the generation of high-frequency noise, and to reduce the time constant when the input signal changes to sufficiently output high frequencies. it can.

On the other hand, the D / A converter 14 is composed of a latch circuit 27, a variable integrator circuit 28 and a control circuit 29, as shown in FIG. 11, and has a pulse train form obtained by reading from the memory 12. The input signal is latched by the latch circuit 27 and then integrated by the variable integration circuit 28 to obtain an analog signal. Here, the time constant in the variable integration circuit 28 is controlled by the signal from the control circuit 29.
The control circuit 29 has the same configuration as the control circuit 26 described above. That is, detecting the level of the input signal,
In response to this, the time constant of the variable integration circuit 28 is controlled. Since the input signal and the output signal of the memory 12 are basically the same, the time constant of the variable integrator circuit 28 can be matched with the time constant of the variable integrator circuit 24 by such control.
The same signal as the input signal can be delayed by a predetermined time and output.

[0007]

However, in such a conventional delay circuit, the conversion characteristics of the A / D converter and the D
There is a problem that the conversion characteristics of the A / A converter cannot be completely matched with each other, a level change or the like occurs, and the input analog signal and the output analog signal do not match. That is, although analog circuits such as CR low pass filters are generally used as the control circuits 26 and 29, the characteristics of these circuits change due to temperature changes and the like. Therefore, it is difficult to completely match the characteristics of the two control circuits 26 and 29, and the signals do not match.

The present invention has been made to solve the above problems, and an object of the present invention is to provide a delay circuit in which an input signal and an output signal can be easily matched.

[0009]

A time constant control circuit according to the present invention is an A / D converter for converting an input analog signal into a pulse train type signal, and an output state of a pulse train type signal output. A / D converter whose conversion characteristics are controlled in accordance with the above, a memory for storing a pulse train type signal output from this A / D converter as 1 and 0 data, and a pulse train output from the memory A D / A converter for converting a signal in the form of an analog signal, and a transmission means for transmitting data regarding conversion characteristics of the A / D converter to the D / A converter; The converter is characterized in that its conversion characteristic is controlled according to the conversion characteristic data in the A / D converter transmitted through the transmission means.

The A / D converter includes a quantizer circuit for quantizing an analog signal and outputting a signal in the form of a pulse signal train, and a variable integrator circuit for integrating the output of the quantizer circuit with an arbitrary time constant. And an adder circuit that adds the input analog signal and the output of the variable integrator circuit and supplies the output to the quantizer circuit, and a change direction that detects whether the change of the input signal is large or small. The D / A converter includes a detection unit and a control unit that changes the time constant of the variable integration circuit according to the detected direction of change, and the D / A converter integrates the pulse train type signal with an arbitrary time constant. It is characterized by including a circuit and control means for changing the time constant of the variable integrator circuit according to the conversion characteristic transmitted through the transmission means.

[0011]

In this way, the conversion characteristic of the D / A converter is controlled according to the conversion characteristic data of the A / D converter. Therefore, it is easy to match the conversion characteristics of both converters, and the input analog signal and the output analog signal can be matched.

Further, the conversion characteristics can be matched by making the time constants of the variable integrator circuits of the A / D converter and the D / A converter the same. In particular, A
By forming the change amount detecting means and control means of the D / A converter by a digital circuit and supplying the data for controlling the variable integrator circuit obtained here to the D / A converter side, a very accurate value can be obtained. The conversion characteristics can be adjusted. A memory, for example, can be used to transmit this data. If the control means on the D / A converter side is also formed as a digital circuit, suitable time constant control can be performed using the supplied digital data.

[0013]

Embodiments of the present invention will be described below with reference to the drawings. FIG. 1 is a block diagram showing the overall configuration of the delay circuit of the embodiment, which has a memory 32 for transmitting time constant control data from the A / D side to the D / A side. The control circuit 26 on the A / D side is composed of a digital circuit, and the output of the time constant control data is the memory 3
Stored in 2. The data in the memory 32 is read out in synchronization with the actual data read out from the memory 12 and supplied to the control circuit 34. Therefore, the control circuit 34 only needs to control the time constant of the variable integrator circuit 28 based on the supplied data, and does not need a circuit for level detection or the like.

As described above, since the time constant control data on the A / D side is supplied to the D / A side via the memory 32 to control the variable integrator circuit on the D / A side, the A / D side and the D / A side are controlled. The conversion characteristics on the side can be accurately matched, and a suitable delay circuit can be provided. Furthermore, since the time constant control data is transmitted via the memory 32, it is easy to synchronize with the actual data transmitted via the memory 12.

In this embodiment, the control circuit 26 is composed of a digital circuit. FIG. 2 shows the configuration of the main part of the control circuit 26. The signal in the form of a pulse train, which is the output of the quantization circuit 22, is input from the input terminal 40. The input signal from the input terminal 40 is input to the D input terminal of the D flip-flop 42, and the CL of the D flip-flop 42 is input.
A predetermined clock is input to the input terminal. The Q output of the D flip-flop 42 is input to one input terminal of the NAND gate 44. A clock is input to the other input terminal of the NAND gate 44 via an inverter 46. These D flip-flop 42 and NAND gate 44
And the inverter 46 is an input signal sampling circuit 4
Make up 8. The output of the NAND gate 44 is inverted and then input to the CL input terminal of the counter 50, and the output of the sampling circuit 48 is counted by the counter 50.

The clock is input to the timer 52, which counts the clock and generates an output signal when a predetermined time has elapsed. The output signal of the timer 52 is input to the D input terminal of the D flip-flop 54, and the clock is supplied to the CL input terminal of the D flip-flop 54. Therefore, the D flip-flop 54
The output of the timer 52 is held at. The Q output of the D flip-flop 54 is input to one input terminal of the NAND gate 56, and the inverted clock is input to the other input terminal of the NAND gate 56. And Nand Gate 56
Is inverted and supplied to the reset terminal of the counter 50. Therefore, the counter 50 is reset when the timer times out. The output of the timer 52 is C
D flip-flop 5 whose clock is supplied to the L input terminal
It is also supplied to the D input terminal of 8. Therefore, the output of the timer 52 is also held in the D flip-flop 58.

On the other hand, the output of the counter 50 is supplied to the D input terminal of the D flip-flop 60, and the CL output terminal of the D flip-flop 60 is supplied with the Q output of the D flip-flop 54. Therefore, the output of the counter 50 is latched in the D flip-flop 60 by the time-up output of the timer 52. Then, the Q outputs of the D flip-flops 58 and 60 are supplied to the time constant control circuit 62.

Next, the operation of the circuit shown in FIG. 2 will be described. The input signal in the form of a pulse train, which is the output of the quantization circuit 22 applied to the input terminal 40, is input to the sampling circuit 48.
At, the sampling is performed by the clock signal applied to the CL terminal. The clock signal is a signal having a frequency sufficiently higher than that of the input signal. On the other hand, the clock signal is counted by the timer 52, and when a predetermined number of clock signals are counted (when a predetermined time elapses),
The output terminal outputs the H level to the + terminal and the L level to the-terminal. Then, the D flip-flop 54 outputs a signal which becomes H for only one clock after the time is up, and the D flip-flop 58 outputs a signal which becomes L for only one clock after the time is up.

The counter 50 counts the output signals from the sampling circuit 48 for a predetermined time set by the timer 52. Here, the sampling circuit 48
The D flip-flop 42 of (3) takes in the input signal at the rising edge of the clock signal. The NAND gate supplies H to the counter 50 when the clock signal is L and the output of the D flip-flop 42 is H. Therefore, the count value corresponding to the H time of the input signal is set in the counter 50. That is, when the input signal includes many H-level portions, the number counted by the counter 50 increases, and when the input signals include many L-level portions,
The number to be counted is reduced. The output of the NAND gate 56 is inverted and supplied to the reset terminal of the counter 50. Then, the NAND gate 56 outputs H when H of the output due to the time-out of the timer 52 is taken into the D flip-flop 54 and the clock signal becomes L. Therefore, the counter 50 is reset by the time-out of the timer 52.

On the other hand, when H due to the time-up of the timer 50 is taken into the D flip-flop 54, this H
Is supplied to the CL terminal of the D flip-flop 60, and the D flip-flop 60 takes in the output of the counter 50 and outputs it to the Q output terminal. The counter 50 is, for example, as shown in FIG.
As shown in FIG. 3, it is composed of 4 bits and has a decoder section for generating an output. In the case of FIG. 3, an exclusive OR gate 70 whose input is connected to the Q output of the 3rd bit and the 4th bit is provided as a decoder unit. Further, FIG. 4 shows another example of the counter 50,
The decoder unit has a first AND gate 72 whose input is connected to the inverted Q output of the second bit, the inverted Q output of the third bit, and the Q output of the fourth bit, and the input having the Q output of the second bit and 3 A second AND gate 74 connected to the Q output of the bit and the inverted Q output of the fourth bit, and an exclusive OR gate 26 to which the outputs of the first and second AND gates 72 and 74 are applied .

In the case of FIG. 3, the exclusive OR gate 70 of the counter 50 generates an H level output when only one of the Q outputs of the 3rd bit and the 4th bit is at the H level, and otherwise outputs L level. Raise the level. The state is shown in the output 1 of FIG. As a result, the input terminal 40
When the input signal (output of the quantization circuit 22) applied to the signal is a signal having many H level components or a signal having many L level components, an L level is generated, and the H level and the L level are almost the same. If the signals are of equal proportion, an H level is generated. Therefore, the counter 50 outputs the L level when the state of the input signal changes. Further, in the case of FIG. 4, the output of the counter 50 becomes the output 2 of FIG. As described above, the range in which the H level is output is narrower when the counter 50 of FIG. 4 is used.

The output of the counter 50 held by the D flip-flop 60 is as up / down data.
It is applied as data of the time constant control circuit 62. That is, the up data for decreasing the time constant is supplied to the time constant control circuit 62 as L, and the down data for increasing the time constant is supplied to H. On the other hand, the output of the D flip-flop 58 is applied as a clock to the time constant control circuit 62.

Next, the time constant control circuit 62 is composed of a normal counter. That is, the H level supplied from the D flip-flop 60 is counted using the signal supplied from the D flip-flop 58 as a clock, and when the predetermined value (for example, several bits) is reached, the time constant of the variable integrator circuit 24 is controlled. Generate a signal to For example, the output L of the D flip-flop 60 is sequentially counted, and when the counter counts up, the time constant of the variable integrator circuit 24 is reduced by a predetermined control amount. Therefore, when the output from the D flip-flop 60 continues to be L, the time constant of the variable integrator circuit 24 decreases accordingly.

Then, the time constant control data output from the time constant control circuit 62 is transferred to the memory 12 via the memory 32.
Delayed by the same amount as the read data from the control circuit 3
4 is transmitted. Therefore, the control circuit 34 controls the variable integrator circuit 28 according to the supplied time constant control data,
The time constants in the variable integration circuits on the A / D side and the D / A side are controlled to be the same. This allows the signal levels of the input signal and the output signal to be matched. In particular, suitable delay can be performed even when the level of the input signal changes greatly.

Although the final output of the control circuit 26 is transmitted from the A / D side to the D / A side in the above example, the present invention is not limited to this, and the value of the counter may be transmitted. Also,
The output signal of the counter 50 may be transmitted. In this case, the memory 32 can be composed of a shift register that delays for a predetermined time.

FIG. 6 shows a configuration example of the time constant control circuit 62. In this example, the number of bits of the internal counter is changed between up-counting and down-counting. That is, each bit of the counter has a D flip-flop 80 and an exclusive OR gate 82 connected to the input side of the D input terminal of the D flip-flop 80.
And the Q output of the D flip-flop 80 is output via the exclusive OR gate 84 and the AND gate 86. In addition, the exclusive OR gate 82
The Q output of the D flip-flop 80 is input to one input terminal of the D flip-flop 60, and the output of the D flip-flop 60 is input to one input terminal of the exclusive OR gate 84.

The other input terminals of the exclusive OR gate 82 and the AND gate 86 of the LSB are pulled up to the power supply. Further, the exclusive OR gate 82 and the AND gate 8 of bits other than the LSB are
The bit output of the previous stage, that is, the output of the AND gate 86 of the bit of the previous stage is input to the other input terminal of 6.
Also, the preset terminal of the D flip-flop 80 of the dummy bit (“1” is preset by L level input)
The output of the D flip-flop 60 is inverted and input to. Therefore, when the output of the D flip-flop 60 is at the L level (when the time constant is changed to a smaller direction), the D flip-flops 80 of the dummy bits are all set to H, that is, "1", and the 3 bits of the dummy bit are set. The output of the AND gate 86 of the eye also becomes H. Further, one input terminal of the exclusive OR gate 84 of each bit is
An L level signal is supplied. Therefore, in the control bit, the H of the Q output of the flip-flop 80 is transmitted as a carry through the AND gate 86 and the exclusive OR gate 82. Then, in this state, the output of the flip-flop 58 is supplied to the flip-flop 80 of the control bit as a clock, so that the control bit operates as a normal 2-bit up counter.

On the other hand, the output of the D flip-flop 60 is H
For level (when changing the time constant in the larger direction),
The signal supplied to the preset terminal of the dummy bit flip-flop 80 is at the L level. Therefore, the preset operation is not performed in the flip-flop 80, and all the normal operations are performed. Then, an H level signal is supplied to one input terminal of the exclusive OR gate 84 for each bit. Therefore, in all the bits, the L of the Q output of the flip-flop 80 is transmitted as a carry for setting the D flip-flop 80 to the L through the H output of the exclusive OR gate 84 and the H output of the AND gate 86. Then, in this state, the output of the flip-flop 58 is supplied as a clock to the flip-flop 80 of the control bit, so that the control bit operates as a normal down counter.

Here, the counting state is shown in FIG. As described above, the time constant control circuit of the present embodiment operates as a 2-bit counter when counting up, and as a 5-bit counter when counting down. Therefore, for example, when the voice output becomes large from the silent state (at the time of attack), it operates as a 2-bit up counter, and when the control bit “1” or “1” is output, the time constant is set. Output the signal to make it smaller. on the other hand,
When the audio output becomes small (at the time of recovery), it operates as a 5-bit down counter and outputs a signal for increasing the time constant when the control bits "0" and "0" are output. Therefore, the change in the time constant changes rapidly during attack and gradually during recovery, as shown in FIG.

[0030]

As described above, according to the time constant control circuit of the present invention, the time constant of the variable integrator circuit is transmitted from the A / D side to the D / A side. Therefore, it is easy to match the conversion characteristics of the quantity converter, and the input analog signal and the output analog signal can be matched. In particular, A
The conversion characteristics can be matched by making the time constants of the addition and integration circuits of the / D converter and the D / A converter the same.

[Brief description of drawings]

FIG. 1 is a block diagram showing an overall configuration of a delay circuit.

FIG. 2 is a block diagram showing a configuration of a main part of a control circuit.

FIG. 3 is a block diagram showing an example of the configuration of a counter 50.

FIG. 4 is a block diagram showing another example of the configuration of the counter 50.

FIG. 5 is an explanatory diagram showing a count state of a counter 50.

FIG. 6 is a block diagram showing a configuration of an example of a time constant control circuit.

FIG. 7 is an explanatory diagram showing states of flip-flops in the time constant control circuit.

FIG. 8 is an explanatory diagram showing a changing state of a time constant.

FIG. 9 is a block diagram showing a schematic configuration of a delay circuit.

FIG. 10 is a block diagram showing a configuration example of an A / D converter.

FIG. 11 is a block diagram showing a configuration example of a D / A converter.

[Explanation of symbols]

 10 A / D converter 12 memory 14 D / A 24 variable integration circuit 26 control circuit 28 variable integration circuit 32 memory 34 control circuit

Claims (2)

[Claims] 1. An A / D converter for converting an input analog signal into a pulse train type signal, the conversion characteristic of which is controlled according to the output state of the output pulse train type signal. A D converter, a memory for storing the pulse train type signal output from the A / D converter as 1 and 0 data, and a D / A for converting the pulse train type signal output from the memory into an analog signal. A converter, and a transmission means for transmitting data regarding conversion characteristics in the A / D converter to the D / A converter, wherein the D / A converter transmits the A signal transmitted through the transmission means. / D
A delay circuit characterized in that the conversion characteristic is controlled according to the conversion characteristic data in the converter. 2. The delay circuit according to claim 1, wherein the A / D converter is a quantizer circuit for quantizing an analog signal and outputting a signal in the form of a pulse signal train, and an output of the quantizer circuit is arbitrary. The variable integrator circuit that integrates with the time constant of, the adder circuit that adds the input analog signal and the output of the variable integrator circuit, and supplies the output to the above quantizer circuit. And a control means for changing the time constant of the variable integrator circuit according to the detected change direction. The D / A converter is of a pulse train type. A variable integrator circuit that integrates a signal with an arbitrary time constant, and, according to the conversion characteristics transmitted through the transmission means,
A delay circuit comprising: a control unit that changes a time constant of the variable integrator circuit.