JPS60127837A - Data processor - Google Patents

Abstract

PURPOSE:To simplify the circuit constitution for suppressing large amplitude changes by adopting the circuit constitution calculating repetitively amplitude data and prescribed data. CONSTITUTION:When a mute release control circuit 43 is logical 1 and an input is given to a terminal 30 of an arithmetic circuit 37, an intermediate value between high reliability data and data from a latch 36 is calculated and otputted to a data selector 34. On the other hand, a calculated output data is fed again to the latch circuit 36. An intermediate value between the former intermediate data and data inputted to a terminal 31 is outputted at the next period T. Moreover, an intermediate value between the data outputted just before and the high reliability data inputted to the terminal 31 is outputted at the next T period. The data approaches gradually by repeating the procedure above to release the muting.

Description

[Detailed Description of the Invention] [Technical Field] The present invention relates to a data processing device, and particularly to a data processing device in which first data representing a signal amplitude at a certain point in time and second data representing reliability of the first data form a pair. The present invention relates to a device for processing a data series, and more specifically relates to an improvement in data processing for removing unnaturalness in t± output.

<Description of the prior art> Generally, on the digital signal reproducing device side and the
Correct reproduction of l/tsuta data may not be possible due to the occurrence of noise in the data transmission path. Generally, pulse-like noise is generated by this number, and in particular, depending on the location where a data error occurs in these data strings, it may be reproduced as excessive noise.

Therefore, an error correction code or an error detection code is added to the data string, and the playback device side receives 1. Noise countermeasures may be taken using a circuit for reproducing correct l,% data at X, a previous value hold circuit, and furthermore an intermediate value interpolation circuit.

However, with these noise countermeasures, large data loss such as l/) may occur which cannot be suppressed completely. In this case, the data that is output in a time-series manner is also long, resulting in data with low reliability over a period of time. For example, if a large dropout occurs in the data of a digital signal obtained by converting an audio signal into PCM, abnormal sound will occur. Therefore, a conventional method has been developed in which the output data is muted when the flag data indicating the reliability of each data shows low reliability for a long period of time, using the error correction code and error detection code described above. Sometimes used together.

However, when muting data, if the signal amplitude level of output data is muted all at once from the signal amplitude level to 0 level, a sudden change in amplitude occurs. This is particularly unfavorable for audio signals. In order to prevent this, there has conventionally been a method of counting the aforementioned flag data for a certain period of time and gradually muting by setting a plurality of attenuation amounts for attenuating the data according to the value of this count. This method is configured to mute data by gradually attenuating it, so there is no sudden amplitude change. However, in general, this method requires extremely complicated circuits, and therefore cannot be applied to devices 6 that are required to be inexpensive and compact, such as home appliances.

<Object of the Invention> In view of the above-mentioned drawbacks of the conventional device, the present invention aims to gradually mute the data representing the signal amplitude and to reduce the unnatural
An object of the present invention is to provide a data processing device that can realize an extremely simple circuit configuration suitable for eliminating the problem.

<Explanation based on examples> Hereinafter, the present invention will be explained in detail using Examples.

FIG. 1 is a diagram showing the main part configuration of a data processing device as an embodiment of the misfire 11. In FIG. 1, 30 is a terminal to which n-bit data representing the signal amplitude is sequentially supplied in time series, and 31 is a terminal to which flag data indicating the reliability of the n-bit data supplied to the terminal 30 is input. It is. 3
2, 33° and 34.35 are data selectors, 36 is a latch circuit that holds the output data of the selector 32 for one sample period of n-bit data, and 37 is the average of the output data of the latch circuit 36 and the output data of the data selector 35. A calculation circuit 38 calculates and outputs value data, a circuit 38 outputs all 0° data, and a control circuit 39 controls each data selector 32, 33, 34, and 35.

Further, 40 indicates the flag data supplied to the terminal 31.
This is a launch circuit that holds bit data for one sample period (T) and supplies it to the control circuit 39. When the flag data is 1", the counter 41 reads it as l-L,"o
The 4u flag data is reset when the reliability of the paired n focus data is low, and when it is high, it is reset.
shall be.

Also, if the count value of the counter is thicker than 9.1, C11 + 2
) or less, -1-start i control circuit 42i±'
The mute release control circuit 43 outputs "1" for the period of lyT when the counter 41 is reset from a value greater than 1+ by 5. However, nl, 1
2 is an integer greater than or equal to 1, for example, = 31, llz =
8, it is convenient to use a ζ inary counter as the counter 41.

FIG. 2 is a timing chart showing the waveforms of each part of FIG. 1 (i) to (x), and Table 1 shows the inputs a, b, and
It is a table showing the relationship between c and d and outputs B', D, F, and H.

Note that when each output shown at B, D, F, and H is "1", the data selectors 32, 33, 34, and 35 are set to B, shown in the first diagram, respectively.
Select and output the data input to the D, F, and H sides. Note that in Table 1, only the seven combinations shown in Table 1 can be considered as inputs.

Table 1, Figure 3 shows a control circuit 39 that realizes the input/output relationship as described above.
It is a circuit diagram showing an example. In FIG. 2, data marked with O is highly reliable data, and data marked with △ is replaced data.

The operation will be explained below using FIG. 2 and Table 1.

First, low reliability n-bit data of 4 sentences or less is connected to terminal l.
Consider the case where the At this time, data selector 3
2 selects the n-bit data supplied to the B side, and 33 selects the n-bit data supplied to the C side, so the data selector 32 always selects the latch 3.
At step 6, data delayed by a period of 1T is output. Furthermore, since the data supplied to the E side is output to the data selector 34, the data that was output from the terminal 50 before IT is once again output from the output terminal 50. However, normally, even when outputting highly reliable data, the configuration is such that pre-IT data is always output, so when the reliability changes, the pre-IT data held in the latch circuit 36 is Highly reliable data is output.

Then, in the next T period, the data from 2T ago held by the latch circuit 36 will be output again.

During the T period when the n-bit data input to the input terminal 30 becomes highly reliable, the data selector 32 selects the data input to the A side, and the data selector 34 selects the data input to the arithmetic circuit 37. Select the data to be output. The output data of the arithmetic circuit 37 becomes intermediate value data between the highly reliable data output at the next T and the held data, and so-called intermediate value interpolation is performed.

Next, the operation during muting will be explained. First, during the mute start period, that is, when the output of the mute start control circuit 42 is 1°, the data selector 35 is all set to 0°.
'The data is supplied to the arithmetic circuit 37. In the arithmetic circuit 37, the data is the average value of the all "'0" data and the data held at the previous value, that is, the data 172 is held at the previous value.

This data is stored in the data selector 33. Data selector 32
The signal is held in the latch circuit 36 via the data selector 34, and is output via the E side of the data selector 34 in the next T period.

On the other hand, this output data is again supplied to the arithmetic circuit 37, and the average value with the all "0" data is taken. At this time, the output of the arithmetic circuit 37 is approximately 1/22 of the data whose previous value was held. Then, the data that is sequentially output is 1/23.1/2 of the data whose previous value was held.
4 ・φ fist 1/2 + 1. In the case of 8-bit data, the data converges to 0' when n=8 (=cross 2).

Next, the operation when mu 1 is released will be explained.

When the output (iv) of the mute release control circuit 43 is "l"', the arithmetic circuit 37 distinguishes between the highly reliable data input to the terminal 3O and the data output from the latch 36, that is, all "0" data. An intermediate value is calculated and outputted via the F side of the data selector 34. On the other hand, this arithmetic circuit 37
The output data of data selector 33. The signal is again supplied to the latch circuit 36 via the data selector 32. Next T
During the period, the intermediate value between this intermediate value data and the data manually input to the terminal 31 is output, and furthermore, in the next T period, the data output immediately before is input to the terminal 31. An intermediate value with high reliability data is output. By repeating this, unless the data is extremely high-frequency and large-amplitude, it will gradually approach data with a high reliability of 1.1, and muting will be canceled.

1] According to the configuration as described above, at the start of muting, the average of all "0'" data and the data representing the signal amplitude output immediately before is output while being repeatedly calculated. The data representing the signal amplitude gradually decreases to O
Good muting can be achieved by approaching . Further, as for the circuit configuration, since the conventional circuit for holding the previous value and interpolating the intermediate value can be used almost as is, it is extremely easy and can be made small-scale.

In the above configuration, the output of the arithmetic circuit 37 is the average data of the output of the launch circuit 36 and the output of the data selector 35, but even with this, if the amplitude change at the start of muting is too large, For example, the output data of the latch circuit 36 is set to 2. The output data of the selector 35 may be mixed at a ratio of 1. In other words, generally speaking, when starting mute, the arithmetic circuit 37 should be configured to output data equal to 1/a of the output of the latch circuit 36 (a is a real number of 1 or more); in this case, the outputs are sequential. 1/a, 1
/a2*·φ1/a''.However, in this case, it is preferable that the value of the above-mentioned 2 be made smaller as the value of a becomes larger, and larger as the value of a becomes smaller.

In addition, in the above example, the average with all "0" data is repeatedly taken, but if necessary, the average with other predetermined data may be taken.This is not as good as muting, for example. This is effective when unreliable data is supplied several times in a row.For example, in a circuit system that always outputs data 1T ago, the previous hold value can be determined in advance, so the previous value held immediately before the data to be held is By repeatedly obtaining and outputting the data and the previous value hold value as predetermined data (several times), it is possible to eliminate the unnaturalness of the signal due to the previous value hold.

Explanation of Effects> As explained in detail using the embodiments above, the data processing device of the present invention has a circuit configuration that can repeatedly calculate certain amplitude data and predetermined data, so that large signals can be obtained. It is possible to remove unnaturalness such as amplitude changes. This is particularly effective in suppressing large amplitude changes at the start of muting because this can be achieved with an extremely simple circuit configuration.

[Brief explanation of the drawing]

FIG. 1 is a diagram showing the main part configuration of a data processing device according to an embodiment of the present invention, FIG. 2 is a timing chart showing waveforms of the first intermediate section, and FIG. 3 is a control circuit in FIG. 1. It is a circuit diagram showing an example. 30 is a first data input terminal, 31 is a second data input terminal, 32, 33, 34.35 are respective data selectors, 36 is a latch circuit, 37 is an arithmetic circuit, and 38 is an all-input terminal for predetermined data. 39 is a control circuit, 4o is a latch circuit, 41 is a counter, 42 is a start control circuit, 43 is a mute release f11m
This is a control circuit. Continuing from page 1 @ Inventor Masaaki Takei @ Inventor Ken Nagasawa - Canon Co., Ltd. Tamagawa Office, 77 Hata, Shimonoge, Takatsu-ku, Kawasaki City, Tamagawa, Canon Co., Ltd. 77 Hata, Shimonoge, Takatsu-ku, Kawasaki City, Tamagawa, Canon

Claims (1)

[Claims] A device that processes a data series in which first data representing a signal amplitude at a certain point in time and second data representing reliability of the first data form a pair, and which operates on two input data. a calculation means for outputting the data obtained by the calculation means; means for supplying predetermined data as input data for one of the calculation means; and a selection for selecting and outputting one of the first data and the output data of the calculation means. A data processing device comprising means for holding the output data of the selection means and supplying it as input data to the other calculation means, and means for controlling the selection means in accordance with the second data.