JPS60127838A - Data processor - Google Patents

Abstract

PURPOSE:To prevent large amplitude changes of a signal by repeating the processing of a calculated output between data representing a signal amplitude and data outputted just before. CONSTITUTION:A data selector 35 applies all 0 data to an arithmetic circuit 37 at the mute start period and outputs an average value 1/2 of a pre-value holding data. The data is held in a latch circuit 36, applied again to the arithmetic circuit 37, where the average value with the data of all 0 is taken, data of 1/2<2>-1/2<n> is outputted and muting is attained. When an output IV of a mute release control circuit 43 is logical 1, an intermediate value between the high reliability data and the all 0 from a terminal 30 is calculated and the result is outputted to a data selector 34. An intermediate value between the former intermediate value and an input data at a terminal 31 is outputted at the next T period. The resulting data approaches the high reliability data gradually by repeating it to release the muting.

Description

[Detailed Description of the Invention] [Technical Field] The present invention relates to a data processing device, and particularly to a data processing device in which first data representing a signal amplitude at a certain point in time and data from a vehicle 2 representing reliability of the first data form a pair. This invention relates to a device that processes a data series, and more specifically, to improving data processing for removing unnaturalness in the output. Correct data may not be reproduced due to the occurrence of noise in the transmission path. Although pulse-like noise is generated in general VC, it may be reproduced as excessive noise depending on the location where data errors occur particularly in these data strings.

Therefore, an error correction code or an error detection code is added to the data string, and noise countermeasures are taken on the playback device side using a circuit that plays back the correct data, a previous value bold circuit, and an intermediate value interpolation circuit. Sometimes it is done.

However, large data loss that cannot be suppressed by these noise countermeasures may occur.

In this case, the data that is output in a time-series manner also has low reliability over a long period of time. For example, audio signal 'k
If a large loss occurs in the data of the PcM digital signal, an abnormality will occur. Therefore, conventional methods have been used to generate data using the above-mentioned error correction code or error detection code, and mute the output data if the flag data indicating the reliability of each data is 1 or higher continuously for a long period of time, indicating low reliability. Sometimes used together.

However, when muting data, if the signal amplitude level of output data is muted all at once from the signal amplitude level to 0 level, a sudden change in amplitude occurs. This is particularly unfavorable for audio signals. In order to prevent this, there has conventionally been a method of counting the aforementioned flag data for a certain period of time, and gradually muting by setting a plurality of attenuation spears that attenuate the data according to the count value. This method is configured to mute data by gradually attenuating it, and then gradually cancel the muting, so there is no sudden change in amplitude.

However, in general, this method requires extremely complicated circuits, and therefore cannot be applied to devices such as home appliances that are required to be inexpensive and compact.

<Object of the Invention> In view of the drawbacks of the conventional devices described above, the present invention provides a data processing device having an extremely simple circuit configuration that prevents sudden amplitude changes from occurring even when muting data representing signal amplitude. The purpose is to provide

<Explanation based on examples> Hereinafter, the present invention will be explained in detail using Examples.

FIG. 1 is a diagram showing the main part configuration of a data processing apparatus as an embodiment of the present invention. In FIG. 1, 30 is a terminal to which n-bit data representing the signal amplitude is sequentially supplied in time series, and 31 is a terminal to which flag data indicating the reliability of the n-bit data supplied to the terminal 30 is input. It is. 32
33, 34, and 35 are data selectors, 36 is a latch circuit that holds the output data of the selector 32 for one sample period of n-bit data, and 37 is the average of the output data of the latch circuit 36 and the output data of the data selector 35. A calculation circuit for calculating and outputting value data, 38 a circuit for generating all "0" data, and 39 a control circuit for controlling each data selector 32, 33, 34, 35.

Further, 40 indicates the flag data supplied to the terminal 31.
A counter 41, which is a latch circuit that holds the bit data for one sample period and supplies it to the control circuit 39, counts when the flag data is ``1'' and is reset when it is 0''.

However, the flag data is set to "1" when the reliability of the pair of n-bit data is low, and set to "0" when the reliability is high. Further, when the count value of the counter is greater than 11 and less than or equal to (l++j'z), the mute start control circuit 42 outputs ゝゝ1''.
When reset from a larger value, it outputs "1" for the period of l and T.However, 1./+.

If 12 is an integer greater than or equal to 1, for example l,=31, and 1z=s, it is convenient to use a binary counter as the counter 41.

FIG. 2 is a timing chart showing the waveforms of each part of FIG. 1 (i) to (x), and Table 1 shows the inputs a, b, and
This is a table showing the relationship between c and d and outputs B, D, F, and H. Furthermore, when each output shown in B, D, F, and H is "1", the data selectors 32, 33, 34, and 35 are B and I shown in the first diagram, respectively.
), F, H side selects and outputs the data t″. In addition, in Table 1, the inputs are 7 shown in Table 1.
Only the following combinations can be considered.
It is a circuit diagram showing an example. In FIG. 2, data marked with O is highly reliable data, and data marked with △ is replaced data.

The operation will be explained below using FIG. 2 and Table 1.

First, the n-bit data with low reliability of less than l5 is the terminal 1.
Consider the case where the At this time, data selector 3
2 selects B and 3:( selects the n-bit data supplied to C1itl+, so the data selector 32 always outputs data delayed by the latch 36 for a period of 1T.

Also, since the data supplied to the E side is output to the data selector 34, the output terminal 50 outputs the data to the terminal 50 before IT.
The data that was output from i"t will be output again. However, even when outputting highly electrifying data, the configuration is such that the data from 1T ago is always output. When the reliability changes, the high reliability data before 1T held in the latch circuit 36 is output.

Then, in the next T period, the data 2T ago held by the latch circuit 36 will be output again.

During the T period when the n-bit data input to the input terminal 30 becomes highly reliable, the data selector 32 selects the data input to the A side, and the data selector 34 selects the data input from the arithmetic circuit 37. Select the data to be output. The output data of this arithmetic circuit 37 becomes intermediate value data between the highly reliable data output at the next T and the held data, and d-th intermediate value interpolation is performed.

Next, the operation during muting will be explained. First, during the mute start period, that is, when the output of the mute start control circuit 42 is "1", the data selector 35 is all "0".
The "data" is supplied to the arithmetic circuit 37. In the arithmetic circuit 37, the data is the average value of all "0" data and the data held at the previous value, that is, 1/2 of the data held at the previous value.

This data is stored in the data selector 33. Data selector 32
It is held in the latch circuit 36 via the data selector 34 and output via the E side of the data selector 34 in the next T period. On the other hand, this output data is again supplied to the arithmetic circuit 37, and the average value with the data of all 0 // is taken.The output of the arithmetic circuit 37 at this time is approximately 1/22 of the data whose previous value was held. becomes. And the data output in the next T period is also almost 1 of the data whose previous value was held.
/22. Then, around 1, the next data to be output is 1/2", 1/2' of the data whose previous value was held.
...1/2n. In the case of 8-pit data, n
=8 (=12), the data converges to ((0//).

Next, the operation when canceling mute will be explained.

When the output (4V) of the mute release control circuit 43 is "1", the arithmetic circuit 37 distinguishes between the highly reliable data input to the terminal 30 and the data output from the launch 36, that is, all "0" data. The intermediate value of . The signal is again supplied to the latch circuit 36 via the data selector 32.

In the next T period, the intermediate value between this intermediate value data and the data input to the terminal 31 is output, and in the next T period, the data output immediately before and the data input to the terminal 31 are output. The intermediate value between the high-reliability data and the current high-reliability data is output.By repeating this, unless the data is high-frequency, large-amplitude data for all culms, the mute will gradually approach high-reliability data and the mute will be released. Become.

According to the above configuration, when canceling mute, the average of the data representing the highly reliable signal amplitude and the data output immediately before is repeatedly calculated and output, so the output signal amplitude is The represented data gradually approaches 0, and muting can be canceled extremely well. Further, as for the circuit configuration, since the conventional pre-hold and intermediate value interpolation circuits can be used almost as they are, it is extremely easy and can be made small-scale.

In the above configuration, the output of the arithmetic circuit 37 is the average data of the output of the latch circuit 36 and the output of the data selector 35, but even with this, if the amplitude change at the start of muting is too large, For example, the output data of the latch circuit 36 may be mixed with the output data of the 2° selector 35 at a ratio of 1.

FIG. 4 is a diagram showing the main part configuration of a data processing device as another embodiment of the present invention. Components similar to those in FIG. 1 are given the same numbers. 30' is an input terminal to which data representing the signal amplitude is supplied; 49 is an OR gate; 51 is a mute control circuit; 52 and 53 are data selectors;
4゜55 are latch circuits, 56 is a mute circuit 557
is an arithmetic circuit.

FIG. 5 is a waveform diagram showing the waveforms of each part in FIGS. 4(a) to 4(f), and the operation will be explained below using FIG. 5. First, a method conventionally used for obtaining the output (d) of the mute circuit 56 will be explained.

The data selector 52 is controlled by the flag data (b) supplied to the terminal 31, and the flag data is "1".
That is, when the data being supplied to the terminal 30' indicates low reliability, the data input to the P side is output. P
The data inputted to f1411 is the data outputted from the selector 52 in the immediately preceding sampling period (1), which is hopped to the previous value by the latch circuit 54.

The mute control circuit 51 is configured so that the count value of the counter 41 is l.
5 or more, outputs X1'', operates the mute circuit 56, and mutes all data in the meantime.The signal waveform resulting from the data is shown in FIG. 5(d). The waveform shown in d) is data representing 11 signal amplitudes, and corresponds to the first data in the present invention,
The flag data supplied to the terminal 31 corresponds to the second data.

Now, the data shown in FIG. 5(d) shows a large amplitude change before and after the period muted by the mute circuit 56.

Here, the output of the OR gate 49 is l! after the start of muting. 2
The data selector 53 is configured to output the data input to the S side only when the output of the OR gate 49 is "1". At this time, the output of the data selector 53 is the data output from the selector 53 at the previous T and the mute circuit 5.
The output (t3) of 6 is calculated (for example, averaged) by the calculation circuit 57. Therefore, as shown in FIG. 5(f), an output without large amplitude changes can be obtained from the data selector 53. Of course, the same effect can be achieved even if the output of the data selector 53 is used as it is as the output from the terminal 50.

According to the data processing device having the above-described structure, the average (calculated output) of the data representing the signal amplitude and the data output immediately before muting can be repeatedly obtained when muting is started and when muting is canceled. It has become possible to suppress all sudden amplitude changes in output data.

In the configuration shown in FIG. 5, the output of the data selector 53 may be used as the data input to the S side, if necessary, other than when muting is started or canceled. For example, when unreliable data is supplied several times in succession to the extent that muting is insufficient, a large amplitude change in the signal caused by release of the previous value hold can be similarly removed.

<Description of Effects> As explained in detail using the embodiments above, the data processing device of the present invention is configured to be able to repeatedly obtain the calculation output of the data representing the signal amplitude and the data output immediately before. , it has become possible to remove unnaturalness such as large amplitude changes in the signal. In particular, when muting is performed, it is effective in suppressing large amplitude changes that occur before and after muting because it can be achieved with an extremely simple circuit configuration.

[Brief explanation of drawings]

FIG. 1 is a diagram showing the configuration of main parts of a data processing device according to an embodiment of the present invention, FIG. 2 is a timing chart showing waveforms of the section in FIG. 1, and FIG. 3 is a control circuit in FIG. 1. FIG. 4 is a circuit diagram showing an example. FIG. 4 is a diagram showing the main part configuration of a data processing device according to another embodiment of the present invention. FIG. 5 is a timing chart showing waveforms of each part in FIG. 30 is a first data input terminal, 31 is a second data input terminal, 32, 33, 34.35 are respective data selectors, 36 is a latch circuit, 37 is an arithmetic circuit, and 38 is an all-input terminal for predetermined data.ゝゝ0'' data generation circuit, 39 is a control circuit, 40 is a latch circuit, 41 is a counter, 42 is a neat start control circuit, 43 is a mute release control circuit,
51 is a mute control circuit, 52.53 is a data selector, 54.55 is a latch circuit, 56 is a mute circuit, 57
is an arithmetic circuit.

Claims (1)

[Claims] An apparatus for processing a data series in which first data representing the total signal amplitude at a certain point in time and second data representing reliability of the first data form a pair, wherein one of the two input data is the second data representing the reliability of the first data. a calculation means for outputting data obtained by calculating the two input data, which is the first data; a selection means for selecting and outputting one of the output data of the calculation means and the first data; a data processing device comprising: means for holding output data of the means and supplying it as input data to the other of the arithmetic means; and means for controlling the selection means in accordance with the second data;