JPS5954014A - Reproducing circuit of pcm signal - Google Patents

Abstract

PURPOSE:To prevent the quantizing noises for a non-sound period, by using the output of a dividing circuit for the 1st clock to control the output signal of a digital-audio converting circuit. CONSTITUTION:For a counter 4, an output QP is set at ''1'' when the value of the PCM signal corresponds to a non-sound period for a 2P<-1> period of clock DK. At the same time, the outputs of Q1-QP are initialized to ''0'' in response to a case where the non-sound period does not exist for three periods of the clock DK. An AND gate 9 obtains an AND between the inversion of the QP of a counter 4 and the clock DK and is connected to a clock input terminal CK of a D/A converting circuit 1. Therefore the circuit 1 stops the D/A conversion of the PCM signal when the QP of the counter 4 is set at ''1''. In such a way, the quantizing noises can be prevented in case a non-sound period is continued.

Description

[Detailed Description of the Invention] Does the present invention provide PCM signals? The present invention relates to a PCM signal reproducing circuit that performs digital-to-analog conversion and reproduces an acoustic signal.

PCM signal VC by time sampling the acoustic signal! An analog-to-digital (AD) conversion circuit is used to convert the data. The AD conversion circuit quantizes the input analog signal in amplitude and converts it into a digital signal.If the conversion bit is N, the amplitude of the input analog signal is quantized in a 2N quantization area, and the corresponding It is converted into a digital number PCM signal. If the ambiguity unit is kA (unit: volt), the maximum amplitude of the input analog signal needs to be A·2N. FIG. 1 is a time chart showing an example of the operation of the AD1 path when the amplitude of the input analog signal is small.

In FIG. 1, the horizontal lines (a), υ), (0) indicate the threshold values of the AD open circuit quantization area. Therefore, (a)
The space between and between Φ) and (0) is the electronic unit A described above. (
el) indicates the input acoustic signal waveform. T1-T4 are the time points of AD open circuit sampling. (d) is ADl! l!
The conversion output of the least significant bit of the l path is shown.

Now, as is clear from FIG. 1, the input acoustic signal has a very small f! value near one quantization area. This will result in AD open circuit quantization noise. In other words, even a slight noise fluctuation when there is no signal will cause AD open circuit quantization noise.
This results in a quantization noise variation corresponding to the lowest bit variation of the Dl path. In order to eliminate this noise fluctuation 2, the AC bias point Y of the input acoustic signal is intermediate between (a) and (b),
Or [Yes]) and (q), but the interval A between the quantization thresholds is 7. of the maximum amplitude of the input acoustic id.General KN is between 8 and 12, so A is a slight hit, and it is difficult to maintain it stably in the middle of the placement threshold due to temperature changes, changes over time, etc.

Pulsed noise is short in duration but relatively large in amplitude and, if sampled by chance, results in fluctuations in the least significant bit of the AD converter. When the acoustic signal is changing,
Although minute noise is not audibly harsh due to the masking effect, minute noise when there is no signal is extremely annoying.

The present invention provides circuit means for preventing the generation of such minute noise (quantization noise) when there is no signal, and will be described in detail below with reference to the drawings.

In Fig. 2, (1) is a DA conversion circuit, and the N-bit PCM signal (
P1 to Pw), the analog signal VC is converted based on the conversion clock applied to the lock terminal (CK). DK is P
This is a conversion clock for converting the CM signal QDA. (2) is a range detection circuit, which outputs a logic level of 11" when the edge of the PCM signal applied to the input terminals (11 to IN) corresponds to a silent period, and a logic level of '0' in other cases. Output terminal (Ql) outputs VC. (3) is a shift register, and the output [Q1] of the range detection circuit (2) is inputted to the data input terminal (D) vc via the inverter (5).
Clock DKK slave output (Qt) ((C) (QIVC
Shifted sequentially.

+71 is input connected to the (Ql), (Q2), and (Q3) outputs of the shift register (3) and is a 9-AND gate, and the output of the AND gate (7) becomes logic level 11", initializing the counter (4). The output of the counter (4) is Q
1 to Qp are all set to logic level 10''.

(8) is an AND gate, Qpf of counter (4)
When the output of the range detection circuit (2) is sl until the fl force reaches 1, the clock (DK) & clock input terminal (CK) of the counter (4) outputs VC. +4J is PCM signal value 2p of clock (DK)
- When corresponding to a silent period over 1 cycle, the Qp ratio output 11'' is 9, and DK (corresponding to when there is no silent period over 05 cycles, (Ql)...(Qp) Each output of is initialized to 10〃.

The AND gate (9) performs the logical product of the Qp ratio output inversion of the counter (4) and the DK clock), and the DA conversion circuit Fi1.
g, the clock input terminal (CK) of (1) is connected to the VC output. Therefore, when the Qp ratio output of the counter (4) is 1, 1 mW! (t) in terms of DAY is DAy6 of pCMig.
2 Stop.

With this configuration, when a silent period continues, DA conversion is not performed, and the acoustic signal 8 can be reproduced without the influence of noise fluctuations mixed into the input analog signal.

9. In Figure 2, the output of the reset input terminal (inverter +5) of the counter (4) may be connected,
In this case, it is possible to prevent noise fluctuations near the welfare threshold N when creating a PCM module by AD converting an input analog signal.

Furthermore, when the QP output of the counter (4) is changed, the conversion clock of the DA conversion circuit is stopped as shown in FIG. Even if the PCM signal value corresponding to the silent period of the analog signal is switched to the value of the PCM signal corresponding to the silent period of the analog signal, it functions in exactly the same way as described above.

Similarly, even if the acoustic signal reproduced by the D-converter circuit (1) is controlled by switching, for example, a transistor element using the Qp output of the counter (4) so that an appropriate fixed potential is supplied, Works the same way. Furthermore, it is clear that the counter (4) may be constructed from a shift register.

With such a configuration, the present invention can achieve reproduction of a PCM signal without generating VC quantization noise during the silent period.

[Brief explanation of drawings]

FIG. 1 is a time chart showing an example of the operation of an analog-to-digital conversion circuit when fluctuations in an input analog signal are small, and FIG. 2 is a block circuit diagram of a PCM signal reproducing circuit of the present invention. (1)...Digital-to-analog conversion circuit, (2J-
... Range detection circuit, (3) ... Frequency division circuit, (4) ...
·counter. −1″ ″′ Quantity −N ″′ ″′ Ward (1, CL
(LO 9 machines

Claims (3)

[Claims] (1) A circuit that reproduces an audio signal by digital-to-analog converting a PCM signal obtained by time-sampling an audio signal and converting it into a digital signal, including: (a) a digital-to-analog conversion circuit that converts the PCM signal to an analog conversion; . (B) A range detection circuit that detects whether the head of the PCM signal is within a predetermined range; Main) When the PCM signal is within a predetermined range. A division circuit divides the frequency of a first clock according to the output of the range detection circuit, and the first clock divided by the frequency division circuit corresponds to a period in which the PCM signal is converted from digital to analog. a clock, and the frequency dividing circuit stops frequency division when a predetermined number of the first clocks are counted, and when the PCM signal is not within a predetermined range, it is converted into a detailed value according to the output of the range detection circuit, A PC characterized in that the output signal of the digital audio conversion circuit is controlled by the output of the frequency dividing circuit to suppress unification noise.
M signal regeneration circuit. (2) PCM signal according to claim 1, which controls the output signal of the digital audio conversion circuit by switching and controlling the input signal to the digital audio conversion circuit to a predetermined value based on the output of the branch circuit. 1 play time. (3) The PCM signal reproducing circuit according to claim 1, wherein the output signal of the digital audio converting circuit is controlled by relaying the output signal of the digital audio converting circuit using the output of the frequency dividing circuit. (4) The PCM signal reproducing circuit according to claims 1, 2, and 6, wherein the frequency dividing circuit is comprised of a lift register.