JP2002184106A - Jitter removing device and digital audio reproduction system - Google Patents

Abstract

PROBLEM TO BE SOLVED: To solve the problem that sound quality is lowered due to jitter to be transmitted together with data when digital audio data reproduced by a digital audio reproducing device is transmitted to an analog audio output device including a D/A converter by using a digital audio interface. SOLUTION: A jitter removing device to remove the jitter of the digital audio data is inserted between the digital audio reproducing device and the analog audio output device. The jitter removing device constantly latches a part with stable waveform by detecting a code change point of a digital audio interface signal and delaying it according to its phase.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a signal transmitted between a digital audio reproducing apparatus and an audio output apparatus by a data format of a digital audio interface, a transmission procedure, and the like (hereinafter, referred to as a "digital audio interface signal"). TECHNICAL FIELD The present invention relates to a jitter removing device for removing jitter of a digital audio signal and a digital audio reproduction system including the jitter removing device.

[0002]

2. Description of the Related Art In a digital audio reproducing apparatus for reproducing digital audio data recorded on a recording medium such as a compact disk or a digital audio tape, servo noise generated in a digital data reproducing section for reading audio data from the recording medium. A reproduction noise such as a noise included in a reproduction signal, a digital noise of a signal processing circuit, or the like, is supplied to a digital-to-analog converter (DAC: Di:
gital Analog Converter) and audio amplifiers with output amplifiers. Such mixing of the reproduction noise into the audio output unit causes deterioration of the sound quality of the audio signal.

For this reason, in a business or high-end consumer system, a digital audio output signal from a digital audio reproducing device is transmitted by a digital audio interface signal and input to the audio output device. Conversion is being performed.

As described above, by separating the digital data reproducing unit and the audio output unit, it is possible to prevent noise from flowing from the digital data reproducing unit and the digital circuit to the analog circuit in the circuit board and the housing. it can.

[0005] However, even if the digital audio playback device and the audio output device are separated, noise inside the digital audio playback device is slightly mixed into the digital audio data interface signal and propagated.
Sound quality degradation due to noise cannot be prevented.

For example, there is a possibility that noise due to an analog circuit of the digital audio reproduction device, in addition to the reproduction noise inside the digital audio reproduction device, is superimposed on the digital audio interface signal and transmitted to the audio output device. Each of these noises causes transmission signal jitter (fluctuation in the time axis direction).

When the digital audio interface line is lengthened, a change in the DC component due to the bit pattern of the transmitted digital audio data itself may cause low-frequency noise and jitter.

When an audio output device receives a digital audio interface signal containing noise and jitter as described above, the noise directly affects an analog circuit via a power supply, a ground wiring pattern, and the like. It becomes the jitter of the clock of D / A conversion, and becomes a factor of the D / A conversion error. Therefore, both noise and jitter of the digital audio interface signal cause sound quality deterioration.

As a method of reducing such noise, data is transmitted in a balanced manner (a method of transmitting a + signal and a − signal in two lines using a differential transceiver) to thereby reduce common mode noise (two-line transmission). A method of removing noise superimposed on both sides in the same manner, and a method of magnetically coupling a transmitting side (digital audio reproducing apparatus) and a receiving side (analog audio output apparatus) of digital audio data with a transformer or using an optical fiber. And a method of optically coupling using a photocoupler to electrically insulate and remove ground noise.

As a method for removing jitter, various jitter removing devices connected between a digital audio reproducing device and an audio output device have been proposed.

As an example of the jitter removing device, a high-precision master clock is prepared in the jitter removing device, the clock is supplied to a digital audio reproducing device and an audio output device, and the digital audio data output from the digital audio reproducing device is provided. Is re-latched in the jitter eliminator.

Further, as an example of a further improved jitter eliminator, a primary side (digital audio reproducing apparatus side) and a secondary side (audio output apparatus side) are electrically separated and optically separated by using a photocoupler. Combine, generate a master clock on the secondary side and supply it to the primary side, the primary side transmits digital audio data to the secondary side using the supplied master clock, and the waveform of digital audio data on the secondary side There has been proposed a method of re-latching a stable portion of the data by using a master clock.

[0013]

As described above, in the method using the jitter eliminator incorporating the master clock generator, the clock transmission lines are defined from the beginning in addition to the data transmission lines, including their phase relationships. When a double-wire data transmission system is used, it can be easily realized.

In such a double-wire data transmission system, since the phase relationship between a clock (eg, word clock) and a data transmission signal is defined, when the reception side is a clock master, the transmission side is defined. Since data must be transmitted in accordance with the phase relationship, it is easy to correctly re-latch the transmission data using the master clock on the receiving side.

However, the commonly used IEC (In)
ternational Electrotechnical Commission) 958,
When a one-wire serial data transmission method such as IEC60958 is used, it is not easy to realize the system.

That is, in the one-line serial data transmission, a self-clock transmission method is employed, so that a transmission side such as a digital audio reproducing apparatus basically becomes a clock master. Many digital audio playback devices for business use perform a slave operation in synchronization with an external word clock input.

Normally, in a digital audio reproducing apparatus corresponding to an external clock input, a word clock equal to the sampling frequency is received and an internal PLL (Phase Lock) is received.
An ed Loop) circuit generates a high-frequency system clock, and a digital audio interface signal based on digital audio data is transmitted by the system clock. However, there is no particular definition of the phase relationship between the digital audio interface signal output and the external clock input.

In the above-described jitter removing apparatus, when the phase of the input digital audio interface signal is unknown, it is difficult to accurately latch it. If the data is latched in the vicinity of the sign change point of the digital audio data, the sign may be confused.

According to the present invention, there is provided a digital audio playback apparatus capable of inserting a digital audio interface signal from a digital audio reproducing apparatus capable of performing a slave operation to an audio output apparatus in the middle of a transmission path and transmitting a digital audio signal having an arbitrary phase transmitted from the digital audio reproducing apparatus. A jitter removing device that can stably remove jitter by latching an interface signal at an appropriate timing; and
It is an object of the present invention to provide a digital audio reproducing system including the jitter removing device.

[0020]

According to a first aspect of the present invention, there is provided a jitter removing apparatus for removing jitter of a digital audio interface signal, comprising: a clock generating unit for generating a master clock, a latch clock, and a word clock; An edge detection unit that detects a sign change point of the digital audio interface signal and generates an edge pulse; a phase detection unit that determines a phase of the edge pulse with respect to the latch clock and outputs a phase detection signal; A variable delay unit for delaying the digital audio interface signal based on the latch signal, a latch unit for latching the delayed digital audio interface signal using the latch clock, and a phase for causing the phase detection unit to perform phase detection again. Set range Characterized by comprising a phase check signal generator.

According to a second aspect of the present invention, there is provided a digital audio reproducing apparatus for reproducing digital audio data recorded on a recording medium and outputting a digital audio interface signal in synchronization with an external word clock; An audio output device that converts the digital audio interface signal output from the jitter removal device to an audio signal and outputs the audio signal, wherein the jitter removal device includes a clock generation unit that generates a master clock, a latch clock, and a word clock. An edge detection unit that detects a sign change point of the digital audio interface signal and generates an edge pulse; a phase detection unit that determines a phase of the edge pulse with respect to the latch clock and outputs a phase detection signal; Based on signal A variable delay unit for delaying the digital audio interface signal, a latch unit for latching the delayed digital audio interface signal using the latch clock, and a phase range for causing the phase detection unit to perform phase detection again. And a phase check signal generator for setting [Detailed description of the invention]

[0022]

FIG. 1 is a schematic diagram showing a schematic configuration of an embodiment of a digital audio reproducing system according to the present invention. In FIG. 1, a digital audio playback system 101 includes a digital audio playback device 102, a jitter removal device 103, and an analog audio output device 104. In this embodiment, the audio output device is an analog audio output device 10 that converts digital audio data into an analog audio signal and outputs the signal.
4 will be described.

Between the digital audio reproducing apparatus 102 and the jitter removing apparatus 103, and between the digital audio reproducing apparatus 102 and the jitter removing apparatus 10
Digital audio data transmission between the digital audio interface 3 and the analog audio output device 104 is performed according to a data format, a transmission procedure, and the like by a digital audio interface. In this embodiment, the digital audio interface is IEC958 or IEC60958.
Shall be stipulated in

The digital audio interface signal in IEC958 has a 24-bit audio data slot, 4-bit additional information, and a 4-bit equivalent synchronizing signal (preamble) for each channel. This is a serial data string, which is a 128-bit serial signal per sample subjected to biface mark modulation.

Therefore, the sampling frequency fs of digital audio data to be transmitted (for example, 44.1k
Hz, 48 kHz, 96 kHz, etc.)
The double 128 fs becomes the transmission channel clock frequency.

The digital audio reproducing apparatus 102 is a digital recording medium (for example, an optical recording medium such as a compact disk or a magnetic recording medium such as a digital audio tape).
Play the digital audio data recorded in the. The reproduced digital audio data is supplied to a word clock (WCK:
It is output as a digital audio interface signal synchronized with Word ClocK).

The jitter removing device 103 converts the internally generated word clock WCK to the digital audio reproducing device 1.
02 and the analog audio output device 104,
The jitter of the digital audio interface signal input from the digital audio playback device 102 is removed and the digital audio interface signal is output to the analog audio output device 104.

The analog audio output device 104 includes a D / A converter for converting digital audio data into an analog audio signal, and converts received digital audio data into analog data based on the word clock WCK supplied from the jitter removing device 103. Convert to audio signal and output.

The word clock WCK is generated by the jitter eliminator 103,
And an analog audio output device 104.
That is, the jitter removing device 103 is a clock master, and the digital audio reproducing device 102 and the analog audio output device 104 are slaves.

The digital audio reproducing device 103 is provided with a word clock WC supplied from the jitter removing device 103.
A digital audio interface signal synchronized with K is output. Although the digital audio interface signal and the word clock WCK have the same frequency, the phase relationship between them is unknown because it differs depending on the device.

After adjusting the phase of the digital audio interface signal input from the digital audio reproducing device 103, the jitter removing device 103 re-latch every serial transmission channel bit using the internally generated high precision clock.

As a result, from the jitter removing device 103,
A digital audio interface signal from which jitter due to the digital audio reproducing device 102 has been removed is output. The analog audio output device 104
A digital audio interface signal without jitter from the jitter removing device 103 and an analog audio signal with high fidelity can be reproduced by the word clock WCK with high accuracy.

FIG. 2 is a schematic diagram showing a schematic configuration of the jitter removing device in the present embodiment. 2, the jitter removing apparatus 103 includes a clock generation unit 201, an edge detection unit 202, a phase detection unit 203, a phase check signal generation unit 204, a variable delay unit 205, and a latch unit 206.

Here, the input digital audio interface signal (input signal) is converted to IDT (Input Digital Audio).
dio inTerface signal), and the delayed digital audio interface signal (delayed signal) is DDT (Delayed
Digital audio inTerface signal) and output digital audio interface signal (output signal) as ODT
(Output Digital audio inTerface signal).

The clock generation unit 201 has a frequency of 256 f, which is twice the transmission channel clock frequency of 128 fs, so that a phase detection unit 203, which will be described later, performs quadrant phase detection.
A high-precision crystal oscillator that generates the s master clock MCK is provided.

The clock generation unit 201 has a frequency 2
56 fs master clock (MCK: Master ClocK)
Clock with a frequency of 128 fs (LC
K: Latch ClocK) and a word clock WCK having a sampling frequency fs which is further divided by 128.
The word clock WCK is sent to the digital audio playback device 102 and the analog audio output device 104.

The edge detector 202 detects the sign change point of the input signal IDT (the level of the transmitted digital signal is "H").
From "L" or "L" to "H")
Is detected, and an edge pulse (EGP: EdGe P
ulse).

The phase detecting section 203 has a master clock M
Based on CK and the latch clock LCK, a phase detection signal is generated in which the phase relationship of the sign change point (edge) of the input signal IDT with respect to the latch clock LCK is represented by 2 bits, and the phase detection signal is transmitted to the variable delay unit 205 described later. Output.

The variable delay unit 205 includes the phase detector 20
In response to the phase detection signal of No. 3, the input signal IDT is delayed and a delayed signal DDT is output.

The latch unit 206 includes a variable delay unit 206
The delay signal DDT output from the latch clock LC
It latches bit by bit using K and outputs an output signal ODT.

When the phase of the input signal IDT is greatly shifted due to power-on, connection change, or the like, the variable delay unit 20
In step 5, the amount of delay for delaying the input signal IDT is corrected.

The phase check signal generation section 204 generates an invalid gate signal (INV: INV) for defining a predetermined allowable range for each initial phase detected by the phase detection section 203.
Valid gate signal).

When the phase of the input signal IDT deviates from the initial phase by an allowable range or more, the phase detector 203 newly performs phase detection. The variable delay unit 205 changes the delay amount of the input signal IDT according to the phase newly detected by the phase detection unit 203.

The error display unit 207 includes a phase detection unit 203
A display indicating that a transmission error has occurred due to a phase shift during the reproduction of the audio signal is performed based on the phase detection signal from.

FIG. 3 is a timing chart for explaining an example of a schematic operation of the jitter removing apparatus according to the present embodiment. FIG.
As shown in (a) and FIG. 3 (b), sections distinguished by a combination of two bits of the master clock MCK and the word clock WCK are defined as sections A to D.

It is assumed that the sign change point of the input signal IDT from the digital audio reproducing apparatus 102 exists in the section D (FIG. 3A) as shown in FIG.

At this time, the latch clock LCK (FIG. 3)
Since the sign change point is close to the latch timing (upward arrow in FIG. 3) according to (b)), there is a risk of an error if latching is performed as it is. Therefore, a fixed amount of delay is given to the input signal IDT (FIG. 3C) to shift the sign change point,
Be able to latch in a stable position of the signal.

For this purpose, the edge detecting section 202 generates an edge pulse EGP as shown in FIG. 3D at the sign change point of the input signal IDT.

The phase detector 203 detects the phase relationship of the input signal IDT with respect to the latch clock LCK.
It is detected which of the four sections A to D is located.

In this example, since the edge pulse EGP (sign change point) is in the section D, the phase detection section 203 outputs a phase detection signal (0, 0) indicating the phase relationship to the variable delay section 205.

When the phase detection signal (0, 0) is input, the variable delay unit 205 selects the delay signal DDT delayed by 2t shown in FIG. Since the 2t delay signal DDT has a sign change point in the section B, no latch error occurs when latching with the latch clock LCK.

The latch section 206 latches the delay signal DDT using the latch clock LCK obtained by dividing the master clock MCK by the high-precision crystal oscillator.
The output signal ODT without jitter shown in (f) is output to the analog audio output device 104.

The phase of the input signal IDT (FIG. 3C) is
Significantly shifted from the initial phase detected by the phase detector 203,
For example, in the section B, the delay amount of 2t of the delay signal DDT becomes inappropriate, so that the phase needs to be re-detected.
Therefore, the phase check signal generator 204 constantly outputs the invalid gate signal INV shown in FIG.

The phase detector 203 detects the edge pulse EGP
If the phase shift exceeds the allowable range and enters the invalid area of the invalid gate signal INV, the phase relationship of the edge pulse EGP with respect to the latch clock LCK is newly detected, and the variable delay unit 205 appropriately adjusts accordingly. Reset the delay to a suitable value.

Next, the operation of each unit in the jitter elimination apparatus of this embodiment will be described in detail. FIG. 4 is a schematic diagram for explaining an example of the edge detection unit. The edge detection unit 202 divides the input signal IDT into two systems, delays one by a delay (IDT ′), and exclusion of the input signal IDT and the input signal IDT ′ using, for example, the circuit shown in FIG. By performing a logical OR (XOR) operation, an edge pulse EGP (FIG. 4B) can be obtained.

FIG. 5 is a schematic diagram for explaining an example of the circuit configuration of the phase detector. The phase detection unit 203 is composed of, for example, two D flip-flop circuits as shown in FIG. The latch clock LCK is input to the data input (D) of one D flip-flop circuit, and the master clock MCK is input to the data input of the other D flip-flop circuit.

A phase detection pulse (PDP: Phase Detect Pulse) in which the edge pulse EGP is detected by using the invalid gate signal INV is input to the clock input (CLK) of both the D flip-flop circuits. Occurs, the latch clock LCK and the master clock MCK at the rise of the phase detection pulse PDP
Of the phase detection signal (P) as shown in FIG.
H1, PH2) until the next clock is input.

The above-described edge detector 202 and phase detector 2
With 03, it is possible to determine the phase relationship between the sign change point of the input signal IDT and the latch clock LCK by using the 2-bit phase detection signals (PH1, PH2).

FIG. 6 is a schematic diagram for explaining an example of the variable delay unit. The variable delay unit 205 includes, for example, a data selector 206a as shown in FIG.
And a plurality of delay elements 206b to 206d. The delay amount is set to a half cycle of the master clock MCK per minute of the delay. A delay time corresponding to a half cycle of the master clock MCK is “t”.

The input terminal S1 of the data selector 206a,
The phase detection signal (PH1, PH2) input from the phase detection unit 203 is input to S2.

The input signal IDT is input to a circuit in which three delay elements (206a, 206b, 206c) with a unit delay of 1t are arranged in series. Data selector 206a
, Input signal IDT, 1t delayed signal from delay element 206a, 2t delayed signal from delay element 206b, and 3t delayed signal from delay element 206c are input to input terminals C2, C3, C0, and C1, respectively.

From the output terminal Y, as shown in FIG. 6B, the phase detection signal (P
H1, PH2) is output.

In FIG. 6B, from the output terminal Y,
In the case of the phase detection signal (0, 0), a delay signal DDT of a delay amount 2t input to the input terminal C0 is output, and in the case of the phase detection signal (0, 1), the delay amount 3t input to the input terminal C1. Is output, and the phase detection signal (1, 1) is output.
0), the delay signal DDT with the delay amount 0 input to the input terminal C2 is output, and when the phase detection signal (1, 1), the delay signal Dt with the delay amount 1t input to the input terminal C3.
DT is output.

FIG. 7 is a timing chart for explaining the operation of the phase detecting section and the variable delay section. Input signal I
DT is, as shown in FIGS. 7C to 7F, IDT (A) to IDT (A) to IDT depending on the phase at which the sign change point exists.
(D) can be classified into four types. Here, the square on the waveform indicates the distribution range of the sign change point.

When the master clock MCK shown in FIG. 7A and the latch clock LCK shown in FIG. 7B are latched by the edge pulse EGP in the phase detector 203, (1) 1),
Phase detection signals (PH1, PH2) of four patterns of (1, 0) and (0, 1) (0, 0) are obtained. This makes it possible to detect in which section the sign change point of the input signal IDT is located.

Of these four input signals IDT,
Since the sign change points of the input signals IDT (A) and IDT (D) are adjacent to the rising timing of the latch clock LCK, a latch error may occur due to jitter.

Since the input signal IDT (C) has a latch timing at the first half of the pulse of the latch clock LCK, there is a possibility that the input signal IDT (C) is affected by a transient response at the sign change point.

Therefore, since the latch timing of the input signal IDT (B) whose sign change point is in the range of the section B is the latter half of the pulse of the latch clock LCK, the latch is performed with the phase most stable by the latch clock LCK. is there.

By adding an appropriate amount of delay to each of the input signals of IDT (A) to IDT (D), the sign change points are aligned in a section B where the latch can be stably latched by the latch clock LCK. be able to.

The variable delay section 205 delays the input signal IDT on the basis of the phase detection signal and on the basis of any one of the four patterns described above.

The amount of delay required for each is shown in FIG.
As shown in FIGS. 7C to 7F, the IDT (A) is “1”.
t ", IDT (B) is 0, IDT (C) is" 3t ", I
DT (D) is “2t”.

Therefore, delay signals DDT (A) to DDT (D) from variable delay section 205 are always signals having a sign change point in section B, and are stably latched by latch clock LCK.

FIG. 8 is a schematic diagram for explaining an example of the phase check signal generator. FIG. 8A shows a circuit configuration of an example of the phase check signal generator, and FIG. 8B is a table showing the relationship between the phase section and the reset section. FIG.
FIG. 6 is a timing chart for explaining the operation of the phase check signal generator.

As shown in FIG. 8A, the phase check signal generator 204 determines the phase relationship of the input signal IDT with respect to the latch clock LCK (FIG. 8B) initially detected by the phase detector 203. Thereafter, an invalid gate signal INV for detecting whether or not there is a large deviation is generated.

In this embodiment, the width of the invalid area of the invalid gate signal INV is set to the width of a half cycle of the master clock LCK.

As shown in FIG. 9, the invalid gate signal INV has four patterns corresponding to the output pattern of the phase detector 203. For example, a section C on the opposite side to the case where the edge pulse EGP is section A is provided. , Edge pulse EG
Section D, edge pulse EGP, when P is section B
Is an invalid area where the phase relationship with the latch clock LCK is opposite, such as a section A with respect to the section C and a section B with respect to the section D when the edge pulse EGP is in the section D.

That is, as shown in FIGS. 8 (c) to 8 (f), the invalid gate signals INV having invalid areas for the sections A to D are INV (A) to INV (A), respectively. INV (D) (FIGS. 8C to 8
(F)).

As shown in FIG. 8 (b), based on the phase detection signals (PH1, PH2) from the phase detection section 203 in accordance with the initial phase of the input signal IDT from the four types of invalid gate signals INV. Selected and the phase detector 2
03 is output.

When the edge pulse EGP exists in the L level region of the invalid gate signal INV, the phase detector 203 does not perform phase detection and maintains the state up to that time. Phase detection is performed only when the edge pulse EGP enters the H-level region. Therefore, usually, once the optimum phase is detected, it is fixed in that state.

When the code change point moves by a half cycle or more of the master clock MCK due to the jitter, the jitter component is reduced by increasing the accuracy of the PLL circuit on the digital audio reproducing apparatus 102 side so that the master clock MCK is generated.
It is necessary to keep it within １ ／ cycle of CK.

As described above, the jitter removing device 103
Using the latch clock LCK, a stable portion of the digital audio interface signal IDT is always latched and output to the analog audio output device 104.

Therefore, in the digital audio reproducing system, the jitter of the digital audio data can be removed, and the deterioration of the sound quality of the audio signal can be reduced.

FIG. 10 is a schematic diagram showing a schematic configuration of another embodiment of the jitter eliminator of the present invention. As shown in FIG. 10, among the components of the jitter removing device 103, the edge detecting unit 202, the phase detecting unit 203, the phase check signal generating unit 204, and the variable delay unit 205 are provided on the primary side (the digital audio reproducing device side). Clock generation unit 201
And a latch unit 206 provided on the secondary side (analog audio output device side), and the two are electrically separated from each other.
T, latch clock LCK and master clock MCK
Only optical transmission is possible.

At this time, if the frequency divider 207 for dividing the latch clock LCK to generate the word clock WCK is provided on the primary side, the word clock WCK does not have to be optically transmitted.

In the above embodiments, the numerical values such as the frequency, the phase division, the delay amount, and the pulse width are merely examples, and do not limit the present invention. In the present embodiment,
Although the jitter removal symmetry is a digital audio interface signal of IEC958, it can be applied to other serial data transmission formats.

[0086]

According to the present invention, when a digital audio playback device and an analog audio output device are connected using a one-line digital audio interface, digital audio data is latched at an optimal timing to reduce jitter. Thus, the sound quality of the audio signal can be reduced.

[Brief description of the drawings]

FIG. 1 is a schematic diagram showing a schematic configuration of an embodiment of a digital audio reproduction system according to the present invention.

FIG. 2 is a schematic diagram showing a schematic configuration of an embodiment of a jitter removing device according to the present invention.

FIG. 3 is a timing chart for explaining an operation example of the jitter removing apparatus of the embodiment.

FIG. 4 is a schematic diagram illustrating an example of a circuit configuration of an edge detection unit.

FIG. 5 is a schematic diagram illustrating an example of a circuit configuration of a phase detection unit.

FIG. 6 is a schematic diagram illustrating an example of a circuit configuration of a variable delay unit.

FIG. 7 is a timing chart for explaining operations of a phase detection unit and a variable delay unit.

FIG. 8 is a schematic diagram illustrating an example of a circuit configuration of a phase check signal generation unit.

FIG. 9 is a timing chart for explaining the operation of the phase check signal generation unit.

FIG. 10 is a schematic diagram showing a schematic configuration of another embodiment of the jitter removing device of the present invention.

[Explanation of symbols]

101: Digital audio playback system, 102
... Digital audio playback device, 103 ... Jitter removal device, 104 ... Analog audio output device. 201 clock generator, 202 clock divider, 203 edge detector, 204 phase detector, 205 phase check signal generator, 206
..Variable delay unit 205a: data selector, 2
06b, 206c, 206d... Delay element, 20
7: latch unit, 208: error display unit.

Claims (2)

[Claims] 1. A jitter removing apparatus for removing jitter of a digital audio interface signal, comprising: a clock generator for generating a master clock, a latch clock, and a word clock; and detecting a sign change point of the digital audio interface signal to generate an edge pulse. An edge detector that generates, a phase detector that determines a phase of the edge pulse with respect to the latch clock and outputs a phase detection signal, and a variable delay unit that delays the digital audio interface signal based on the phase detection signal. A latch unit that latches the delayed digital audio interface signal using the latch clock, and a phase check signal generation unit that sets a phase range for causing the phase detection unit to perform phase detection again. Features Jitter removal apparatus. 2. A digital audio reproducing apparatus which reproduces digital audio data recorded on a recording medium and outputs a digital audio interface signal in synchronization with an external word clock, a jitter removing apparatus, and a digital audio data output from the jitter removing apparatus. An audio output device that converts the digital audio interface signal into an audio signal and outputs the audio signal; the jitter removing device includes a clock generation unit that generates a master clock, a latch clock, and a word clock; An edge detection unit that detects a transition point and generates an edge pulse; a phase detection unit that determines a phase of the edge pulse with respect to the latch clock and outputs a phase detection signal; A variable delay section for delaying the interface signal, a latch section for latching the delayed digital audio interface signal using the latch clock, and a phase range for causing the phase detection section to perform phase detection again. A digital audio reproduction system comprising a phase check signal generation unit.