JPH07153006A - Digital signal recorder - Google Patents

Abstract

PURPOSE:To record a data signal which is not affected by jitter and to eliminate a state in which no recording exists. CONSTITUTION:D-flip-flops 4 and 12 latch a digital video signal, and supply it to data channels 5 and 13 of a rotary transformer. A frequency divider 20 divides in frequency a clock signal, and supplies it to a primary side core of a clock channel 21. D-flip-flops 8 and 16 are transmitted with transmission data signal transmitted from the channels 5 and 13 from a secondary side core of a clock channel 21, and latched to be output based on a clock signal returned to an original frequency by a multiplier 25. A level detector 24 detects a level of a frequency-divided clock signal, and switches changeover switches 9 and 17 in response to a detected level.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a digital signal recording circuit for recording a digital video signal or a digital audio signal on a magnetic tape by using a rotary head.

[0002]

2. Description of the Related Art Recently, in a digital signal recording / reproducing apparatus such as a digital video tape recorder or a digital audio tape recorder, a rotary head is used in order to relatively increase the tape speed and enable high density recording. There is. For example, when digital video data is recorded on a magnetic tape by a digital video tape recorder, the data is transmitted to a rotary head using a rotary transformer which is electrically coupled but mechanically separated.

Of the digital signal recording / reproducing apparatus for transmitting data to the rotary head using such a rotary transformer, two examples of conventional digital signal recording circuits are shown in FIG.
9 and the common positions (a, b, c, d,
The waveform of the signal in e) is shown in FIG.

First, a conventional example shown in FIG. 8 will be described. In this conventional example, a data signal is input from an unillustrated digital signal processing system via an input terminal 51. This data signal is supplied to the data terminal D of the D-flip-flop circuit 53. To the clock input terminal CL of the D-flip-flop circuit 53, the clock signal shown in c of FIG. 10 obtained by a digital signal processing system (not shown) is supplied via the input terminal 52. Then, the D-flip-flop circuit 53 outputs a data signal having a waveform as shown in FIG. 10A from the output terminal and supplies the data signal to the primary side core of the rotary transformer 54.

The rotary transformer 54 transmits the data signal supplied from the D-flip-flop circuit 53 to the primary core to the secondary core rotated through a minute gap. The signal transmitted to the secondary side core is supplied to the slicer 56, which is a binarizing unit, via the differential amplifier circuit 55. The data signal binarized by the slicer 56 passes through the differential amplifier circuit 57 and the magnetic head 58.
Is supplied to. Then, the magnetic head 58 records the binarized data signal on a magnetic tape (not shown).

Here, when the rotary transformer 54 transmits the data signal supplied to the primary core to the secondary core, the data signal is distorted. That is, the signal transmitted to the secondary side core has a waveform including jitter as shown in b of FIG.

This is an influence of general characteristics of the rotary transformer 54. For example, the rotary transformer has the property that the transmission delay time varies depending on the frequency of the data signal to be transmitted. When the data signal is an audio signal or a video signal, it contains many frequency components, and therefore the delay time is different. Therefore, as mentioned above,
The signal transmitted to the secondary core of the rotary transformer 54 passes through the differential amplifier circuit 55 and the slicer 56 at the time of FIG.
Jitter is included as shown in b).

When the signal containing the jitter is recorded on the magnetic tape by the magnetic head 58 as described above, the recording magnetization reversal timing is deviated and the detection window width during reproduction is narrowed. Therefore, in the conventional example shown in FIG. 8, good reproduction was hindered and the recording density could not be increased.

Therefore, conventionally, a method of improving the coupling coefficient of the rotary transformer and a method of compensating by an inverse circuit using a coil and a capacitor have been considered, paying attention to the fact that the transmission distortion is linear.

First, changes in general characteristics of the rotary transformer when the coupling coefficient of the rotary transformer is improved will be described with reference to the drawings. In the amplitude characteristic of the rotary transformer and the delay characteristic of the zero-cross point for the rectangular wave shown in FIGS. 11 and 12, the characteristics are obviously improved by increasing the coupling coefficient k. For example, in the amplitude characteristic shown in FIG. 11, in which the horizontal axis represents the frequency of the signal to be transmitted and the vertical axis represents the change in the amplitude with respect to the change in the frequency, the coupling coefficient k is 0.92,
Amplitude characteristics are improved as they are improved to 0.98 and 0.995. Further, for example, in the amplitude characteristic shown in FIG. 12 in which the horizontal axis represents the frequency of the signal to be transmitted and the vertical axis represents the change in the delay time at the zero-cross point with respect to the change in the frequency, the coupling coefficients k are 0.92 and 0.98. , 0.995, the delay time at the zero-cross point becomes shorter.

However, in order to increase the coupling coefficient k, 1
It is necessary to make the air gap between the secondary core and the secondary core as narrow as possible. For example, in order to obtain a value such as k = 0.995, the air gap between the primary core and the secondary core should be extremely small. Since it must be narrowed and the processing accuracy must be increased accordingly, the cost becomes high.

Next, it is difficult for a method such as compensation by an inverse circuit created by a coil and a capacitor, paying attention to linear transmission distortion, to cope with variations in the inductance of the rotary transformer, and the circuit scale. Is also not practical because it grows.

Therefore, instead of these methods, a technique as shown in FIG. 9 has been proposed, for example, in Japanese Patent Laid-Open No. 224008/1988, in order to solve the problems of the conventional example.

In the conventional example shown in FIG. 9, a data signal input from an unillustrated digital signal processing system via an input terminal 60 is supplied to a data terminal D of a D-flip-flop circuit 61. To the clock input terminal CL of the D-flip-flop circuit 61, the clock signal shown in c of FIG. 10 which is obtained when a data signal is produced by a digital signal processing system (not shown) is supplied via the input terminal 66. Then, the D-flip-flop circuit 61 outputs a signal having a waveform as shown in a of FIG. 10 from the output terminal. In this way, the data signal supplied from the digital signal processing system (not shown) via the input terminal 60 is synchronized by the D-flip-flop circuit 61 and shaped into a signal having no jitter as shown in a of FIG. It The signal as shown in a of FIG. 10 is supplied to the primary side core of the data channel 62 of the rotary transformer. This data signal channel (hereinafter referred to as data channel) 62 is 1
The data signal is transmitted to the secondary core that is rotated through the secondary core and a minute air gap (for example, an air gap having a coupling coefficient of 0.98).

The data signal transmitted to the secondary side core of the data channel 62 is supplied to the data terminal D of the D-flip-flop circuit 65 via the differential amplifier circuit 63 and the slicer 64. To the clock input terminal CL of the D-flip-flop circuit 65, a signal is transmitted by a channel (hereinafter referred to as a clock channel) 68 different from the data channel 62, and is transmitted via a differential amplifier circuit 69 and a slicer 70 in FIG. The clock signal shown in d is supplied.

The clock channel 68 receives a clock signal, as shown in FIG. 10C, input from a digital signal processing system (not shown) via the input terminal 66 and the differential amplifier circuit 67 from the core on the primary side. It is transmitted to the next core.

Then, the D-flip-flop circuit 65 outputs a synchronized inverted waveform as shown by e in FIG. 10 from the output terminal. The inverted waveform as shown by e in FIG. 10 is supplied to the magnetic head 72 via the differential amplifier circuit 71.

Here, the inverted waveform as shown by e in FIG. 10 is delayed in time as compared with the signal data input from the input terminal 60, but does not include jitter. Therefore, the conventional example of FIG. 9 does not change the recording magnetization reversal timing as in the conventional example of FIG. 8 described above,
It does not narrow the detection window width during playback.

[0019]

In the conventional example of FIG. 9 described above, the frequency of the clock signal used for latching by the D-flip-flop circuit 65 is the highest frequency of the data signal transmitted by the data channel 62. Of 2
I need twice. For example, the maximum fundamental frequency of the video data signal transmitted by the data channel is, for example, 55 MHz.
, The frequency of the clock signal is 110 MHz.

A clock signal having a frequency of 110 MHz,
When a 55 MHz video data signal is transmitted by a rotary transformer, as is clear from FIG. 11, the amplitude of the clock signal is 4d even when the coupling coefficient is 0.98.
It will be about B. Considering the variation of the coupling coefficient and the like, the amplitude deterioration of about 10 dB or more actually occurs. That is, in the conventional example of FIG. 9, the frequency of the clock signal needs to be twice the frequency of the data signal, so that the amplitude of the clock signal becomes insufficient due to the high frequency cutoff. Also,
Generally, a rotary transformer causes a large phase shift when the frequency of a signal to be transmitted changes greatly. Besides this,
Since the frequency of the clock signal is twice the frequency of the data signal, there may be a difference in the delay time between the data signal and the clock signal. Therefore, in the conventional example shown in FIG. 9, it is possible that the D-flip-flop circuit 65 cannot correctly latch the data signal, that is, cannot correctly synchronize.

If the clock signal cannot be sent to the secondary side of the clock channel for some reason, the data signal transmitted by the data channel cannot be recorded at all.

The present invention has been made in view of the above-mentioned circumstances, and does not cause an amplitude shortage and a phase shift of the clock signal and optimizes the delay time between the data signal and the clock signal. An object of the present invention is to provide a digital signal recording circuit which can record a data signal by a correct latch, that is, a correct synchronization, and can switch an alternative signal to record when a clock signal is not transmitted and eliminate the fear of not recording anything. To do.

[0023]

A digital signal recording circuit according to the present invention includes a rotary transformer having a plurality of signal transmission channels, and one of the channels of the rotary transformer for dividing the frequency of a clock signal. The frequency dividing means for supplying to the secondary side, the multiplying means for multiplying the frequency of the output signal from the secondary side of the one channel of the rotary transformer, and the primary side of the other channel of the rotary transformer. Binarizing means for binarizing a data signal transmitted to the secondary side of another channel, and a binarizing output signal from the binarizing means based on the clock signal multiplied by the multiplying means. The above-mentioned problem is solved by having a latch means for

In this case, the frequency band of the divided clock signal transmitted from the primary side of the one channel of the rotary transformer to the secondary side of the rotary transformer is from the primary side of the other channel of the rotary transformer to the secondary side. It is preferably equal to the frequency band of the data signal transmitted to the side.

Here, the digital signal recording circuit according to the present invention responds to the detection means for detecting the presence or absence of the divided clock signal transmitted by the one channel of the rotary transformer, and the detection output from the detection means. It is also possible to provide switching means for switching and outputting the latch output signal from the latch means and the binarized output signal from the binarization means.

In the digital signal recording circuit according to the present invention, the rotary transformer having a plurality of signal transmission channels and the secondary side of the other channel via the primary side of the other channel of the rotary transformer. Binarizing means for binarizing the transmitted data signal, and the binarizing means for binarizing the data signal based on the clock signal transmitted from the primary side to the secondary side of one channel of the rotary transformer. Latching means for latching the converted output signal, detecting means for detecting the presence or absence of the clock signal transmitted by the one channel of the rotary transformer, and latching output from the latching means in response to the detection output from the detecting means. The above-mentioned problem is solved by providing switching means for switching and outputting a signal and the binarized output signal.

In this case, a plurality of the other channels of the rotary transformer are provided and a clock signal transmitted through the one channel is latched with a plurality of data signals transmitted through the other plurality of channels. Therefore, it is preferable to use the same in common.

[0028]

Since the clock signal for binarizing the data signal is divided in advance and made equal to the frequency of the data signal, it is possible to prevent the amplitude of the signal from being insufficient due to the high frequency cutoff and to avoid the risk of phase shift. . Further, since the divided clock signal is transmitted to the secondary side by a clock channel different from the channel transmitting the data signal among the plurality of channels of the rotary transformer, the delay time with the data signal is delayed. The data signal is correctly synchronized by the optimized clock signal, and the data signal without the influence of jitter can be recorded. In addition, by detecting the level of the clock signal transmitted from the clock channel, it is possible to grasp the state in which the clock signal is not transmitted from the clock rotation transformer, and when it is not possible to record a data signal that is not affected by jitter, substitute it. Since it is possible to record the data signal of, there is no occurrence of the condition that no data signal is recorded.

[0029]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS Some preferred embodiments of a digital signal recording circuit according to the present invention will be described below with reference to the drawings.

First, a first embodiment of the digital signal recording circuit according to the present invention will be described with reference to FIGS. FIG. 1 is a block diagram showing a schematic configuration of the first embodiment. Further, FIG. 2 is a waveform diagram showing the waveforms of the transmission data signal and the transmission clock signal of the first embodiment.
In the first embodiment, the transfer rate is 110 Mbps.
Since the NRZ non-modulated signal is recorded in (bits per second), the maximum fundamental frequency of the data signal is 55 MHz, and the detection window width during reproduction is 9.09 ns.

As shown in FIG. 1, the digital signal recording circuit of the first embodiment has input terminals 1 and 2 to which a digital video signal having a maximum fundamental frequency of 55 MHz is inputted from a digital signal processing system (not shown). The digital video signals from the input terminals 1 and 2 are supplied to the data terminals D of the D-flip-flop circuits 4 and 12, respectively. The D-flip-flop circuits 4 and 1
A clock signal obtained by a digital signal processing system (not shown) is supplied to each of the clock input terminals CL of No. 2 via the input terminal 3. The frequency of this clock signal is 55 MHz, which is the highest fundamental frequency of the above video data signal.
Twice, that is, 110 MHz.

Then, the D-flip-flop circuits 4 and 12 output the data signal from each output terminal. These data signals are sent to the rotary transformer data channel 5.
And 13 primary cores.

The data channels 5 and 13 transmit the data signal supplied to the primary side core, which is the fixed side, to the secondary side core, which is the rotating body side. The transmission data signal transmitted to the rotator side by the data channels 5 and 13 is subjected to binarization processing or waveform shaping processing of the input signal via the differential amplifier circuits 6 and 14, for example, slicers 7 and 15. It is supplied to such binarizing means. The slicers 7 and 15 convert the input transmission data signal into a discrete quantity, that is, a binarized signal, depending on whether the input transmission data signal exceeds or does not exceed a predetermined level. The transmission data signal converted into the binarized signal is a signal containing jitter as shown in a of FIG. 2 due to transmission distortion of the data channels 5 and 13 in advance. And
The transmission data signal containing the jitter in advance is supplied to the data terminals D of the D-flip-flop circuits 8 and 9 which are the latch means.

On the other hand, the clock signal from the input terminal 3 is supplied to the D-flip-flop circuits 4 and 1 as described above.
It is supplied to each of the two clock input terminals CL and is also supplied to the frequency dividing circuit 20.

The frequency dividing circuit 20 doubles the frequency of the clock signal by setting the frequency dividing ratio to 2. That is, the clock signal having a frequency of 110 MHz supplied from the input terminal 3 is generated by the frequency dividing circuit 20 at a frequency of 55 M.
It is a divided clock signal of Hz. By thus dividing the frequency by the frequency dividing circuit 20, the clock signal whose frequency is the same as the highest fundamental frequency of the data signal essentially has the same delay time as the data signal. Therefore, the management of these delay times becomes easy, and the adjustment for reducing the individual time difference becomes unnecessary. Further, since the clock signal has a single frequency, the delay time can be changed by a simple primary-system filter, but by lowering the frequency by the frequency dividing circuit, the variable range is expanded and the delay time difference can be optimized. It will be easier. Further, since the frequency of the clock signal is lowered, the transmission waveform can be improved, and further, the crosstalk to the rotary transformer and various signal lines wired around it can be reduced.

The frequency of this divided clock signal is 55 MHz.
Is the same value as the highest fundamental frequency of the video data signal as described above. The divided clock signal is supplied to the core on the primary side of the clock channel 21 different from the data channels 5 and 13.

The clock channel 21 transmits the divided clock signal supplied to the primary core wound on the fixed side to the secondary core wound on the rotor side. Here, since the divided clock has a single frequency, delay does not cause jitter. The frequency-divided clock signal transmitted to the rotator side by the clock channel 21 is binarizing means for binarizing the input signal via the differential amplifier circuit 22, for example, a slicer 23 and a level detecting circuit. 24.

The slicer 23 binarizes the divided clock signal and converts it into a high (H) level logic signal and a low (L) level logic signal having a cycle as shown in FIG. This Figure 2
The H-level and L-level logic signals as shown in b of FIG.

The multiplication circuit 25 is generally composed of a circuit as shown in FIG. That is, the multiplication circuit is generally composed of an integrating circuit including a resistor R and a capacitor C, and an exclusive OR gate 42. A general multiplication operation of this multiplication circuit will be described with reference to the waveform diagram of FIG.

The clock pulse signal S1 supplied to the multiplication circuit via the input terminal 41 is supplied to the integration circuit. This integrating circuit is composed of the resistor R and the capacitor C as described above, and generates the sawtooth wave signal S2. The clock pulse signal S1 and the sawtooth wave signal S2 are supplied to the exclusive OR gate 42. The exclusive OR gate 42 distinguishes "0" and "1" based on the threshold value Th. Therefore, the exclusive OR gate 42 outputs the output pulse signal S3 having twice the frequency of the clock pulse signal S1. The output pulse signal S3 of the multiplication circuit 25 has a duty ratio a / b and is output from the output terminal 43.

In the digital signal recording circuit of the first embodiment using the multiplication circuit which performs such a general operation,
The signal shown in b of FIG. 2 which is the output signal of the slicer 23 is a signal having a clock waveform as shown in c of FIG. The clock signal having the clock waveform as shown in FIG. 2C has the same frequency as the clock before being input to the frequency dividing circuit 20. Therefore, by the multiplication circuit 25, the clock signal at the correct timing when the data signal is originally latched can be easily reproduced over a wide band. Further, since the multiplication circuit 25 has a simple structure, it helps to reduce the circuit scale of the digital signal recording circuit of the first embodiment.

2c output from the multiplier 25
The clock signal as shown in FIG. 2 is supplied to the clock input terminals C of the D-flip-flop circuits 8 and 16 which are the latch means.
It is supplied to L as a synchronization clock.

The D-flip-flop circuits 8 and 16 are
As described above, it is the latch means, and the transmission data signal having the waveform as shown in FIG. 2A supplied from the slicers 7 and 15 to each data terminal D is supplied to each clock input terminal CL from the multiplication circuit 25. By latching with the clock signal as shown in FIG. 2C, the data signal from which the jitter is removed is output from each output terminal Q. The output terminals Q are connected to the selected terminals 9b and 17b of the changeover switches 9 and 17, respectively.

On the other hand, the level detection circuit 24 detects the level of the divided clock signal supplied from the differential amplifier circuit 22 and changes the switch 9 according to the presence or absence of the detected level.
And 17 switching control. This level detection circuit 2
4 is composed of, for example, a full-wave rectifier circuit.
The change-over switches 9 and 17 include the above-described selected terminals 9b and 17b and the selected terminals 9a and 9a to which a transmission data signal as shown in FIG. 17a and movable pieces 9c and 17c which are switched and connected to these selected terminals.

For example, when the level detection circuit 24 detects the divided clock signal level, the level detection circuit 24 switches the movable pieces 9c and 17c of the changeover switches 9 and 17 to the selected terminals 9b and 17b to perform differential amplification. Circuit 1
0 and 18 are supplied with jitter-free data signals synchronized by the D-flip-flop circuits 8 and 16. Then, the magnetic heads 11 and 19 record a data signal which is not affected by the jitter on a magnetic tape (not shown).

Further, for example, when the level detection circuit 24 does not detect the divided clock signal level, the level detection circuit 24 switches the movable pieces 9c and 17c of the changeover switches 9 and 17 to the selected terminals 9a and 17a, respectively. A transmission data signal that does not pass through the D-flip-flop circuits 8 and 16 is supplied to the dynamic amplifier circuits 10 and 18. Then, the magnetic heads 11 and 19 record a data signal as shown in FIG. 2A on a magnetic tape (not shown).

In this way, the level detection circuit 24 detects the presence / absence of the level of the divided clock signal, controls the switching of the changeover switches 9 and 17 according to the detection result, and the magnetic heads 11 and 19 appropriately. The reason why the data signal to be recorded is selectively switched is that the data signal can be recorded even when the divided clock is not supplied from the clock channel 21 due to, for example, a disconnection short circuit. . There are a plurality of data channels 5 and 13 corresponding to the number of the magnetic heads 11 and 19, and even if one of them stops transmitting a data signal for some reason, it cannot completely record a data signal. Absent. On the other hand, since only one clock channel 21 is provided and the transmitted clock is commonly supplied to the other channels, the clock channel 21 transmits the clock signal for some reason. When it disappears, no data signal is recorded. Therefore, when the level detection circuit 24 detects that the clock signal is not transmitted, D-
The transmission data signal, which does not pass through the flip-flop circuits 8 and 16, is recorded by the magnetic heads 11 and 19 so as to prevent a situation in which no data signal is recorded.

As described above, in the digital signal recording circuit of the first embodiment, the frequency of the clock signal is previously divided by the frequency dividing circuit 20 so as to equalize the frequency of the data signal. You do not have to consider the risk. Further, since the divided clock signal is transmitted to the rotating body on the secondary side by the rotation channel 21 for clock different from the data channels 5 and 13 for transmitting the data signal, it is delayed from the signal data. The signal data is synchronized by the time-optimized clock signal, and the data signal without the influence of jitter can be recorded by the magnetic heads 11 and 19. Further, by detecting the level of the clock signal transmitted from the clock channel 21 by the level detection circuit 24, it is possible to grasp the state in which the clock signal is not transmitted from the clock channel 21 and to obtain the data signal not affected by the jitter. When it is not possible to record, the alternative data signal can be recorded from the magnetic heads 11 and 19, so that the state in which there is no data signal recording does not occur. Further, since the level detection circuit 24 detects a clock signal having a frequency that is, for example, halved by the frequency division circuit, the level detection circuit 2 is detected.
Since the operating frequency of 4 can be lowered, the circuit can be easily realized and the power consumption can be suppressed.

Further, since the digital signal recording circuit of the first embodiment essentially aligns the delay times of the data signal and the clock signal, it becomes easy to manage these delay times and to reduce the individual time difference. No adjustment required. Further, since the clock signal has a single frequency, the delay time can be changed by a simple primary-system filter, but by lowering the frequency by the frequency dividing circuit, the variable range is expanded and the delay time difference can be optimized. It will be easier. Further, since the frequency of the clock signal is lowered, the transmission waveform can be improved, and crosstalk to the rotary transformer and various signal lines wired around it can be reduced.

Further, the clock of the low-speed logic circuit for various processes required on the rotary drum is generated by dividing the frequency of the clock signal. In the digital signal recording circuit of the first embodiment, the clock is previously divided by the frequency dividing circuit. Since the frequency is divided to some extent, it is possible to omit a circuit for newly dividing the frequency on the rotary drum.

Further, in the digital signal recording circuit of the first embodiment, when the D-flip-flop circuits 8 and 16 which are the latch means latch the data signals transmitted by the data channels 5 and 13 of the rotary transformer, , The clock signal transmitted to the clock channel 21 of the rotary transformer is used as a shared clock signal.

Of course, the digital signal recording circuit of the first embodiment may be applied to the digital signal recording / reproducing circuit as shown in FIG. The digital signal recording / reproducing circuit shown in FIG. 5 is a circuit for recording and reproducing a digital signal.

That is, in the digital signal recording / reproducing circuit shown in FIG. 5, when recording the digital signal from the digital signal processing system 81, the clock signal transmitted by the clock channel 82a of the rotary transformer 82 is transferred to the rotary transformer 82. Data channels 82b, 82c, 8
It is also used as a latch for the data signal transmitted by 2d and 82e. The latches that share this clock signal are areas (binarization means + latch means + level detection means + switching means) 86a and 86b for performing the same signal processing as the area 30 surrounded by a broken line in FIG. , 86c and 8
It is done in 6d. The recording heads R1A and R2A corresponding to the data channels 82b and 82c are connected to the area 86a. Also, the area 86b
To the recording heads R3A and R4A corresponding to the data channels 82d and 82e. on the other hand,
The area 86c has data channels 82b and 82c.
And a recording head R1 provided to face the recording heads R1A and R2A on the rotating drum by 180 degrees.
B and R2B are connected. Further, in the area 86d, recording heads R3B and R4B corresponding to the data channels 82d and 82e are provided to face the recording heads R3A and R4A by 180 degrees on the rotating drum.
Are connected. For example, in the recording heads R1A and R1B, the timing of the data signal is controlled by the timing control circuit 84.

The digital signal recording / reproducing circuit shown in FIG. 5 is composed of reproducing heads PB1A and PB1B, PB2A and PB2B, PB3A and PB3B which are opposed to each other by 180 degrees on a rotating drum from a magnetic tape (not shown). , PB4A and PB4B are used to read the data signal. The read data signal is supplied to the signal processing unit 88. The signal processing unit 88 performs predetermined signal processing on the read data signal based on the clock signal supplied from the timing control circuit 84, and reproduces this data signal from the reproduction data channel 87 of the rotary transformer 87.
a, 87b, 87c and 87d. Then, each reproduction data channel 87a, 87b, 87c and 8
7d transmits the reproduction data signal to the digital signal processing system 81.

Next, a second embodiment of the digital signal recording circuit according to the present invention will be described with reference to FIG. The digital signal recording circuit of the second embodiment differs from the digital signal recording circuit of the first embodiment described above in that the jitter output from each output terminal of the D-flip-flop circuits 8 and 16 as the latch means. That is, only the data signal that is not affected by is supplied to the magnetic heads 11 and 19. That is, in the second embodiment, the data signal which is not influenced by the jitter can be always recorded on the magnetic tape from the magnetic heads 11 and 19.

Next, a third embodiment of the digital signal recording circuit according to the present invention will be described with reference to FIG. The digital signal recording circuit according to the third embodiment is different from the digital signal recording circuit according to the first embodiment described above in that the clock channel 21 is divided without dividing the clock signal supplied from the input terminal 3. This is the point of transmission to the secondary side, which is the rotating body side. Therefore, this third
In the embodiment, the frequency dividing circuit and the frequency multiplying circuit are unnecessary.
The rest of the configuration is the same as that of the first embodiment described above, so the description is omitted here.

Therefore, in the digital signal recording circuit of the third embodiment, the clock signal of a single frequency is transmitted by the clock channel 21 different from the data transmission channels 5 and 13, and the D-flip-flop circuits 8 and 1 are transmitted.
Since it is used for synchronization in 6, there is little influence of jitter,
The transmitted signal can be recorded. Further, by detecting the level of the clock signal transmitted from the clock channel 21 by the level detection circuit 24, the state in which the clock signal is not transmitted from the clock channel 21 is grasped, and the data signal which is not influenced by the jitter is obtained. When it is not possible to record, the alternative data signal can be recorded from the magnetic heads 11 and 19, so that the state in which there is no data signal recording does not occur.

The digital signal recording circuit according to the present invention is not limited to the digital signal recording circuit of each of the above-mentioned embodiments.

For example, in the multiplication circuit of the digital signal recording circuit according to the first and second embodiments, the multiplication is set to 2
However, the present invention is not limited to this, and may be any integral multiple so as to correspond to the frequency dividing circuit. Further, the multiplication circuit is not limited to being configured only by the combination of the integration circuit and the exclusive OR circuit, and a PLL or a harmonic selection amplification circuit may be used.

In the digital signal recording circuits according to the first and second embodiments, the clock signal which has been multiplied and returned to the correct frequency is input to the D-flip-flop circuit to synchronize the transmission data signal. By using the double-edge type flip-flop circuit, the transmission data signal can be synchronized without using the multiplication circuit.

Further, when the level detecting means detects the non-transmission of the clock signal, it is not the jitter-free transmission data signal synchronized by the D-flip-flop circuit, but D.
The switching means that is switched so as to output the transmission data signal in which jitter does not pass through the flip-flop circuit is not limited to the above-mentioned switching switch. That is, a master-slave flip-flop circuit is used as the D-flip-flop circuit,
By synchronizing the clock signals supplied to the master part and slave part and setting the transmission data signal to the hollow state, the synchronization is prohibited and the transmission data signal including the jitter transmitted by the data rotary transformer is output. Means may be used.

The level detecting circuit is not limited to the one having a full-wave rectifying circuit, but may be a half-wave rectifying circuit, a gate with hysteresis, or a peak detecting circuit. .

Further, in each of the above-mentioned embodiments, the slicer is used as the binarizing means for binarizing the data signal transmitted by the rotary transformer, but the comparator is used as the binarizing means for the data signal. May be binarized.

Further, in the digital signal recording circuit of each of the above-mentioned embodiments, the regions 30, 31, and 32 surrounded by the broken line may be constituted by an integrated circuit. For example, the differential amplifier circuits 6, 14 and 2 described with reference to FIG.
2, slicers 7, 15 and 23, D-flip-flop circuits 8 and 16, changeover switch circuits 9 and 17, differential amplifier circuits 10 and 18, a level detection circuit 24, and a multiplication circuit 25 (above, enclosed by a broken line in FIG. 1 Area 30)
May be configured as a single integrated circuit having a built-in recording circuit for two channels. Since the multiplication circuit and the level detection circuit can be shared by both channels, it is possible to reduce the circuit scale and save power. In addition, since the multiplication circuit is built in, it is not necessary for the pattern on the substrate to pass a high-frequency clock, which is advantageous for the waveform characteristics of the timing signal and can reduce interference with other circuits.

[0065]

According to the digital signal recording circuit of the present invention, a rotary transformer having a plurality of signal transmission channels and the frequency of a clock signal are frequency-divided and supplied to the primary side of one channel of the rotary transformer. Frequency dividing means, multiplying means for multiplying the frequency of the output signal from the secondary side of the one channel of the rotary transformer, and the other side of the other channel via the primary side of the other channel of the rotary transformer. Binarizing means for binarizing the data signal transmitted to the secondary side, and latching means for latching the binarized output signal from the binarizing means based on the clock signal multiplied by the multiplying means. Therefore, it is possible to prevent shortage of signal amplitude due to high frequency cutoff, and to avoid the risk of phase shift. Also,
The frequency-divided clock signal is transmitted to the rotating body on the secondary side by a rotary transformer for clock different from the rotary transformer transmitting the data signal. Therefore, the delay time between the clock signal and the data signal is optimized. The data signal is correctly synchronized by the signal, and the data signal without the influence of jitter can be recorded. In addition, by detecting the level of the clock signal transmitted from the clock channel, it is possible to grasp the state in which the clock signal is not transmitted from the clock rotation transformer, and when it is not possible to record a data signal that is not affected by jitter, substitute it. Since it is possible to record the data signal of, there is no occurrence of the condition that no data signal is recorded.

[Brief description of drawings]

FIG. 1 is a block diagram showing a schematic configuration of a first embodiment of a digital signal recording circuit according to the present invention.

FIG. 2 is a waveform diagram showing a signal waveform of each part of the first embodiment.

FIG. 3 is a specific circuit diagram of a multiplication circuit used in the digital signal recording circuit of the first embodiment.

FIG. 4 is a waveform diagram for explaining the operation of the multiplication circuit shown in FIG.

FIG. 5 is a block diagram showing a schematic configuration of a digital signal recording / reproducing circuit as a modified example of the first embodiment.

FIG. 6 is a block diagram showing a schematic configuration of a digital signal recording circuit of a second embodiment according to the present invention.

FIG. 7 is a block diagram showing a schematic configuration of a digital signal recording circuit according to a third embodiment of the present invention.

FIG. 8 is a block diagram showing a schematic configuration of a conventional example of a digital signal recording circuit.

FIG. 9 is a block diagram showing a schematic configuration of another conventional example of a digital signal recording circuit.

FIG. 10 is a waveform diagram showing a signal waveform at each position of a conventional digital signal recording circuit.

FIG. 11 is an amplitude characteristic diagram of a rotary transformer.

FIG. 12 is a delay characteristic diagram of a zero cross point when a rectangular wave is input to a rotary transformer.

[Explanation of symbols]

 4, 8, 12, 16 ... D-flip-flop circuit 5, 13 ... Data channel 6, 10, 14, 18, 22 ... Differential amplifier circuit 7, 15, 23 ... Slicer 11 , 19 ... Magnetic head 20 ... Dividing circuit 21 ... Clock rotation transformer 24 ... Level detection circuit 25 ... Multiplier circuit

Claims (5)

[Claims] 1. A rotary transformer having a plurality of signal transmission channels, frequency dividing means for dividing the frequency of a clock signal and supplying the divided frequency to a primary side of one channel of the rotary transformer, and the rotary transformer. The multiplication means for multiplying the frequency of the output signal from the secondary side of the one channel, and the data signal transmitted to the secondary side of the other channel via the primary side of the other channel of the rotary transformer. Digital signal recording, comprising: binarizing means for binarizing; and latching means for latching the binarized output signal from the binarizing means based on the clock signal multiplied by the multiplying means. circuit. 2. The frequency band of the divided clock signal transmitted from the primary side to the secondary side of the one channel of the rotary transformer is from the primary side to the secondary side of the other channel of the rotary transformer. 2. The digital signal recording circuit according to claim 1, wherein the frequency is equal to the frequency band of the data signal transmitted to the digital signal recording circuit. 3. A detecting means for detecting the presence / absence of a divided clock signal transmitted by the one channel of the rotary transformer, and a latch output signal from the latch means and the latch output signal according to the detection output from the detecting means. 3. The digital signal recording circuit according to claim 1, further comprising switching means for switching and outputting the binarized output signal from the binarizing means. 4. A rotary transformer having a plurality of signal transmission channels, and a data signal transmitted to the secondary side of the other channel via the primary side of the other channel of the rotary transformer is binarized. And a latching means for latching a binarized output signal from the binarizing means based on a clock signal transmitted from the primary side to the secondary side of one channel of the rotary transformer. Detecting means for detecting the presence or absence of a clock signal transmitted by the one channel of the rotary transformer; and a latch output signal from the latch means and the binarized output signal according to the detection output from the detecting means. A digital signal recording circuit, characterized in that switching means for switching and outputting each is provided. 5. A plurality of the other channels of the rotary transformer are provided, and a clock signal transmitted through the one channel latches a plurality of data signals transmitted through the other plurality of channels, respectively. 5. The digital signal recording circuit according to claim 1, wherein the digital signal recording circuit is commonly used for the purpose.