JPH0771007B2 - Digital data demodulation method - Google Patents

Description

Description: BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention is applied when an information signal such as an audio signal or a video signal is converted into a digital signal and recorded on an optical disc or a magnetic tape. Digital data demodulation method. [0002] When recording a digital information signal,
In order to increase the recording density on the recording medium and reduce the direct current component of the transmission signal, digital modulation called channel coding is performed. Miller modulation is known as conventional channel coding. However, in the mirror modulation, the DC component of the modulation output cannot be zero. For example, when an audio PCM signal is recorded by a rotary head, the recording signal is transmitted via a rotary transformer. If the recording signal contains a direct current component, the rotary transformer cannot transmit the direct current component, which causes a problem that the waveform of the recording signal is distorted. When the recording signal has many low-frequency components, it is necessary to extend the frequency characteristic of the rotary transformer to the low range. Further, when a recording method for suppressing crosstalk between adjacent tracks by making the extension direction of the gap of the recording head different between adjacent tracks, crosstalk suppression for the low frequency component of the recording signal is used. The effect is insufficient. When reproducing an optical disk having a reflective layer on its surface, direct current noise is generated due to dust adhering to the reflective layer, scratches on the reflective layer, and the like. If the digital signal recorded on the disk does not contain a DC component, DC noise can be removed by the filter. From the above-mentioned point, it is required to make the DC component of the recording signal zero. Therefore, a deforming mirror (denoted as M ² )
Modulation has been proposed. Furthermore, a modulation method (referred to as M ³ modulation) in which the effect of suppressing the DC component is improved over that of M ² modulation has been proposed. In these M ² modulation method and M ³ modulation method, the minimum inversion interval of the modulation output is T (where T is the length of one bit cell) and the maximum inversion interval is. 3T
Is. It is desirable that the maximum inversion interval, that is, the maximum value of the interval at which the transition of the data value occurs, is short in order to reduce the low frequency component and improve the clock recovery capability of the recovery circuit. The present invention relates to a method of demodulating digital data which is based on digital modulation in which the direct current component is set to zero and the maximum inversion interval can be shortened as compared with M ² modulation and M ³ modulation. It is also for the purpose of provision. According to the present invention, a data bit sequence consisting of bits having a first value or a second value is (a) continuous when bits of a second value are continuous. Second
(B) inversion at the center of the bit cell of the first value bit, (c) even number of bits of the first value sandwiched between the bits of the second value Of the two first value bits, the inversion at the center of the bit cell of the last two is suppressed, and the inversion is performed at the boundary of the two first value bit cells. (D) After the second value bit When a 2-bit pattern of (second value bit, first value bit) comes at the position next to the following even number of first value bits, the second of these 2 bits Inversion at the center of the bit cell of the value bit, and to obtain the data bit sequence by demodulating the modulated signal generated by inversion as the state transition so as to satisfy the condition of (e) at the boundary of the bit cell Edge inversion detection means for detecting signal inversion, ( ) And the center inversion detection means for detecting the signal inversion in the center of the bit cell, (g) output of the edge inversion detection means, a delay means for delaying the output and demodulation the output of the center inversion detection means, (h) Based on the outputs of the edge inversion detection means, the center inversion detection means, and the delay means, when the data bit has the first value corresponding to (c), but the signal is inverted at the boundary of the bit cell, and (d) ), The digital data demodulating method further comprises means for determining when the signal is inverted at the center of the bit cell having the second value. In the embodiment of the present invention, the first value is a logical 1 and the second value is a logical 0. Of course, it is possible to change this correspondence. For reference of explanation of this one embodiment
Therefore, an example of a digital modulation method will be described. In this example, inversion as a state transition is caused according to the following rules (a) to (d). (A) Inversion at the boundary of a bit cell sandwiched by bit 0. (B) Bit 1 is the inversion in the center of the bit cell. (C) Of an even number of bits 1 sandwiched between bits 0,
The last two bits 1 suppress the inversion at the center,
Inversion occurs at the boundaries of the bit cells of bit 1 of each. (D) An even number of bits 1 following bit 0 is followed by (0
110), an inversion occurs in the center of the bit cell of the first bit 0 of the 4 bits. The above rules (a) and (b) are known for M ² modulation. According to the rules (a) and (b) only, in the case of n data bit strings (where n ≧ 1 and n is an even number) sandwiched by bit 0, such as (011 ... 110). , DC component is generated. When n is an odd number, the polarity of 0 located at the front and the polarity of 0 located at the rear are opposite to each other, and no DC component is generated. Whether or not a DC component is generated is determined by whether DSV (an integrated value when 1 is +1 and 0 is -1) converges to 0 or diverges. Therefore, according to the rule (c), bit 0
Even in the case of an even number of 1s sandwiched between, the DC component is prevented from being generated. In the rules of (a) (b) (c),
3T occurs as the maximum inversion interval. In order to suppress this, the rule (d) is required. FIG. 1A shows a data bit sequence DIN in which one bit is arranged in each of a large number of consecutive bit cells (length T of each bit cell). Modulation rules (a) to (d)
Is applied as shown in FIG. 1C to form the modulated output data DOUT shown in FIG. 1B. As shown in FIG. 1A, (0
If there is a pattern of (0110) after four 1's following 1111) and 0, rule (c) first suppresses the last two bits 1 from being inverted at the center. An inversion is made to occur at the boundary of two bit 1 bit cells. Then, according to the rule (d), (0110)
The inversion occurs in the center of the bit cell of the first bit 0 of the 4 bits. Therefore, the reversal interval of this part is
It becomes 1.5T. FIG. 1D shows the modulated output when modulated according to the rules (a) (b) (c). The modulated output of FIG. 1B and the bit cell to which the rule (d) is applied have the same waveform, and the illustration of this portion is omitted. As is clear from FIG. 1D, without rule (d), 3T
The maximum inversion interval of In the above example of the modulation method, the maximum inversion interval can be as short as 2.5T. There are four types of inversion intervals that can occur: T, 1.5T, 2T, 2.5T. By utilizing this, as the synchronization pattern added to the modulation output, for example, the inversion interval having a length of 3T can be used. The portion of the DSV is likewise zero and Figure 2D of starting with 2 bits at the end of even a few 1 (110110), DSV does not diverge, the DC component can be zero. Next, before the demodulation method to which the present invention can be applied
An example of a proposed modulation method will be described. This modulation method
The method causes inversion according to the following rules (a) to (d). (A) Inversion at the boundary of a bit cell sandwiched by bit 0. (B) Bit 1 is the inversion in the center of the bit cell. (C) Of an even number of bits 1 sandwiched between bits 0,
The last two bits 1 suppress the inversion at the center,
Inversion occurs at the boundaries of the bit cells of bit 1 of each. (D) After an even number of bits 1 following bit 0,
When the pattern of (01) arrives, inversion occurs at the center of the 2-bit (01) 0 bit cell. The rules of the above (a) (b) (c ) has previously
This is the same as the example of the modulation method described . The rule (d) is an extension of the rule (d) in the previous example, and has a wider application range. For a data bit sequence DIN in which one bit is arranged in each of a large number of continuous bit cells as shown in FIG. 2A, as shown in FIG. 2C, the above (a )
Any one of the modulation rules (b), (c), and (d) is applied,
The modulated output data D0UT shown in FIG. 2B is obtained. Figure 2
D shows the modulation output data when the rule of (d) is not used. However, in FIG. 2D, the portion of the same waveform as in FIG. 2B until the modulation rule of (d) is applied is not shown. In the part of the data bit sequence of (011011010) in FIG. 2A, first, two 1's are sandwiched by 0's. Therefore, according to the rule of FIG. Invert at the boundary. And (0
Since the 1) bit pattern follows, the rule of (d) is applied, causing an inversion in the center of this 2-bit 0 bit cell. Furthermore, this (01) is included (011
The rule of (c) is applied to the bit pattern of 0) to cause inversion at the boundary of two 1's of each other bit cell. The latter two bits (10) cause an inversion in the center of the bit cell of the one bit. As a result, the reversal interval becomes 1.5T, 1.5T, 1.5T, T. The waveform shown in FIG. 2D when there is no rule (d) has the inversion intervals of this section of 3T and 2.5T. That is, the inversion interval of 3T is divided into two inversion intervals of 1.5T, and the inversion interval of 2.5T is 1.5T and T.
It is divided into inversion intervals. DS focusing only on this section
V is (+0.5) regardless of whether rule (d) is applied, as is apparent from FIGS. 2B and 2D.
Becomes In this example of the modulation method , the DC component can be zero, and the maximum inversion interval can be shortened to 2.5T. Furthermore, as can be seen from FIG. 2B, this modulation
The example method does not result in consecutive 2.5T inversion intervals.
Without rule (d), as shown in FIG. 2D, 2.5T
May occur continuously. By utilizing this, this strange
As an example of the adjustment method , a bit pattern in which inversion intervals of 2.5T are continuous can be used as the synchronization pattern. FIG. 3 shows an example of a modulation circuit which is a premise of the demodulation method of the present invention. An NRZ data bit sequence DIN is supplied from the input terminal 1 and serial-to-parallel conversion is performed by the shift register 2. Shift register 2
Is a 3-bit one, and three consecutive data bits A (0), A (1), A (2) are extracted and supplied to the modulation logic 3. The data bit A (0) is the present bit, and A (1) and A (2) are future bits. Bit A (1) is the JK flip-flop 4
J input. As the K input of the flip-flop 4, data of 1 is always given. When the J input of the flip-flop 4 becomes 1 and the bit clock BC is applied, the output of the flip-flop 4 is inverted and the J input becomes 0.
Then, the output becomes 0. The output of the flip-flop 4 is synchronized with A (0). The output OD (0) of the flip-flop 4 performs a toggle operation during a period in which continuous 1 bits sandwiched by 0s are input. Therefore, when the number of 1s sandwiched by 0s is an odd number, OD (0)
Becomes 1, and when this is an even number, OD (0) becomes 0. The output of the flip-flop 4 is supplied to the modulation logic 3. The modulation logic 3 has a center inversion signal Ct (0) and an edge inversion signal Eg expressed by the following logical expressions.
It is a combinational circuit or ROM that generates (0). However,
In the following description, ↓ is a symbol that means negation. Ct (0) = A (0) ・ A (1) ・ A (2) + A (0) ・ ↓ OD (0) ・ A (1) ・ ↓ A (2) + OD (0) ・ ↓ A (1) Eg (0) = ↓ A (0) ・ ↓ A (1) + OD (0) ・ A (1) ・ ↓ A (2) When Ct (0) is 1, the center of the bit cell of A (0) Inversion occurs at. A (0) ・ A (1) ・ A (2)
The term of is when the following 2 bits are both 1, that is, A
It becomes 1 when (0) is 1 and is not included in the last 2 bits of continuous 1. Next A (0) ・ ↓ OD (0) ・ A
(1) · ↓ A (2) is the last 2 bits (A (0) A of the sequence of bit 1 in which A (0) is sandwiched by 0s).
(1)) and A (0) is an even bit 1
It becomes 1 when. OD (0) ・ ↓ A (1) is
When A (0) is an odd 1 and the next bit is 0, it becomes 1. The fact that Ct (0) becomes 1 means that the modulation rule (b) causes inversion at the center of the bit cell. When Eg (0) is 1, inversion occurs at the boundary of the bit cell of A (0). The items of ↓ A (0) and ↓ A (1) become 1 when two bits 0 continue. This corresponds to the modulation rule (a). OD (0) ・ A (1) ・
↓ The term of A (2) is 2 bits (1
It is 1 when it is the first 1 of 1) and A (0) is an odd 1 (that is, A (1) is an even number). This term corresponds to the modulation rule (c). Further, the modulation logic 3 outputs a discrimination signal EV1 (0) represented by the following logical expression in order to cause inversion according to the modulation rule of (d). EV1 (0) = OD (0) · A (1) · ↓ A (2) This signal EV1 (0) is one of the terms included in the logical expression of the edge inversion signal Eg (0). This discrimination signal EV
1 (0) becomes 1 when the modulation rule of (c) is applied as described above. The discrimination signal EV1 (0) is supplied to the 3-bit shift register 5 and the input terminal 7A of the switch circuit 6. The switch circuit 6 also has input terminals 7B and 7C. Bit A from shift register 2 to input terminal 7B
(0) is supplied, and an input of 0 is always supplied to the input terminal 7C. Output of switch circuit 6 and shift register 5
Thus, the discrimination signal EV1 (-3) delayed by 3 bits is supplied to the AND gate 8. The output of the AND gate 8 is supplied to one input terminal of the OR gate 9. OR
The flip-flop 10 is connected to the other input terminal of the gate 9.
Center inverted signal Ct (-
1) is supplied. The output Ct '(-
1) and the edge inversion signal Eg (-1) delayed by 1 bit by the flip-flop 11 are supplied to the parallel input of the shift register 12. In the switch circuit 6, the input terminal 7A is selected when performing the modulation of the above-described example , and the demodulation method of the present invention is selected.
The input terminal 7B is selected when performing the modulation of the example that is the premise of the law, and the input terminal 7C is selected when performing the modulation according to the modulation rules of (a), (b), and (c) excluding (d). AND
The output of the gate 8 and the above-described example or the premise of the demodulation method
The center inversion signal according to the modulation rule (d) of the example is extracted. Since an input of 0 is always applied to the input terminal 7C, the output of the AND gate 8 is always 0,
Modulation rule (d) is not used. The shift register 12 performs parallel-to-serial conversion, and its serial output TG is input to the toggle flip-flop 13. The output of the flip-flop 13 is taken out to the output terminal 14 as the modulation output DOUT. A clock 2BC having a cycle of 0.5T is supplied to the terminal 15, and this clock 2BC is used as a clock input to the shift register 12 and the flip-flop 13. Further, the clock 2BC is divided into (1/2) frequency divider circuit 16
A bit clock BC having a period T formed by dividing by is used as a shift / load control signal for the shift register 12 and also as clock inputs for the other shift registers 2, 5 and flip-flops 4, 10, 11. To be done. The shift register 12 performs the shift operation by the clock 2BC when the clock BC is 1 and performs the parallel load operation when the clock BC is 0. FIG. 4 is a time chart of this modulation circuit, which is a premise of the demodulation method . FIG. 4A shows a clock 2BC having a period of 0.5T, and FIG. 4B shows a clock BC of a period T. 2A as an example of the input data bit sequence DIN
The signal waveform when the one shown in FIG. Therefore, from the shift register 2 to FIG.
As shown in (3), three data bit sequences delayed by T appear, and each of them includes A (2), A (1), and A (0) bits. FIG. 4D shows a signal OD (0) which becomes 1 when the bit A (0) is 1 and is an odd number. FIG. 4E shows the center inversion signal Ct (0) which becomes 1 in the bit cell which causes inversion in the center. FIG. 4F shows an edge inversion signal Eg which becomes 1 in the bit cell which causes inversion at the edge.
(0). This edge inversion signal Eg (0) is delayed by the flip-flop 11 by T to become the edge inversion signal Eg (-1) shown in FIG. 4I. Of the edge inversion signal Eg (0), 1 is set according to the modulation rule (c) in the 1 section of the discrimination signal EV1 (0) shown in FIG. 4G. This determination signal EV1
(0) is delayed by 3T by the shift register 5,
It becomes the pulse signal EV1 (-3) shown in H. When the input terminal 7A of the switch circuit 6 is selected in the example described above , EV1 (0) and EV1 are selected.
The AND output of both (-3) is output to the OR gate 9 as Ct (-
Supplied with 1). The output Ct 'of this OR gate 9
(-1) and Eg (-1) are loaded in parallel to the shift register 12 by the bit clock BC and output by the clock 2BC. Therefore, the pulse signal TG shown in FIG. 4J is output from the shift register 12, the flip-flop 13 is inverted at the falling edge thereof, and the modulation output DOUT shown in FIG. 4J is formed. In the example which is a premise of the demodulation method in which the input terminal 7B of the switch circuit 6 is selected, the delayed discrimination signal E is used.
AN of V1 (-3) (Fig. 4H) and A (0) (Fig. 4C)
The D output is supplied to the OR gate 9 to generate the output Ct '(-1) of the OR gate 9 shown in FIG. 4K. Then, as shown in FIG. 4K, the output T from the shift register 12
G is supplied to the flip-flop 13, and the modulation output DOU
T is obtained. This modulation output DOUT has the same waveform as that shown in FIG. 2B. [0037] Figure 5 shows the example of the configuration of a demodulation circuit according to the present invention. The reproduced modulated signal DIN is supplied to the input terminal indicated by 21. Input data DI to demodulation circuit
N is supplied to the cascade connection of the flip-flops 22 and 23. A clock ↓ 2BC, which is extracted from the input data DIN and has a period of 0.5T from the terminal 25, is used as a clock input to the flip-flops 22 and 23. The outputs of the flip-flops 22 and 23 are the exclusive OR gate 2
4 and the inversion detection signal is taken out at the output of the exclusive OR gate 24. The inversion detection signal is
It is a pulse signal which becomes 1 in the period of 0.5T at the inversion position. The inversion detection signal is input to the shift register 26, subjected to serial-to-parallel conversion processing, and converted into a 2-bit parallel signal. The shift register 26 is
Clock ↓ Shifts with 2BC. Clock ↓ 2B
C is inverted by the inverter 27, and the (1/2) frequency divider circuit 28
The bit clock BC is divided by. The (1/2) frequency divider circuit 28 is supplied with a reset pulse formed by detecting a sync pattern added to the modulated signal, and the phase of the bit clock BC is the phase of the bit clock at the time of modulation. It is made to match the phase. The bit clock BC is used as a bit clock for flip-flops and shift registers provided after the shift register 26. The 2-bit parallel output of the shift register 26 is delayed by 1 bit by each of the flip-flops 29 and 30 to be a center inversion signal Ct '(0) and an edge inversion signal Eg (0). This Ct '(0) is A
It is supplied to one input terminal of the ND gate 31. AND
The other input terminal of the gate 31 has a discrimination signal E described later.
V1 (−2) is supplied via the inverter 32. A
Center inversion signal Ct output from the ND gate 31
(0) becomes 1 in the bit cell in which the inversion occurs in the center, and the edge inversion signal Eg from the flip-flop 30 is generated.
(0) becomes 1 in the bit cell where inversion occurs at the boundary. The center inversion signal Ct (0) and the edge inversion signal Eg (0) and the signals Eg (-1) and Ct obtained by delaying the center inversion signal Et (0) by flip-flops 33 and 34, respectively.
(-1) is supplied to the demodulation logic 36. The center inversion signal Ct (0) is input to the J input of the JK flip-flop 35.
Is supplied. The K input of this flip-flop 35 is
It is always set to 1. Therefore, the flip-flop 3
At the output of 5, a pulse ODc (-1) of which Ct (-1) which becomes 1 becomes 1 when the odd number is generated is supplied to the demodulation logic 36. Demodulation logic 36 is a combinational circuit or ROM that produces an output based on the following logical equation: EV1 (0) = Eg (0) · Ct (−1) · ↓ ODc (−1) + Eg (0) · ↓ Eg (−1) · ↓ D (−1) D (0) = Ct ( 0) + EV1 (0) + EV1 (-1) This demodulation logic 36 is for detecting when the demodulation output is 1. The output D (0) of the demodulation logic 36 is delayed by T by the flip-flop 37 and is taken out to the output terminal 38 as a demodulation output (waveform of NRZ). At the same time, the output of the flip-flop 37 is D
It is input to the demodulation logic 36 as (-1). The discrimination signal EV1 (0) from the demodulation logic 36 is supplied to the 2-bit shift register 39. This shift register 3
The discrimination signal EV1 (-1) from 9 is supplied to the demodulation logic 36, and the discrimination signal EV1 (-2) is supplied to the AND gate 31 via the inverter 32. From the modulation rule (b), it is clear that when Ct (0) is 1, the demodulation output D (0) is 1. Also, according to the modulation rule (c), the data bit is 1
However, the discrimination signal EV1 (0) becomes 1 when the signal is inverted at the boundary. Eg of the above formula
The term of (0) · Ct (−1) · ↓ ODc (−1) is shown in FIG.
As shown in A, there is an even number of 1's in the original data series, which is 4 or more (4 in the example shown in the figure).
Becomes In the case of this data series, the modulation signal DIN shown in FIG. 6B is supplied to the demodulation circuit. Therefore, as shown in FIG. 6B, both the center inversion signal Ct (-1) and the edge inversion signal Eg (0) become 1. This Ct (-1) becomes 1 at the time of even-numbered 1, so ODc (-1) is 0.
Therefore, due to these conditions, EV1 (0) becomes 1 as shown in FIG. 6C. In addition, the shift register 3
↓ EV1 (-2) delayed by 2T by 9 becomes 0. As a result, the center inversion signal cannot pass through the AND gate 31. This is the modulation rule (d)
This is because the inversion at the center of the bit cell of 0 caused by is prohibited. Eg (0). ↓ Eg (-
1)-↓ D (-1) is for detecting the case where two 1's are continuous in the original data series as shown in FIG. 7A. In this case, as shown in FIG. 7B, a modulation signal DIN which is inverted at the bit cell boundary is generated. As is clear from FIGS. 7A and 7B, each component of the above term becomes 1, and as shown in FIG. 7C, the determination signal EV1
(0) becomes 1. Also, when modulation rule (d) is applied, an inversion occurs in the center of the 0 bit cell after the two 1s. In order to prohibit the inversion detection output at the center, E
V1 (−2) is supplied to the AND gate 31. In addition to the above configuration, various circuit configurations are possible as the modulation circuit and the demodulation circuit. [0048] [Effect of the Invention] demodulation process of the digital data of the invention is applied, it is possible to zero the DC component, recording apparatus using a rotary head, a channel coding, such as optical disk reproducing apparatus By doing so, it is possible to reduce the distortion (peak shift) of the recording waveform and remove low frequency noise. Further, demodulation method of the present invention, it is possible to shorten the maximum inversion interval compared to M ² modulation and M ³ modulation, it is possible to achieve further reduction of the low-frequency component of the modulated output, the clock reproduction capability Can be improved.

BRIEF DESCRIPTION OF THE DRAWINGS FIG. 1 is a reference for explaining an embodiment to which the present invention can be applied.
3 is a waveform diagram used to describe an example of a modulation method for [2] One modulation method underlying the demodulation method of the present invention
It is a waveform diagram used for description of an example . FIG. 3 is a block diagram of an example of a modulation circuit which is a premise of the demodulation method of the present invention . FIG. 4 is a time chart used for explaining a modulation circuit which is a premise of the demodulation method of the present invention . FIG. 5 is a block diagram of an example of a demodulation circuit to which the present invention is applied. FIG. 6 is a time chart used for explaining this demodulation circuit. FIG. 7 is a time chart used for explaining this demodulation circuit. [Explanation of Codes] 1 Input terminal 3 of data bit series 3 Modulation logic 6 Switch circuit 21 Input terminal 36 of modulated data bit series 36 Demodulation logic

   ─────────────────────────────────────────────────── ─── Continued front page    (56) References JP-A-57-27412 (JP, A)               JP-A-57-28456 (JP, A)               Japanese Patent Publication 4-46017 (JP, B2)               Japanese Patent Publication 2-50549 (JP, B2)               Japanese Patent Publication Sho 63-26473 (JP, B2)               International Publication 85-67 (WO, A)               US Patent 4672363 (US, A)               European Patent 144449 (EP, B)

Claims (1)

Claims: A data bit sequence consisting of bits having a first value or a second value is (a) when the bits of the second value are consecutive, the bit cells of the consecutive bits of the second value are Inversion at a boundary, (b) inversion in the center of the bit cell of the bit of the first value, (c) of an even number of bits of the first value sandwiched between bits of the second value, Suppress the inversion at the center of the bit cell of the last two bits of the first value and invert at the boundary of the two bit cells of the first value, (d) follow the bit of the second value When a 2-bit pattern of (bit of the second value, bit of the first value) comes to the position next to the even number of bits of the first value, the bit of the two bits Invert at the center of the bit cell of the second value bit, which satisfies the condition And (e) edge inversion detection means for detecting signal inversion at the boundary of the bit cell to demodulate the modulated signal generated by causing inversion as the state transition and obtain the data bit sequence. (F) center inversion detection means for detecting signal inversion at the center of the bit cell , (g) delay means for delaying the output of the edge inversion detection means, the output of the center inversion detection means, and the demodulation output, (H) On the basis of the outputs of the edge inversion detection means, the center inversion detection means, and the delay means, the signal is inverted at the boundary of the bit cell even though the data bit has the first value corresponding to (c). A method for demodulating digital data, comprising means for determining when the signal is inverted and when the signal is inverted at the center of the bit cell of the second value corresponding to (d) above.