JPH0738109A - Semiconductor device and manufacture thereof - Google Patents

Abstract

PURPOSE:To make it possible to decrease threshold voltage without lowering short channel effect and mutual conductance by preventing deterioration in characteristics by hot carrier. CONSTITUTION:An N-channel MOS transistor of LDD structure, on which a drain region 4 is formed by an N<-> layer 4a and an N<+> layer 4b is formed on a P-type substrate l. The center part of the channel part, located directly under a gate electrode 3, is composed of a P<-> layer (same as substrate 1) of almost uniform low density. On the other hand, the surface part 6 of the substrate 1 in the region, where the gate region of the end part of the channel part are overlapped, is composed of a P layer of the low density same as the substrate 1. Also, the part 7 of the prescribed depth in the substrate 1 located under the surface part 6 of the region, where the gate region and the drain region, consists of the P<+> layer of a concentration higher than that of the substrate 1.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device and a method of manufacturing the same, and more particularly, to a lightly doped drain (LD).
D: Lightly Doped Drain) MOS transistor and its manufacturing method.

[0002]

2. Description of the Related Art In recent years, the problem of hot carriers has become important with the miniaturization of semiconductor devices.

The hot carriers are carriers of electrons or holes that are not in thermal equilibrium with the crystal lattice in the solid body which is the semiconductor substrate, and have high energy.
If hot carriers are injected into the gate oxide film of the MOS transistor or create a surface level, the characteristics of the transistor are deteriorated (specifically, the threshold voltage of the transistor is moved in the positive direction). Or reduce the mutual conductance). The characteristic deterioration of the transistor due to the hot carriers is particularly remarkable in the NMOS transistor having a gate length of submicron (1 μm) or less.

In order to avoid this, it is effective to relax the electric field in the vicinity of the drain region to reduce the substrate current, and a typical method is the LDD structure. In the LDD structure, a high-concentration impurity layer (n ⁺ layer in the N-channel MOS transistor, p layer in the P-channel MOS transistor)
⁺ Low concentration impurity layer near the drain due to the layer) (in N-channel MOS transistor n ^- layer, P-channel MOS
In the transistor, a p ⁻ layer is provided, and the electric field near the drain is relaxed by the low concentration impurity layer. In addition, LD
Regarding the D structure, Junichi Nishizawa: Semiconductor Research, No. 26
This is described in detail in the volume "VLSI Technology Device Process No. 11" (published by the Industrial Research Board).

[0005]

By the way, in the LDD structure, it is necessary to increase the concentration of the low concentration impurity layer as the gate length becomes shorter due to miniaturization (G. Krieger, et a.
l., “Moderately Doped NMOS (M-LDD) -HOT electron an
d Current Drive Optimization. ”IEEE Trans. Electro
n Devices, vol.38, pp.121-127.).

However, shortening the gate length and increasing the concentration of the low concentration impurity layer leads to promotion of the short channel effect. When the short channel effect occurs, the threshold voltage is lowered, a desired value cannot be obtained, the expected circuit operation cannot be performed, and the power consumption is increased. If the short channel effect becomes more severe, punch-through will occur and the MOS transistor will not operate. Punch-through is a phenomenon in which the depletion layer on the drain side extends and the potential under the gate cannot be controlled by the gate voltage, and as the drain voltage is increased, the drain current flows even if the gate voltage is 0V.

As a method for solving this, Japanese Patent Laid-Open No. 3-2
As disclosed in Japanese Patent No. 36279, there has been proposed a method (generally called a counter-doping method) in which the surface concentration of the channel portion is lowered and the deep portion is made highly concentrated. In this publication, arsenic is ion-implanted into a P-well formed by injecting boron at a higher concentration than usual to reduce the surface concentration of the channel portion and control the threshold voltage.

In this counter-doping method, the maximum electric field strength of the drain region is deeper than half the diffusion depth of the drain. As a result, the maximum electric field strength of the drain region deviates from the current path and separates from the gate oxide film, so that hot carriers can be prevented from being injected into the gate oxide film.

However, the counter-doping method is
Although it is possible to improve the short-channel effect, it has been reported that it causes a significant decrease in transconductance (Katsuhiko Ichinose et al .: “Counter-doped NMOSFET characteristics”, 1992 Autumn Meeting of the Applied Physics Society, 1
7p-ZS-1.p.654.). According to this report, in the counter-doping method, the transconductance decreases due to factors other than the surface electric field, and it is considered that the decrease in carrier mobility due to impurity scattering is a possible cause.

That is, although the LDD structure is used to prevent the reduction of the mutual conductance due to hot carriers, there is a problem that when the counter-doping method is used together, the mutual conductance becomes lower than that of the conventional structure.

Further, in recent years, it has been required to lower the power supply voltage in order to increase the speed of the semiconductor device, and accordingly, the threshold voltage also needs to be lowered. Therefore, not only the positive shift of the threshold voltage due to hot carriers must be prevented, but also the threshold voltage must be lowered more positively.

The present invention has been made to solve the above problems, and an object thereof is to prevent characteristic deterioration due to hot carriers and to prevent a short channel effect and a reduction in mutual conductance. An object of the present invention is to provide a semiconductor device that can reduce the threshold voltage.

[0013]

According to the present invention, a substrate impurity profile in a central portion of a channel portion immediately below a gate and a substrate impurity profile in a region where a gate region and a drain region at an end portion of the channel portion overlap each other are provided. In contrast, the impurity concentration of the surface portion of the substrate in the region where the gate region and the drain region overlap is low,
The gist is that the impurity concentration of the portion under the surface portion up to a predetermined depth inside the substrate is high.

[0014]

Therefore, according to the present invention, the counter-doping method is applied to the region where the gate region and the drain region overlap. That is, most of the hot carriers are generated at the interface between the gate insulating film and the substrate, but in the present invention, the interface portion (the surface portion of the substrate in the region where the gate region and the drain region overlap) has a low concentration. I have to. Therefore, generation of hot carriers at the interface between the gate insulating film and the substrate can be suppressed, and as a result, most of the hot carriers can be suppressed. As a result, the short channel effect can be solved while preventing the characteristic deterioration due to hot carriers.

Further, since the substrate impurity profile of the central portion of the channel portion and the substrate impurity profile of the region where the gate region and the drain region of the end portion of the channel portion overlap each other are different, the counter doping method is applied to the entire channel portion. When applied, no problem of reduction in transconductance occurs.

Further, the threshold voltage can be controlled independently for the central portion of the channel portion regardless of the structure of the end portion of the channel portion, so that the threshold voltage can be easily lowered.

[0017]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment in which the present invention is embodied in an N-channel MOS transistor will be described below with reference to FIGS.

FIG. 1 is a sectional view of an N-channel MOS transistor of this embodiment. An LDD structure N-channel MOS transistor is formed on a p-type single crystal silicon substrate 1 formed of a low concentration p ⁻ layer. That is, the gate electrode 3 is formed on the substrate 1 via the gate oxide film 2. In addition, a drain region or a source region (hereinafter, referred to as a drain region for convenience of description) 4 is formed on the surface of the substrate 1 so as to sandwich the gate electrode 3. Then, sidewall spacers 5 made of a silicon oxide film are formed on the sidewalls of the gate oxide film 2 and the gate electrode 3.

Immediately below the side wall spacer 5 and its side
The drain region 4 in the vicinity has a low concentration of n.^-Made of layer 4a
ing. On the other hand, it was separated from the sidewall spacer 5
The drain region 4 of the portion is a high concentration n⁺Made of layer 4b
ing. This n^-Layers 4a and n ⁺Layer 4b and drain region
Regarding the point that region 4 is composed,
Is the same.

The central portion of the channel portion just below the gate electrode 3 has a substantially uniform low-concentration p ^- layer (the substrate 1) as in the conventional N-channel MOS transistor having no LDD structure.
Same as).

On the other hand, the surface portion 6 of the substrate 1 in the region where the gate region and the drain region at the end of the channel portion overlap each other is composed of a p ⁻ layer having the same low concentration as the substrate 1. Further, the substrate 1 under the surface portion 6 in the region where the gate region and the drain region overlap each other
The portion 7 up to a predetermined depth inside is formed of a p ⁺ layer having a higher concentration than that of the substrate 1.

Next, the N of the present embodiment constructed as described above is used.
The manufacturing process of the channel MOS transistor will be described. Step 1 (see FIG. 2): On the P-type single crystal silicon substrate 1,
Normal channel implantation for controlling the threshold voltage is performed to make the substrate 1 a low concentration p ⁻ layer (not shown). This controls the threshold voltage.

Then, a gate oxide film 2 is formed on the surface of the substrate 1. Any method (oxidation method, CVD method, PVD method, etc.) may be used for forming the gate oxide film 2. Next, the gate electrode 3 is formed on the gate oxide film 2. What material is used to form this gate electrode 3 (polysilicon gate, polycide gate, metal gate, etc.)
May be used.

Step 2 (see FIG. 3): implantation energy; 2
00 KeV, dose; 5 × 10¹²cm ^-2, Tilt angle; 60 °
The gate electrode 3 and gate oxide film 2 are
As a mask, rotating oblique ion implantation of arsenic is performed on the substrate 1.
U

As a result, not only the exposed surface portion of the substrate 1 but also the lower portion 11 of the end portion of the gate oxide film 2 in the surface portion of the substrate 1 covered with the gate oxide film 2 is exposed.
A low-concentration n ⁻ layer 11 is formed in a (that is, the surface portion 6 of the substrate 1 in the region where the gate region and the drain region at the end of the channel portion overlap).

Step 3 (see FIG. 4): implantation energy; 5
Under the conditions of 0 KeV, dose amount: 1 × 10 ¹³ cm ^-2 , and inclination angle: 30 °, the substrate 1 is subjected to rotational oblique ion implantation of boron using the gate electrode 3 and the gate oxide film 2 as a mask.

As a result, the p ⁺ layer 12 having a higher concentration than that of the substrate 1 is formed in the portion of the substrate 1 up to a predetermined depth. Further, the low-concentration n ⁻ layer 11 has a low-concentration p − level similar to that of the substrate 1 due to the implantation of boron, which is a P-type impurity.
^- made to layer 13. That is, in the active region other than the central portion of the channel portion immediately below the gate electrode 3, the surface portion of the substrate 1 (that is, the surface portion 6 shown in FIG. 1) has a low concentration (p ⁻
The layer 13) and the portion to the predetermined depth inside the substrate 1 (that is, the portion 7 shown in FIG. 1) have a high concentration (p ⁺ layer 12). This is no exception to the fact that the counter-doping method is applied to the region where the gate region and the drain region at the end of the channel portion overlap, except for the central portion of the channel portion directly below the gate electrode 3.

Step 4 (see FIG. 5): A TEOS film having a film thickness corresponding to the gate oxide film 2 and the gate electrode 3 is formed on the surface of the substrate 1 by the CVD method. Then, the formed TEOS film is removed by the entire surface etch-back method so that only the TEOS film on the sidewalls of the gate oxide film 2 and the gate electrode 3 remains. The remaining TEOS film becomes the sidewall spacer 5.

Step 5 (see FIG. 6): implantation energy; 5
Under the conditions of 0 KeV, dose amount: 8 × 10 ¹³ cm ^-2 , and inclination angle: 15 °, the substrate 1 is subjected to rotational oblique ion implantation of phosphorus using the sidewall spacers 5 as a mask.

[0030] By rotation oblique ion implantation of phosphorus is this N-type impurity, p ⁺ layer 12 and p ^- portion corresponding to the drain region 4 in the layer 13 (i.e., p ⁺ layer 12 and p ^- the layer 13, FIG. 1 (A portion other than the portion 7 and the surface portion 6 shown in FIG. 3) becomes a low concentration n ⁻ layer 14.

Step 6 (see FIG. 1): implantation energy; 8
Arsenic ions are vertically implanted into the substrate 1 by using the sidewall spacers 5 as a mask under the conditions of 0 KeV and a dose amount of 5 × 10 ¹⁵ cm ^-2 .

As a result, the portion of the low-concentration n ⁻ layer 14 distant from the sidewall spacer 5 becomes the high-concentration n ⁺ layer 4b. Step 7: By performing heat treatment, the implanted impurities are appropriately diffused so as to have a desired impurity profile. As a result, the structure shown in FIG. 1 can be obtained.

As described above, in the present embodiment, the threshold value control by the normal channel implantation is performed on the central portion of the channel portion directly below the gate electrode 3, and the central portion of the channel portion has a low concentration (p ⁻ The layer) reduces the threshold voltage. Then, the counter-doping method is applied only to the region where the gate region and the drain region at the end of the channel portion overlap, except for the central portion of the channel portion. That is, the surface portion 6 of the substrate 1 in the region where the gate region and the drain region overlap each other has a low concentration (p ⁻ layer),
The portion 7 up to a predetermined depth inside is made to have a high concentration (p ⁺ layer).

Therefore, in this embodiment, Japanese Patent Laid-Open No. 3-236 is used.
Similar to Japanese Patent No. 279, the short channel effect can be solved while preventing characteristic deterioration due to hot carriers. That is, most of the hot carriers are generated at the interface between the gate oxide film 2 and the substrate 1, but in this embodiment, the interface portion (that is, the surface portion 6) has a low concentration. Therefore, generation of hot carriers at the interface between the gate oxide film 2 and the substrate 1 can be suppressed, and as a result, most of the hot carriers can be suppressed. As a result, the maximum point of the electric field strength of the drain region 4 is deeper than half the diffusion depth of the drain. As a result, the maximum electric field strength of the drain region 4 deviates from the current path and is separated from the gate oxide film 2, so that hot carriers can be prevented from being injected into the gate oxide film 2.

In addition, in this embodiment, the counter-doping method is applied only to the region where the gate region and the drain region at the end of the channel portion overlap with each other, and the counter-doping method is applied to the central portion of the channel portion. The threshold is controlled by channel injection. Therefore, according to the present embodiment, the transconductance, which is a problem when the counter-doping method is applied to the entire channel portion as in JP-A-3-236279, does not occur.

Further, in the present embodiment, the threshold control is performed independently of the n ⁻ layer 4a of the LDD structure and each of the portions 6 and 7 to which the counter-doping method is applied by controlling the threshold of the central portion of the channel portion. The voltage can be set. Therefore, according to this embodiment, the threshold voltage can be easily lowered.

The present invention is not limited to the above embodiment, but may be carried out as follows. 1) Rather than performing a collective heat treatment in step 7,
Heat treatment is performed in each of the steps 2, 3, 5, and 6.

2) Step 3 is performed first, and then step 2 is performed. At this time, when the heat treatment is performed in each of step 2 and step 3, the heat treatment in step 3 may be omitted and the heat treatment in step 2 may also be performed.

3) Steps 1, 4, 5 and 6 are carried out first, and then steps 2 and 3 are carried out. 4) The rotating oblique ion implantation in step 3 is replaced with ion implantation perpendicular to the substrate, and the implanted boron is diffused to a predetermined region by heat treatment.

5) The impurities (boron, arsenic, phosphorus) implanted in the steps 1, 2, 3, 5, 6 are replaced with other impurities of the same conductivity type (for example, boron → indium,
Arsenic → antimony, arsenic → phosphorus, etc.).

6) The n ⁻ layer 4a is omitted, and the drain region 4 is formed only from the n ⁺ layer 4b. In this case, since the LDD structure is not used, the effect of suppressing hot carriers is slightly inferior to that of the above-mentioned embodiment, but almost the same effect can be obtained.

7) Since steps 4 to 6 are steps for forming an LDD structure, these steps 4 to 6 are LD
The following or method known as a method for creating the D structure is replaced.

First, ion implantation perpendicular to the substrate 1 is performed to form a low concentration n ^- layer 4a. Next, the sidewall spacers 5 are formed. Subsequently, using the sidewall spacers 5 as a mask, ions are implanted perpendicularly to the substrate 1 to form a high-concentration n ⁺ layer 4b.

First, as in step 4,
The spacer 5 is formed. Next, using the sidewall spacers 5 as a mask, ions are implanted perpendicularly to the substrate 1 to form a high-concentration n ⁺ layer 4b. Then, the sidewall spacers 5 are removed. Then, ion implantation perpendicular to the substrate 1 is performed to form a low concentration n ⁻ layer 4a. After that, the sidewall spacers 5 are formed again.

8) A P-well is formed on the substrate 1, and an N-channel transistor similar to that in the above embodiment is formed in the P-well. 9) Reverse the conductive gas of the above embodiment to obtain a P channel MOS.
Embody it in a transistor.

10) The above 1) to 9) are appropriately combined and carried out.

[0047]

As described in detail above, according to the present invention, it is possible to prevent the characteristic deterioration due to hot carriers and to reduce the threshold voltage without causing the short channel effect and the decrease in the mutual conductance. It has the excellent effect that

[Brief description of drawings]

FIG. 1 is a sectional view of an N-channel MOS transistor according to an embodiment of the present invention.

FIG. 2 is a cross-sectional view for explaining the manufacturing process of the embodiment.

FIG. 3 is a cross-sectional view illustrating the manufacturing process of the example.

FIG. 4 is a cross-sectional view illustrating the manufacturing process of the example.

FIG. 5 is a cross-sectional view for explaining the manufacturing process of the embodiment.

FIG. 6 is a cross-sectional view for explaining the manufacturing process of the example.

[Explanation of symbols]

DESCRIPTION OF SYMBOLS 1 p-type single crystal silicon substrate 3 gate electrode 6 surface part of substrate 1 in a region where a gate region and a drain region at an end of a channel part overlap 7 surface part 6 in a region where a gate region and a drain region overlap Under the substrate 1 to a predetermined depth

Claims (2)

[Claims] 1. A substrate impurity profile in a central portion of a channel portion immediately below a gate (3) and a substrate impurity profile in a region where a gate region and a drain region at an end portion of the channel portion overlap each other are different from each other. The impurity concentration of the surface portion (6) of the substrate (1) in the region where the drain region and the drain region overlap is low, and a portion (7) below the surface portion (6) up to a predetermined depth inside the substrate (1). 3.) A semiconductor device having a high impurity concentration of. 2. A step of ion-implanting a conductive impurity different from that of the substrate (1) at a predetermined angle with respect to the substrate (1) using the gate electrode (3) as a mask, and the gate electrode (3). 3.) The method of manufacturing a semiconductor device according to claim 1, further comprising the step of: ion-implanting into the substrate (1) the same conductivity type impurity as that of the substrate (1).