JPH04186774A - Semiconductor device - Google Patents

Semiconductor device

Info

Publication number
JPH04186774A
JPH04186774A JP2314000A JP31400090A JPH04186774A JP H04186774 A JPH04186774 A JP H04186774A JP 2314000 A JP2314000 A JP 2314000A JP 31400090 A JP31400090 A JP 31400090A JP H04186774 A JPH04186774 A JP H04186774A
Authority
JP
Japan
Prior art keywords
layer
impurity concentration
surface
layers
source
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP2314000A
Inventor
Masaaki Aoki
Shinpei Iijima
Tatsuya Ishii
Masabumi Miyamoto
Original Assignee
Hitachi Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Hitachi Ltd filed Critical Hitachi Ltd
Priority to JP2314000A priority Critical patent/JPH04186774A/en
Publication of JPH04186774A publication Critical patent/JPH04186774A/en
Application status is Pending legal-status Critical

Links

Abstract

PURPOSE: To prevent punchthrough of a MOS transistor miniaturized in a device size and to improve carrier mobility of an Si surface by setting a distance between the lower surface of second conductivity type source.drain impurity layer and the lower surface of a first conductivity type surface low impurity concentration layer shorter than a channel length between source and drain impurity layers.
CONSTITUTION: A single crystalline Si layer 3 by an epitaxial grown is formed on a high impurity concentration semiconductor substrate region 1, and the thickness of a low impurity concentration layer 8 in the layer 3 is increased as compared with the depths of source, drain impurity layers 4, 5. The concentration of the layer 8 is set to one power or less of the impurity concentration of its lower side high impurity concentration layer 9. Further, in order to substantially completely suppress a punchthrough, a distance (a) between the lower surfaces of the layers 4, 5 and the lower surface of the layer 8 is set to half or less of a channel length L. Thus, bending of a band on the Si surface is alleviated, and carrier mobility is increased more.
COPYRIGHT: (C)1992,JPO&Japio
JP2314000A 1990-11-21 1990-11-21 Semiconductor device Pending JPH04186774A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP2314000A JPH04186774A (en) 1990-11-21 1990-11-21 Semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP2314000A JPH04186774A (en) 1990-11-21 1990-11-21 Semiconductor device

Publications (1)

Publication Number Publication Date
JPH04186774A true JPH04186774A (en) 1992-07-03

Family

ID=18048012

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2314000A Pending JPH04186774A (en) 1990-11-21 1990-11-21 Semiconductor device

Country Status (1)

Country Link
JP (1) JPH04186774A (en)

Cited By (19)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2011103314A1 (en) * 2010-02-18 2011-08-25 Suvolta, Inc. Electronic devices and systems, and methods for making and using the same
JP2013507000A (en) * 2009-09-30 2013-02-28 スボルタ,インコーポレーテッド Electronic device and system, and manufacturing method and usage thereof
US8970289B1 (en) * 2012-01-23 2015-03-03 Suvolta, Inc. Circuits and devices for generating bi-directional body bias voltages, and methods therefor
US8976575B1 (en) 2013-08-29 2015-03-10 Suvolta, Inc. SRAM performance monitor
US8988153B1 (en) 2013-03-09 2015-03-24 Suvolta, Inc. Ring oscillator with NMOS or PMOS variation insensitivity
US8994415B1 (en) 2013-03-01 2015-03-31 Suvolta, Inc. Multiple VDD clock buffer
JP2016516298A (en) * 2013-03-14 2016-06-02 インテル・コーポレーション Nanowire transistor leakage reduction structure
US9449967B1 (en) 2013-03-15 2016-09-20 Fujitsu Semiconductor Limited Transistor array structure
US9680470B2 (en) 2011-02-18 2017-06-13 Mie Fujitsu Semiconductor Limited Digital circuits having improved transistors, and methods therefor
US9786703B2 (en) 2013-05-24 2017-10-10 Mie Fujitsu Semiconductor Limited Buried channel deeply depleted channel transistor
US9793172B2 (en) 2011-05-16 2017-10-17 Mie Fujitsu Semiconductor Limited Reducing or eliminating pre-amorphization in transistor manufacture
US9812550B2 (en) 2012-06-27 2017-11-07 Mie Fujitsu Semiconductor Limited Semiconductor structure with multiple transistors having various threshold voltages
US9853019B2 (en) 2013-03-15 2017-12-26 Mie Fujitsu Semiconductor Limited Integrated circuit device body bias circuits and methods
US9865596B2 (en) 2010-04-12 2018-01-09 Mie Fujitsu Semiconductor Limited Low power semiconductor transistor structure and method of fabrication thereof
US9893148B2 (en) 2013-03-14 2018-02-13 Mie Fujitsu Semiconductor Limited Method for fabricating a transistor device with a tuned dopant profile
US9922977B2 (en) 2010-06-22 2018-03-20 Mie Fujitsu Semiconductor Limited Transistor with threshold voltage set notch and method of fabrication thereof
US9953974B2 (en) 2011-12-09 2018-04-24 Mie Fujitsu Semiconductor Limited Tipless transistors, short-tip transistors, and methods and circuits therefor
US9966130B2 (en) 2011-05-13 2018-05-08 Mie Fujitsu Semiconductor Limited Integrated circuit devices and methods
US10325986B2 (en) 2009-09-30 2019-06-18 Mie Fujitsu Semiconductor Limited Advanced transistors with punch through suppression

Cited By (29)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US10325986B2 (en) 2009-09-30 2019-06-18 Mie Fujitsu Semiconductor Limited Advanced transistors with punch through suppression
JP2013507000A (en) * 2009-09-30 2013-02-28 スボルタ,インコーポレーテッド Electronic device and system, and manufacturing method and usage thereof
US10224244B2 (en) 2009-09-30 2019-03-05 Mie Fujitsu Semiconductor Limited Electronic devices and systems, and methods for making and using the same
US10217668B2 (en) 2009-09-30 2019-02-26 Mie Fujitsu Semiconductor Limited Electronic devices and systems, and methods for making and using the same
US8975128B2 (en) 2009-09-30 2015-03-10 Suvolta, Inc. Electronic devices and systems, and methods for making and using the same
US10074568B2 (en) 2009-09-30 2018-09-11 Mie Fujitsu Semiconductor Limited Electronic devices and systems, and methods for making and using same
WO2011103314A1 (en) * 2010-02-18 2011-08-25 Suvolta, Inc. Electronic devices and systems, and methods for making and using the same
US9865596B2 (en) 2010-04-12 2018-01-09 Mie Fujitsu Semiconductor Limited Low power semiconductor transistor structure and method of fabrication thereof
US9922977B2 (en) 2010-06-22 2018-03-20 Mie Fujitsu Semiconductor Limited Transistor with threshold voltage set notch and method of fabrication thereof
US9985631B2 (en) 2011-02-18 2018-05-29 Mie Fujitsu Semiconductor Limited Digital circuits having improved transistors, and methods therefor
US9680470B2 (en) 2011-02-18 2017-06-13 Mie Fujitsu Semiconductor Limited Digital circuits having improved transistors, and methods therefor
US9838012B2 (en) 2011-02-18 2017-12-05 Mie Fujitsu Semiconductor Limited Digital circuits having improved transistors, and methods therefor
US9966130B2 (en) 2011-05-13 2018-05-08 Mie Fujitsu Semiconductor Limited Integrated circuit devices and methods
US9793172B2 (en) 2011-05-16 2017-10-17 Mie Fujitsu Semiconductor Limited Reducing or eliminating pre-amorphization in transistor manufacture
US9953974B2 (en) 2011-12-09 2018-04-24 Mie Fujitsu Semiconductor Limited Tipless transistors, short-tip transistors, and methods and circuits therefor
US8970289B1 (en) * 2012-01-23 2015-03-03 Suvolta, Inc. Circuits and devices for generating bi-directional body bias voltages, and methods therefor
US10217838B2 (en) 2012-06-27 2019-02-26 Mie Fujitsu Semiconductor Limited Semiconductor structure with multiple transistors having various threshold voltages
US10014387B2 (en) 2012-06-27 2018-07-03 Mie Fujitsu Semiconductor Limited Semiconductor structure with multiple transistors having various threshold voltages
US9812550B2 (en) 2012-06-27 2017-11-07 Mie Fujitsu Semiconductor Limited Semiconductor structure with multiple transistors having various threshold voltages
US8994415B1 (en) 2013-03-01 2015-03-31 Suvolta, Inc. Multiple VDD clock buffer
US8988153B1 (en) 2013-03-09 2015-03-24 Suvolta, Inc. Ring oscillator with NMOS or PMOS variation insensitivity
US9893148B2 (en) 2013-03-14 2018-02-13 Mie Fujitsu Semiconductor Limited Method for fabricating a transistor device with a tuned dopant profile
US9825130B2 (en) 2013-03-14 2017-11-21 Intel Corporation Leakage reduction structures for nanowire transistors
JP2016516298A (en) * 2013-03-14 2016-06-02 インテル・コーポレーション Nanowire transistor leakage reduction structure
US9853019B2 (en) 2013-03-15 2017-12-26 Mie Fujitsu Semiconductor Limited Integrated circuit device body bias circuits and methods
US9449967B1 (en) 2013-03-15 2016-09-20 Fujitsu Semiconductor Limited Transistor array structure
US9786703B2 (en) 2013-05-24 2017-10-10 Mie Fujitsu Semiconductor Limited Buried channel deeply depleted channel transistor
US9991300B2 (en) 2013-05-24 2018-06-05 Mie Fujitsu Semiconductor Limited Buried channel deeply depleted channel transistor
US8976575B1 (en) 2013-08-29 2015-03-10 Suvolta, Inc. SRAM performance monitor

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