JPH0737808A - Manufacture of polycrystalline semiconductor film - Google Patents
Manufacture of polycrystalline semiconductor filmInfo
- Publication number
- JPH0737808A JPH0737808A JP17950393A JP17950393A JPH0737808A JP H0737808 A JPH0737808 A JP H0737808A JP 17950393 A JP17950393 A JP 17950393A JP 17950393 A JP17950393 A JP 17950393A JP H0737808 A JPH0737808 A JP H0737808A
- Authority
- JP
- Japan
- Prior art keywords
- film
- semiconductor film
- polycrystalline silicon
- silicon film
- polycrystalline
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Abstract
Description
【0001】[0001]
【産業上の利用分野】この発明は、多結晶半導体膜の製
造方法に関する。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for manufacturing a polycrystalline semiconductor film.
【0002】[0002]
【従来の技術】ガラス、石英等の絶縁基板上に多結晶シ
リコンを成膜する技術は、高精細液晶ディスプレイ(以
下、TFT−LCDと称する)や周辺駆動回路を同一基
板上に形成した駆動回路一体型TFT−LCDを製造す
る目的で、現在盛んに研究開発が行われている。2. Description of the Related Art A technique for depositing polycrystalline silicon on an insulating substrate such as glass or quartz is a driving circuit in which a high-definition liquid crystal display (hereinafter referred to as TFT-LCD) and a peripheral driving circuit are formed on the same substrate. Currently, research and development are being actively conducted for the purpose of manufacturing an integrated TFT-LCD.
【0003】一般に多結晶シリコンを用いた薄膜トラン
ジスタ(以下、TFTと称する)においては、OFF時
のリーク電流を低減するために、活性層となる多結晶シ
リコンの膜厚を50nm以下としている。Generally, in a thin film transistor using polycrystalline silicon (hereinafter referred to as a TFT), the thickness of polycrystalline silicon, which is an active layer, is set to 50 nm or less in order to reduce the leak current at the time of OFF.
【0004】しかしながら、CVD法により形成した多
結晶シリコン膜では、成長初期に形成された多結晶シリ
コンの結晶性が悪く、膜を厚くしなければ結晶性の良好
な多結晶シリコン膜を得ることが困難であり、従ってT
FTの活性層として十分な特性を有する50nm以下の
薄い多結晶シリコンの膜を形成することができないとい
う問題があった。However, with a polycrystalline silicon film formed by the CVD method, the polycrystalline silicon formed in the initial stage of growth has poor crystallinity, and a polycrystalline silicon film with good crystallinity can be obtained unless the film is thickened. Difficult, so T
There is a problem in that a thin polycrystalline silicon film having a thickness of 50 nm or less having sufficient characteristics cannot be formed as an active layer of FT.
【0005】[0005]
【発明が解決しようとする課題】従来の多結晶シリコン
膜の製造方法においては、成長初期に形成された多結晶
シリコン膜の結晶性が悪く、膜を厚くしなければTFT
の活性層として十分な特性を有する程度の結晶性の良好
な多結晶シリコン膜を得ることができないという問題が
あった。In the conventional method for manufacturing a polycrystalline silicon film, the polycrystalline silicon film formed in the initial stage of growth has poor crystallinity, and the TFT must be thickened unless the film is thickened.
However, there is a problem in that it is not possible to obtain a polycrystalline silicon film having good crystallinity enough to have sufficient characteristics as the active layer.
【0006】この発明は、上記事情を考慮してなされた
もので、その目的とするところは、TFTの活性層とし
て十分な特性を有する多結晶半導体を50nm以下の薄
い膜厚で実現する多結晶半導体膜の製造方法を提供する
ことにある。The present invention has been made in view of the above circumstances, and an object thereof is to realize a polycrystalline semiconductor having a thin film thickness of 50 nm or less, which is a polycrystalline semiconductor having sufficient characteristics as an active layer of a TFT. It is to provide a method for manufacturing a semiconductor film.
【0007】[0007]
【課題を解決するための手段】本発明は、気相成長法に
よって絶縁基板上に多結晶半導体膜を形成する多結晶半
導体膜の製造方法において、絶縁基板上に第1の半導体
膜を気相成長した後この第1の半導体膜をビームアニー
ル法により少なくとも表面を溶融温度より低い温度に加
熱する工程と、この第1の半導体膜上に第2の半導体膜
を気相成長する工程とを具備することを特徴とする多結
晶半導体膜の製造方法を提供するものである。The present invention relates to a method for producing a polycrystalline semiconductor film, which comprises forming a polycrystalline semiconductor film on an insulating substrate by vapor phase epitaxy, wherein a first semiconductor film is vapor-deposited on the insulating substrate. After the growth, the step of heating the first semiconductor film at least at a temperature lower than the melting temperature by a beam annealing method, and the step of vapor-phase growing the second semiconductor film on the first semiconductor film are provided. A method for manufacturing a polycrystalline semiconductor film is provided.
【0008】ここでは、第1の半導体が溶融するまで加
熱するものではなく、溶融温度近傍まで加熱して、少な
くとも第1の半導体層の表面が低水素の層(好ましくは
水素濃度1×1015〜1×1019atom/cm 3 )に改質す
るものである。Here, the first semiconductor is not heated until it is melted, but is heated to near the melting temperature and at least the surface of the first semiconductor layer has a low hydrogen content (preferably a hydrogen concentration of 1 × 10 15). ˜1 × 10 19 atom / cm 3 ).
【0009】特に、ビームアニール法により加熱する第
1の半導体膜の膜厚が50〜10nm以下であることが
得られる多結晶半導体積層膜を結晶性を均一性良く形成
する点から好ましい。Particularly, it is preferable that the thickness of the first semiconductor film to be heated by the beam annealing method is 50 to 10 nm or less in order to form the polycrystalline semiconductor laminated film with good crystallinity.
【0010】[0010]
【作用】絶縁基板上に気相成長法によって多結晶半導体
膜を形成した場合、絶縁基板が非晶質であるため、基板
界面近傍での成長初期膜の結晶性が、一般的に悪くな
る。When the polycrystalline semiconductor film is formed on the insulating substrate by the vapor deposition method, the crystallinity of the initial growth film in the vicinity of the substrate interface generally deteriorates because the insulating substrate is amorphous.
【0011】一方、本発明によれば、半導体膜表面をビ
ームアニール法により表面加熱した後、その上に気相成
長膜を形成するため、この2つの半導体膜の積層膜は薄
くても基板と反対側の表面は結晶性の良好な多結晶もし
くは多結晶に近くTFTの活性層となるのに十分な特性
を有する半導体膜となる。これは、ビームアニール法に
より加熱した第1の半導体膜の表面状態が、ガラス基板
や絶縁膜表面と比較して結晶成長の下地として良好な結
晶性に改質されるためである。On the other hand, according to the present invention, since the surface of the semiconductor film is heated by the beam annealing method and then the vapor phase growth film is formed on the surface, the laminated film of these two semiconductor films can be used as a substrate even if it is thin. The surface on the opposite side becomes a polycrystalline film having a good crystallinity or a semiconductor film having a characteristic close to that of a polycrystalline film and having sufficient characteristics to become an active layer of a TFT. This is because the surface state of the first semiconductor film heated by the beam annealing method is modified to have better crystallinity as a base for crystal growth as compared with the surface of the glass substrate or the insulating film.
【0012】[0012]
【実施例】以下、本発明の詳細を図示の実施例によって
説明する。図1は、本発明の第1の実施例に係る多結晶
シリコン膜の断面図である。これを形成工程に従い説明
すると、最初にガラス基板からなる絶縁基板1上に、プ
ラズマCVD法によりアモルファスシリコン膜2を約1
0nm形成する。この際の形成条件は、SiH4 :20
sccm、H2 :80sccm、0.5Torr、基板温度400℃
で行った(図1(a))。The details of the present invention will be described below with reference to the illustrated embodiments. 1 is a sectional view of a polycrystalline silicon film according to a first embodiment of the present invention. This will be described according to the forming process. First, an amorphous silicon film 2 is formed on the insulating substrate 1 made of a glass substrate by the plasma CVD method to a thickness of about 1 μm.
0 nm is formed. The forming conditions at this time are SiH4: 20
sccm, H2: 80 sccm, 0.5 Torr, substrate temperature 400 ° C
(Fig. 1 (a)).
【0013】次にエキシマレーザを用いたレーザアニー
ル法により、アモルファスシリコン膜2にレーザ照射し
てアモルファスシリコン膜2を改質する。この際のアニ
ール条件は、室温、真空中(1×10-6Torr以下)、照
射エネルギー:100mW/cm2 、照射時間14〜18n
sである。ここでは、あくまでも第1の半導体が溶融す
るまで加熱するものではなく、溶融温度近傍まで加熱す
ることで表面を改質するためのものである。アモルファ
スシリコン膜2に対しては、500℃〜融点まで加熱す
ることが好ましい(図1(b))。Next, the amorphous silicon film 2 is modified by irradiating the amorphous silicon film 2 with a laser by a laser annealing method using an excimer laser. The annealing conditions at this time are room temperature, vacuum (1 × 10 −6 Torr or less), irradiation energy: 100 mW / cm 2 , irradiation time 14 to 18 n
s. Here, it is not for heating the first semiconductor until melting, but for heating the surface of the first semiconductor to near the melting temperature to modify the surface. The amorphous silicon film 2 is preferably heated to 500 ° C. to the melting point (FIG. 1 (b)).
【0014】更に改質したアモルファスシリコン膜2上
に、原料ガスとしてSiH4 +SiF4 あるいはSiH
4 +SiF4 +H2 を用いたプラズマCVD法により、
多結晶シリコン膜3を約40nm形成した。この多結晶
シリコン膜3のプラズマCVD法を更に詳しく説明する
と、平行平板型プラズマCVD装置を用いて、例えば、
基板温度:400℃で、原料ガスとしてSiH4 :2s
ccm,SiF4 :98sccm,H2 :50sccm
を圧力:1Torrで導入し、RFパワー:200Wで
放電を行い、多結晶シリコン膜3を形成した。また、多
結晶シリコン膜3の形成前に、H2 プラズマ或いはSi
F4 プラズマによる界面処理を行ってもよい(図1
(c))。On the further modified amorphous silicon film 2, SiH4 + SiF4 or SiH is used as a source gas.
By the plasma CVD method using 4 + SiF4 + H2,
A polycrystalline silicon film 3 having a thickness of about 40 nm was formed. The plasma CVD method of the polycrystalline silicon film 3 will be described in more detail. For example, using a parallel plate plasma CVD apparatus,
Substrate temperature: 400 ° C, SiH4: 2s as source gas
ccm, SiF4: 98 sccm, H2: 50 sccm
Was introduced at a pressure of 1 Torr and discharged at an RF power of 200 W to form a polycrystalline silicon film 3. Before forming the polycrystalline silicon film 3, H2 plasma or Si is used.
Interfacial treatment with F4 plasma may be performed (Fig. 1
(C)).
【0015】このような製造方法により形成した多結晶
シリコン膜では、全体の膜厚が約50nmと薄いにもか
かわらず、断面TEMによる評価を行ったところ、第1
層の界面からSiの(220)に対応する明瞭なピーク
が観察され、良好な結晶性の多結晶シリコン膜を形成で
きることがわかった。比較のために、50nmの多結晶
シリコン膜をプラズマCVD法により一度に形成したも
のの断面TEMによる評価を行ったところ、小さな結晶
粒(微結晶粒)のみであり、良好な結晶性の多結晶シリ
コン膜を形成できていないことがわかった。The polycrystalline silicon film formed by such a manufacturing method was evaluated by cross-sectional TEM even though the total film thickness was as thin as about 50 nm.
A clear peak corresponding to Si (220) was observed from the interface of the layers, and it was found that a polycrystalline silicon film with good crystallinity could be formed. For comparison, a 50 nm polycrystalline silicon film formed at one time by the plasma CVD method was evaluated by a cross-sectional TEM. As a result, it was found that only small crystal grains (fine crystal grains) were present, and polycrystalline silicon with good crystallinity was obtained. It was found that the film could not be formed.
【0016】図2は、本発明の第2の実施例に係る多結
晶シリコンTFTの断面図である。以下、これを製造工
程に従い説明する。最初にガラス基板からなる絶縁基板
1上にSiO2 膜からなるアンダーコート層4を形成し
た後、第1の実施例と同様な方法によりアモルファスシ
リコン膜2,多結晶シリコン3をそれぞれ10nm、4
0nm形成する(図2(a))。FIG. 2 is a sectional view of a polycrystalline silicon TFT according to the second embodiment of the present invention. This will be described below according to the manufacturing process. First, an undercoat layer 4 made of a SiO2 film is formed on an insulating substrate 1 made of a glass substrate, and then an amorphous silicon film 2 and a polycrystalline silicon film 3 having a thickness of 10 nm and 4 respectively are formed by the same method as in the first embodiment.
0 nm is formed (FIG. 2A).
【0017】次に、シリコン膜2,3を島状にパターニ
ングした後、SiO2 膜からなるゲート絶縁膜5をEC
RプラズマCVD法により形成する(図2(b))。次
に、MoやTa等の高融点金属あるいはドープした多結
晶シリコンからなるゲート電極6を形成し、パターニン
グした後、イオンドーピング法によりPあるいはB等の
ドーパントを打ち込み、エキシマレーザアニール法によ
りドーパントを活性化し、ソース・ドレイン領域7を形
成する(図2(c))。Next, after patterning the silicon films 2 and 3 into islands, the gate insulating film 5 made of a SiO2 film is subjected to EC.
It is formed by the R plasma CVD method (FIG. 2B). Next, after forming the gate electrode 6 made of a refractory metal such as Mo or Ta or doped polycrystalline silicon, and patterning it, a dopant such as P or B is implanted by an ion doping method, and a dopant is added by an excimer laser annealing method. It is activated and the source / drain regions 7 are formed (FIG. 2C).
【0018】最後に、SiO2 膜からなる層間絶縁膜8
を形成し、ソース・ドレインのコンタクト・ホールを形
成した後、Alからなるソース・ドレイン電極9をスパ
ッターにより形成し、パターニングを行い、多結晶シリ
コンTFTが完成した(図2(d))。Finally, the interlayer insulating film 8 made of SiO2 film
After forming a source / drain contact hole, a source / drain electrode 9 made of Al was formed by sputtering and patterned to complete a polycrystalline silicon TFT (FIG. 2D).
【0019】このような製造方法により形成した多結晶
シリコンTFTは、ON/OFF比:105 以上、電界
効果移動度:約50cm2 /V・secと良好な特性が
得られた。比較のために、上述した多結晶シリコン膜
2,3を合計した膜厚の多結晶シリコン膜を連続して気
相成長し、エキシマレーザアニールを行う以外は第2の
実施例と同様に形成したTFTを評価した結果、ON/
OFF比:105 、電界効果移動度:5cm2 /V・s
ecでり、良好な特性を得ることができなかった。The polycrystalline silicon TFT formed by such a manufacturing method had good characteristics such as an ON / OFF ratio of 10 5 or more and a field effect mobility of about 50 cm 2 / V · sec. For comparison, a polycrystalline silicon film having a total film thickness of the above-described polycrystalline silicon films 2 and 3 was formed in the same manner as in the second embodiment except that vapor phase growth was continuously performed and excimer laser annealing was performed. As a result of evaluating the TFT, ON /
OFF ratio: 10 5 , field effect mobility: 5 cm 2 / V · s
ec, and good characteristics could not be obtained.
【0020】本発明はその趣旨の範囲内において以下の
ように種々変形しても良い。 (1)第1及び第2の半導体層は、シリコンを使用した
が、これ以外の半導体例えばC、SiC、Ge等でも同
様に形成することができる。 (2)気相成長法は、プラズマCVD法を使用したが、
これ以外の方法例えば、ECRプラズマCVD法であっ
ても良い。 (3)ビームアニール法は、レーザービームを使用した
が、他のエネルギビーム例えば電子ビームを使用しても
良い。 (4)本発明は、TFT以外の他のデバイス、例えば多
結晶半導体層にPN接合を有するダイオードにも適用で
きる。The present invention may be variously modified within the scope of the spirit thereof as follows. (1) Although silicon is used for the first and second semiconductor layers, other semiconductors such as C, SiC, and Ge can be similarly formed. (2) The plasma CVD method was used as the vapor phase growth method.
Other methods, for example, ECR plasma CVD method may be used. (3) The beam annealing method uses a laser beam, but other energy beams such as an electron beam may be used. (4) The present invention can be applied to devices other than TFTs, for example, a diode having a PN junction in a polycrystalline semiconductor layer.
【0021】[0021]
【発明の効果】以上述べたように本発明の多結晶シリコ
ン膜の製造方法によれば、薄い膜においても、TFTの
活性層に使用でき得る程度の結晶性の良好な多結晶シリ
コン膜を得ることができる。As described above, according to the method for producing a polycrystalline silicon film of the present invention, a polycrystalline silicon film having a good crystallinity that can be used as an active layer of a TFT can be obtained even with a thin film. be able to.
【図1】本発明の第1の実施例に係る多結晶シリコン薄
膜の工程順の断面図。FIG. 1 is a sectional view of a polycrystalline silicon thin film according to a first embodiment of the present invention in process order.
【図2】本発明の第2の実施例に係るTFTの工程順の
断面図。2A to 2D are cross-sectional views in the order of steps of a TFT according to a second embodiment of the present invention.
1…絶縁基板 2…シリコン膜(アモルファスシリコン膜) 3…多結晶シリコン膜 4…アンダーコート層 5…ゲート絶縁膜 6…ゲート電極 7…ソース・ドレイン領域 8…層間絶縁膜 9…ソース・ドレイン電極 DESCRIPTION OF SYMBOLS 1 ... Insulating substrate 2 ... Silicon film (amorphous silicon film) 3 ... Polycrystalline silicon film 4 ... Undercoat layer 5 ... Gate insulating film 6 ... Gate electrode 7 ... Source / drain region 8 ... Interlayer insulating film 9 ... Source / drain electrode
Claims (1)
半導体膜を形成する多結晶半導体膜の製造方法におい
て、 絶縁基板上に第1の半導体膜を気相成長した後この第1
の半導体膜をビームアニール法により少なくとも表面を
溶融温度より低い温度に加熱して低水素層に改質する工
程と、 この第1の半導体膜上に第2の半導体膜を気相成長する
工程とを具備することを特徴とする多結晶半導体膜の製
造方法。1. A method of manufacturing a polycrystalline semiconductor film, which comprises forming a polycrystalline semiconductor film on an insulating substrate by a vapor phase growth method, comprising: forming a first semiconductor film on the insulating substrate by vapor phase growth;
A step of heating at least the surface of the semiconductor film to a temperature lower than the melting temperature by a beam annealing method to modify it into a low hydrogen layer, and a step of vapor-depositing a second semiconductor film on the first semiconductor film. A method for manufacturing a polycrystalline semiconductor film, comprising:
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP17950393A JPH0737808A (en) | 1993-07-21 | 1993-07-21 | Manufacture of polycrystalline semiconductor film |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP17950393A JPH0737808A (en) | 1993-07-21 | 1993-07-21 | Manufacture of polycrystalline semiconductor film |
Publications (1)
Publication Number | Publication Date |
---|---|
JPH0737808A true JPH0737808A (en) | 1995-02-07 |
Family
ID=16066958
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP17950393A Pending JPH0737808A (en) | 1993-07-21 | 1993-07-21 | Manufacture of polycrystalline semiconductor film |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPH0737808A (en) |
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US6846728B2 (en) | 1999-09-08 | 2005-01-25 | Matsushita Electric Industrial Co., Ltd. | Semiconductor thin film, semiconductor device employing the same, methods for manufacturing the same and device for manufacturing a semiconductor thin film |
-
1993
- 1993-07-21 JP JP17950393A patent/JPH0737808A/en active Pending
Cited By (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US6846728B2 (en) | 1999-09-08 | 2005-01-25 | Matsushita Electric Industrial Co., Ltd. | Semiconductor thin film, semiconductor device employing the same, methods for manufacturing the same and device for manufacturing a semiconductor thin film |
KR100797018B1 (en) * | 1999-09-08 | 2008-01-22 | 마쯔시다덴기산교 가부시키가이샤 | Semiconductor thin film, semiconductor device employing the same, methods for manufacturing the same and device for manufacturing a semiconductor thin film |
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