JPH04163910A - Semiconductor thin film production method - Google Patents

Abstract

PURPOSE:To prepare poly-Si with a large particle diameter and low resistance in a short anneal period of time by using a mixed gas which consists of forma tion gas of an amorphous semiconductor film whose main component is silicon diluted with helium. CONSTITUTION:An amorphous or polycrystalline Si thin film with a thickness of about 1,000-1,500Angstrom is formed on a quartz substrate 300 by PCVD or reduced pressure vapor phase growth. After this Si thin film is etched to the pattern for the TFT channel region 301, particle diameter is increased by solid phase growth and laser annealing. In order to perform this solid phase growth and anneal process and create poly-Si with particle diameters of a few microns, a mixed gas that consist of the formation gas SiH4 and He gas with the following proportion, (SiH4)/(He)=5-20%. The internal pressure is 0.8 Torr, the rf frequency is 13.56MHz, and the power density is 30-100mW/cm<2>. By annealing the a-Si film formed under these conditions in a 600 deg.C N2 gas, the film can be transformed to poly-Si.

Description

[Detailed description of the invention] [Industrial application field] The present invention relates to a method for manufacturing a semiconductor thin film.

[Prior Art] Polycrystalline silicon (poly-3i) thin films have been actively researched because they can be applied to a variety of highly integrated semiconductor devices and large-area electronic devices, such as liquid crystal displays and image sensors. . Poly-3i thin film transistors (TPTs) with high carrier mobility have been actively researched because they can be applied to liquid crystal displays with built-in drivers and contact image sensors. In particular, amorphous silicon (a-3i) is produced using plasma chemical vapor deposition (PCVD), and then solid-phase growth annealed in an N2 gas atmosphere to obtain a large grain size p.

A method of creating a high carrier mobility TPT by creating 1y-3i is being actively researched.

On the other hand, doped poly-3i has been conventionally used as a gate electrode material for TPT. doped poly-
Amorphous silicon (a-5i) doped with high impurity temperature using PCVD method to reduce resistivity of 3i
), and by solid phase growth, a low resistance p
There are ways to form oly-3i.

[Problems to be Solved by the Invention] A-3i formed by the PCVD method has conventionally used pure hydrogen as a diluent gas. Since this a-3i contains a large amount of hydrogen, the time to release this hydrogen during annealing acts as the incubation time required for the generation of crystal nuclei, resulting in a problem that the solid phase growth time becomes long. is intended to solve the above problems, and its purpose is to produce large grain size or low resistance p
The objective is to create oly-3i by short-time annealing.

[Means for Solving the Problems] The method for manufacturing a semiconductor thin film of the present invention includes: (1) a method for depositing an amorphous semiconductor containing silicon as a main component on a substrate; It is characterized by using a mixed gas containing helium as a diluent gas.

(2) The method is characterized by including a step of annealing the amorphous semiconductor to cause solid phase growth.

[Example 1] Hereinafter, the method for manufacturing a semiconductor thin film of the present invention will be explained based on FIG. 3. In this example, Si is used as an example of a semiconductor. Applicable to Furthermore, the embodiments of the present invention include thin film transistors (TP).
T) will be taken as an example, but the application is not limited to TPT, and can of course be similarly applied to integrated circuit elements (IC1LSI) formed on crystalline silicon wafers.

First, about 1000 to 1500 amorphous or polycrystalline Si thin films are formed on a quartz substrate 300 by PCVD or low pressure chemical vapor deposition (LPGVD). The substrate is not limited to quartz substrate, but also low melting point glass substrate, MgO-A
After etching this Si thin film, which may be a crystalline insulating substrate such as l2O3, CaF2, BP, etc., into the pattern of the channel region 301 of the TFT, the grain size is increased by means such as solid phase epitaxy mirror annealing (see Fig. 3). a)) Solid phase growth may be performed before patterning.

In this example, poly-3i with a large grain size of several μm was formed by forming a-3i film by the PCVD method, and solid-phase growth annealing.
The process of creating a will be described as an example. Film forming gas is SiH4 and H
A gas mixed with e gas at a ratio of [SiH4]/[He] = 5 to 20% is used. Desirably, it is about 18%, the substrate temperature is 150 to 250°C, preferably about 180°C, and the internal pressure is 0.8 Torr. rf frequency is 13.5
6MHz, power density 30-100mW/
Cm2. p.

The wer density is preferably 63 mW/cm', and the a-3i film formed under these conditions is annealed in N2 gas at 600°C to transform into poly-3i. Here, in order to clarify the effect of the He diluent gas, a comparison will be made between an a-8i film formed using H2 gas as the diluent gas and a case of solid phase growth in the same manner. Si in case of H2 gas
The dilution rate of H gas is also the same as that of He gas. Figure 1 shows the solid phase growth annealing time dependence of the crystallization rate of a-3i determined by Raman scattering method.

The annealing temperature is 600°C. In Figure 1, the solid line is the crystallization rate change curve when He dilution gas is used, and the broken Ml to H2
This is the case when diluting gas is used. As is clear from FIG. 1, when He dilution gas is used, the transition to pOly-3i occurs in a shorter time than when H2 dilution gas is used.

Next, by thermal oxidation or sputtering, a gate insulating film of 5i02302 is deposited on the Si thin film at a thickness of about 300 to 1500 Å.
Form a film. A doped a-3i thin film 303 is formed on this SiO2 thin film by about 2000 to 7000 people (Fig. 3(b)
)). In the PCVD method, the doping concentration can be relatively freely set by changing the flow rate ratio between the doping gas and the SiH gas. Therefore, there is an advantage that high-temperature layer doping with impurities or atoms of several percent or more can be easily performed.

Here again, the PCVD method will be used to form the a-8i thin film 303 as an example. A mixed gas of SiHa and a doping gas diluted with He gas was used as the film forming gas. The doping gas is B2 when forming a p-type Si thin film.
H6 gas was used, and PH3 gas was used when forming an n-type Si thin film. The doping gas concentration for He dilution is B 2 H
6. PH3 is both in the range of 0.1 to 1%, preferably 0.5%. The substrate temperature is 150 to 250°C, particularly preferably around 180°C. The internal pressure is 0.8 Torr. RF frequency is 13°56MHz, power density is 30~100
mW/Cm2. Power density is 63 mW
/ cm m2 is preferable, SiH, and PH3, B2H6
The mixing ratio with gas is the gas flow rate ratio, [B2H6] / [8iH4] ≧ 0.1% [PH3]
/[3iH4]≧0. In the range of 1%・B2H6(
In the case of PH3 (n type), it is particularly desirable to have a force of about 5%, and in the case of PH3 (n type), about 0.5%, and the gas flow rate ratio is 0.1%.
If it is less than the solid solubility limit of B and P in Si, the effect of reducing the resistivity after activation annealing, which will be described later, will be small, and the doped po
This is because there is no difference in resistivity from ly-3i. In particular, in the case of B doping, the effect is great when the film is formed at a gas concentration ratio above the solid solubility limit.The creation of the a-3i film 303 is not limited to the PCVD method, but rather using a mixed gas of Si2H6 and B2H6/He on the substrate. An LPCVD method in which thermal decomposition is performed at a temperature of about 450° C. may also be used.

After this, solid phase growth (activation) annealing is performed to dope the a
-Transfer Si to doped poxy-Si304 (
Figure 3 (C)). Annealing conditions vary greatly depending on the dopant temperature of the doped A-8i thin film and dopant type (n, p), but -550 to 1000°C for boat fishing.
Anneal for several hours at a temperature in the range of . However, when using a low melting point glass substrate, the annealing temperature is limited to 600° C. or less.

Again, in order to clarify the dilution effect of He gas, −
As an example, a comparison will be made with a case where the doping gas B2H6 gas is diluted with N2 gas. The dilution temperature for the dopant dilution gas is as follows for both He and N2 gas:
[B 2H6] / [He Koni [B2H6] /
[H-2] = 0.2%. Figure 1 shows poly-3
Figure 3 shows the solid phase growth annealing time dependence of the resistivity of i. The annealing temperature is 600°C.

The temperature of the dopant relative to Si is determined by the gas flow rate ratio [B2H6
] / [S i H4 122%. In FIG. 1, the solid line shows the case when a He diluted doping gas is used, and the broken line shows the case when a N2 diluted doping gas is used. 1st
As is clear from the figure, when He dilution gas is used, N2
Low resistance poly in a shorter time than using diluent gas
It can be seen that -8i is obtained. This is due to the following reasons. When N2 dilution gas is used, the amount of hydrogen in a-3i is larger than when He dilution gas is used, so N2 is desorbed from the a-3i film at the initial stage of annealing and the concentration drops below a certain level. It takes time to become. Since solid phase growth does not start unless H2 in the a-3i film falls below a certain level, N in the a-3i film is
2 By lowering the irrigation level, the annealing time required to start solid phase growth can be shortened.

The annealing method itself involves segregation of dopants at grain boundaries, etc.
Any method may be used as long as it has a heating rate and temperature that does not cause abnormal expansion, and a cooling method that prevents the formation of a surface oxide film.

Regarding the annealing time, it is desirable that the annealing time is long enough to saturate the activation rate of the dopant, especially for polys doped with 2% or more dopant at high temperature.
For -3i, step annealing that gradually moves from low temperature to high temperature annealing is better.The reason for performing such step annealing is that if the heating rate is fast or the initial annealing temperature is high, dopants will segregate at grain boundaries. This is to prevent the resistivity from becoming higher than that of low-temperature doped poly-3i. In order to obtain poly-3i with low resistance, it is desirable that the initial annealing is performed at a relatively low temperature of 550 to 620 ° C. for 2 hours or more to make the average grain size of poly-3i large to 1 μm or more. This is because when the crystal grain size is small, the length of the crystal grain boundaries included per unit volume becomes long, and when impurities segregate at the grain boundaries, this causes a significant increase in resistivity. - Microscopically, amorphous regions remain at the grain boundaries of a poly-3i thin film annealed by solid phase growth at a maximum temperature of less than 900°C during annealing. The amorphous region at the grain boundary cannot be completely transformed into a crystalline region even if the activation annealing time is increased.

Therefore, in the case of n-type samples, N2
It is desirable to carry out the annealing at a temperature of 900°C or higher for 30 minutes or more, which transforms the amorphous phase into a crystalline phase and further reduces the volume of the amorphous phase while keeping the grain size large, resulting in further resistance. This is because the rate can be lowered.

Further, this short-time annealing process is not limited to N2 annealing, but may be replaced by a rapid thermal annealing method using a halogen lamp or the like. When the dopant is boron, the N2 annealing temperature is less than 1000°C. N2
When annealing is performed at 1000°C or higher, 8M in silicon
This is because the particles segregate in the crystal grain boundaries or in the quartz substrate, and the resistivity increases instead.

After this, the doped poly-8i is patterned to form the gate electrode "3"05.
The solid phase growth may be performed after patterning the gate electrode. Next, ion implantation is performed with P+ ions in the case of n-channel TPT and P+ ions in the case of p-channel TPT using the gate electrode as a mask, and the source region 30
6 and a drain region 307 are formed. After this source
Thermal annealing is performed at 600 to 900''C for the purpose of activating the drain (FIG. 3(d)).

Next, an interlayer insulating film of S is deposited on top of this by low pressure CVD.
i O2 film 308 is deposited by about 8,000 people (see Figure 3 (
e)) The interlayer insulating film may be a silicon nitride film, etc. At this stage, hydrogen is introduced into the channel silicon layer by a method such as a hydrogen plasma method, a hydrogen ion implantation method, or a hydrogen diffusion method from a plasma nitride film. Then, the gate insulating film/Si
This has the effect of terminating dangling bonds existing at interfaces, grain boundaries, etc., and reducing defect level density. Such a hydrogenation step may be performed before laminating the glabellar insulating film.

Finally, source and -drain contact holes are opened and a metal film (AI, etc.) for wiring material is deposited by sputtering at approximately 800 OA, and a source electrode 309 and a drain electrode 310 are deposited and patterned to complete the TPT. (Figure 3(f))
.

[Effects of the Invention] According to the method for manufacturing a semiconductor thin film of the present invention, doped poly-3i with low resistance can be formed in a shorter time than in the conventional solid-phase growth method from a-3i using hydrogen dilution gas. can do. Therefore, the throughput during mass production of large-area electronic devices using TPT or the like can be greatly increased.

For this reason, large-area LCD panels, close-contact image sensors,
It is effective when applied to TPT-driven liquid crystal shutter arrays, TPT-driven thermal heads, etc. In addition to TPT applied products, 3D SO elements or SRA
It is applicable to all semiconductor devices such as highly integrated semiconductor elements such as M and bipolar transistors.

[Brief explanation of drawings]

FIG. 1 is a diagram showing changes in the crystallization rate of a-3i with respect to annealing time. Figure 2 shows doped poly-8i versus annealing time.
A diagram showing changes in resistivity of. FIG. 3 is a diagram showing the manufacturing process of TPT. 101, a-8i film formed using hydrogen dilution gas
Crystallization rate change curve. 102,...Crystallization rate change curve of a-3i formed into a film using helium gas. 201, poly film formed using hydrogen dilution gas
-3i resistivity change curve. 202, p deposited using helium dilution gas. 1y-3i resistivity change curve. 300, quartz substrate. 301,,,channel region. 302,..., gate oxide film. 303,,,doped a-3i. 304, doped poly-3i. 305,,,gate electrode. 306, source area. 307,, drain region. 308, interlayer insulating film. 309, source electrode. 310, Drain electrode. Applicant: Seiko Epson Co., Ltd. Annie-j1411 (hr 5!, ) During annealing-
(hrm,)

Claims (2)

[Claims] (1) A method for depositing an amorphous semiconductor mainly composed of silicon on a substrate, characterized in that a mixed gas containing helium as a diluent gas is used as a film forming gas for the amorphous semiconductor. manufacturing method. 2. The method of manufacturing a semiconductor device according to claim 1, further comprising the step of: (2) annealing the amorphous semiconductor to cause solid phase growth.