JPH04286370A - Thin film semiconductor device - Google Patents

Abstract

PURPOSE:To form a silicon thin film excellent in crystallinity making the most of the merits of a solid growth method so as to obtain a thin film transistor small in OFF-state current by a method wherein a semiconductor thin film whose fluorine content is smaller than a specific value is provided so as to serve as an active region. CONSTITUTION:An amorphous Si film 1-2 is deposited on a quartz substrate 1-1 through a plasma CVD device. A chamber is cleaned with Freon before the amorphous Si film 1-2 is deposited, and the amorphous Si film 1-2 is thermally treated to discharge hydrogen from it. Then, the amorphous Si film 1-2 is made to grow in solid phase. At this point, an amorphous Si film whose fluorine content is smaller than 5X10<17>cm<-3> is annealed at a temperature of 600 deg.C for 16 hours into a silicon thin film 1-3 whose grain diameter is over 2mum. In result, an excellent thin film transistor very small in OFF-state current can be realized.

Description

[Detailed description of the invention]

0001

[Industrial Application Field] The present invention forms a semiconductor thin film with excellent crystallinity on an insulating amorphous material such as a quartz substrate or a glass substrate, and uses the semiconductor thin film as an active region to achieve excellent properties. The present invention relates to a method for manufacturing a thin film semiconductor device having the following.

0002

[Prior Art] A method for forming a thin polycrystalline silicon film or a single crystal silicon thin film with large crystal grains with uniform crystal orientation on an amorphous insulating substrate or an amorphous insulating film is as follows.
SOI (Silicon On Insulator)
r) known as technology. {SOI structure formation technology,
Industrial books}. Broadly classified, there are recrystallization methods, epitaxial methods, insulating layer embedding methods, and bonding methods. Recrystallization methods include a method in which silicon is melted and recrystallized by laser annealing or electron beam annealing, and a solid phase growth method in which silicon is grown in a solid phase without raising the temperature to a melting temperature. It is classified into two types. The solid phase growth method is superior in that it can be recrystallized at a relatively low temperature. 55
It has also been reported that crystal grains in silicon thin films grew despite low-temperature heat treatment at 0°C. {IEEE
Electron Device Letter
s, vol. EDL-8, No. 8, p361, Aug
ust 1987}.

[0003] A thin film transistor manufactured using a silicon thin film whose grain size is increased by solid-phase growth of an amorphous silicon thin film (a-Si) deposited by plasma CVD has an extremely large on-state current. {Japanese
Journal of Applied Ph.
ics Vol. 29, No. 12, p. L23
80, 1990}

0004

However, an a-Si film formed by plasma CVD may contain a large amount of fluorine (F) as an impurity. This is because if the a-Si film is deposited after cleaning the plasma CVD chamber with Freon (CF4) gas plasma, the fluorine remaining in the chamber will be incorporated into the a-Si film. . Since fluorine has a large bonding energy with silicon, fluorine remains in the Si film during annealing at about 500 to 700°C. Therefore, a Si film containing a large amount of fluorine has a large number of defect levels. A thin film transistor made using such a Si film has a low on-state current and a high off-state current. The inventor conducted an experiment and found that 2x fluorine
The off-state current of an Nch thin film transistor made by solid-phase growth of an a-Si film containing 1018 cm-3 is 200 to 4
It was 00pA. This is a very large value, and may cause display unevenness or an increase in current consumption when a liquid crystal panel is manufactured, for example. In addition, the amount of fluorine is S
It was investigated by IMS analysis. The background level at this time was 3 x 1017 cm-3.

[0005] The present invention is directed to plasma CV as described above.
Impurities that are a problem when solid-phase growing a Da-Si film,
In particular, it is an object of the present invention to provide a thin film semiconductor device that prevents fluorine contamination and maximizes the advantages of solid phase growth, and a method for manufacturing the same.

[0006]

[Means for Solving the Problems] The present invention is characterized in that a semiconductor thin film having a fluorine content of 5×10 17 cm −3 or less is provided as an active region.

[0007]

EXAMPLES (Example 1) Example 1 will be explained along the steps of manufacturing a thin film transistor using a fluorine-poor silicon thin film according to the present invention.

A non-single crystal semiconductor thin film is formed on an insulating amorphous material. As the insulating amorphous material, a quartz substrate, a glass substrate, a nitride film, a SiO2 film, or the like is used. When using a quartz substrate, the process temperature is 1200℃.
It is permissible up to about ℃, but when using a glass substrate,
Limited to low temperature processes below 600°C. The present invention
An example will be described in which a quartz substrate is used and a Si thin film is used as the non-single crystal semiconductor thin film. plasma CV
A quartz substrate 1-1 is prepared using D apparatus as shown in FIG. 1(a).
On top, a mixed gas of SiH4 and H2 is applied at 13.56MHz.
The amorphous Si film 1- is decomposed by high-frequency glow discharge.
Deposit 2. The SiH4 partial pressure of the mixed gas is 10~
20%, and the internal pressure in the depot is about 0.5 to 1.5 torr. The substrate temperature is suitably 250°C or less, about 180°C. The amount of bound hydrogen determined from infrared absorption measurement was approximately 8.
atomic%. The chamber before the deposition of the amorphous Si film 1-2 was cleaned with Freon, and the amorphous Si film subsequently deposited contained 2.times.10@18 cm@-3 of fluorine. Therefore, in the present invention, after the Freon cleaning, dummy deposition is performed, and then actual deposition is performed. Alternatively, Freon cleaning may be abolished and the chamber may be cleaned using another method such as bead treatment.

[0009] Subsequently, the amorphous Si film was heated at 400°C to 5°C.
Heat treatment is performed at 00°C to release hydrogen. This step aims to prevent explosive desorption of hydrogen.

Next, the amorphous thin film 1-2 is grown in a solid phase. As a solid phase growth method, furnace annealing using a quartz tube is convenient. As the annealing atmosphere, nitrogen gas, hydrogen gas, argon gas, helium gas, etc. are used. 1×10
Annealing may be performed in a high vacuum atmosphere of −6 to 1×10 −10 Torr. Solid phase growth annealing temperature is 500℃
~700°C. In such low-temperature annealing, only crystal grains having crystal orientations with low activation energy for crystal growth grow selectively, and moreover, they grow slowly and to a large size. In the inventor's experiments, the fluorine content was 5 x 1017c.
An amorphous silicon film of less than m-3 is annealed at a temperature of 600
A silicon thin film with a large grain size of 2 μm or more has been obtained by solid phase growth at 16 hours at a temperature of 16 hours. Figure 1
In (b), 1-3 indicates a solid-phase grown silicon thin film.

Next, the solid-phase grown silicon thin film is patterned into an island shape as shown in FIG. 1(c) by photolithography.

Next, as shown in FIG. 1(d), a gate oxide film 1-4 is formed. The gate oxide film can be formed by LPCVD, photo-excited CVD, plasma CVD, ECR plasma CVD, high vacuum evaporation, plasma oxidation, or high pressure oxidation at 500°C. There are the following low temperature methods. The gate oxide film formed by the low-temperature method becomes an excellent film that is denser and has fewer interface states by heat treatment. When using a quartz substrate as the amorphous insulating substrate 1-1, a thermal oxidation method can be used. The thermal oxidation method includes d
There are ry oxidation method and wet oxidation method, but the oxidation temperature is 10
The dry oxidation method is more suitable because the film quality is excellent, although the temperature is higher than 00°C.

After forming the oxide film, boron ions may be implanted into the channel. This is intended to prevent the threshold voltage of the Nch thin film transistor from shifting to the negative side. When the deposited thickness of the amorphous silicon film is about 500 to 1500 Å, the boron dose is suitably about 1×10 12 to 5×10 12 cm −2 .

When the thickness of the amorphous silicon film is as thin as 500 Å or less, the amount of boron is reduced, and as a guideline, it is 1×10 12 cm −2 or less. Further, when the film thickness is 1500 Å or more, the boron dose amount is increased, and as a guideline, it is 5×10 12 cm −2 or more.

Next, as shown in FIG. 1(e), a gate electrode 1-5 is formed. As the gate electrode material, a polycrystalline silicon thin film, molybdenum silicide, a metal film such as aluminum or chromium, or a transparent conductive film such as ITO or SnO2 can be used. Film forming methods include CVD method,
Although there are methods such as a sputtering method, a vacuum evaporation method, and a plasma CVD method, a detailed explanation thereof will be omitted here.

Next, as shown in FIG. 2(a), the game
Impurity ions are implanted using the gate electrode 1-5 as a mask to form the source region 1-6 and drain region 1-7 in a self-aligned manner.
form. When manufacturing an Nch transistor, P+ or As+ is used as the impurity, and Pc
When manufacturing an h transistor, B+ or the like is used. In addition to ion implantation, laser
There are methods such as doping method and plasma doping method. The arrows 1-8 represent impurity ion beams. When a quartz substrate is used as the insulating amorphous material 1-1, a thermal diffusion method can be used. The impurity concentration is approximately 1×10 15 to 1×10 20 cm −3 .

Subsequently, as shown in FIG. 2(b), interlayer insulating films 1-9 are laminated. The interlayer insulating film material includes:
An oxide film or nitride film is used. The film thickness may be any thickness as long as the insulation is good, but it is usually from several thousand Å to several μm. A simple method for forming the nitride film is the LPCVD method or the plasma CVD method. The reaction includes
A mixed gas of ammonia gas (NH3), silane gas, and nitrogen gas, or a mixed gas of silane gas and nitrogen gas, etc. is used.

Subsequently, activation annealing is performed for the purpose of densifying the interlayer insulating film, activating the source region and drain region, and restoring crystallinity. The activation annealing may be performed at 1000° C. for about 30 minutes in a N2 gas atmosphere. If you want to further improve the crystallinity and reduce the off-state current of the thin film transistor, the activation annealing should be performed at 900°C.
It is effective to lower the temperature to about .degree. C. and increase the annealing time to about 1 to 10 hours. Or 500 to get started
A two-step activation annealing method in which the crystallinity is sufficiently recovered by annealing at ~700°C for about 1 to 20 hours and then activated at a high temperature of 900 to 1000°C is also effective. In addition, RTA using infrared lamps and halogen lamps
(Rapid Thermal Annealin
g) Laws are also effective. Furthermore, a laser activation method using a laser beam or the like can be used.

Next, when hydrogen ions are introduced by a method such as a hydrogen plasma method, a hydrogen ion implantation method, or a hydrogen diffusion method from a plasma nitride film, dangling bonds existing at the gate oxide film interface, etc. defects are inactivated. Such a hydrogenation process is applied to the interlayer insulating film 1-9.
This may be done before laminating the layers. Alternatively, the hydrogenation step may be performed after forming a source electrode and a drain electrode, which will be described later. Next, as shown in FIG. 2(c), contact holes are formed in the interlayer insulating film 1-9 and the gate insulating film 1-4, contact electrodes are formed, and source electrodes 1-10 and This is referred to as a drain electrode 1-11. The source electrode and drain electrode are formed of a metal material such as aluminum or chromium. In this way, a thin film transistor is formed.

[0020]

As explained above, an amorphous Si film formed by plasma CVD contains several tens of percent hydrogen in most cases. From the results of thin film transistor characteristic analysis, SIMS analysis, etc., it has been found that impurities contained in the amorphous Si film, particularly fluorine, inhibit solid phase growth.

In the present invention, the amount of fluorine contained is 5×1
Since an amorphous silicon thin film with a thickness of 0.017 cm -3 or less is grown in a solid phase, a silicon thin film with few defect levels can be obtained. As a result, we were able to realize an excellent thin film transistor with extremely low off-state current. The off-state current of a thin film transistor produced by solid-phase growth of an amorphous silicon thin film containing about 1×10 18 cm −3 without controlling fluorine as in the conventional method is extremely large. FIG. 3 shows the results of experiments conducted by the inventor to explain the effects of the present invention. FIG. 3 is a characteristic diagram of an Nch thin film transistor. The horizontal axis is the game
The vertical axis shows the drain current. The broken line shows the characteristics of a conventional thin film transistor made by solid-phase growth of an amorphous silicon thin film containing 2 x 1018 cm-3 of fluorine, and the solid line shows the characteristics of a conventional thin film transistor made by solid-phase growth of an amorphous silicon thin film containing 2 x 1018 cm-3 of fluorine.
It shows the characteristics of a thin film transistor according to the present invention produced by solid-phase growth of the following amorphous silicon thin film. Note that the measurement conditions were the same. According to the present invention, the off-state current is 1
It is clear that the reduction is more than an order of magnitude.

[0022] Since the amorphous silicon thin film containing very few impurities is grown in solid phase, even if the annealing temperature for solid phase growth is as low as 600°C, long annealing is not required for crystal nucleation, and latent growth is possible. It is possible to significantly shorten the time. If the annealing temperature is low, the nucleation density will be low, and a Si film with a very large crystal grain size will finally be obtained. Therefore, the present invention not only significantly shortens the time required for solid phase growth, but also has an extremely large effect on forming a Si film with a large grain size.

[0023] Since a large-grain Si film can be obtained in a very short time of 1 to 2 hours, it is very effective in shortening process time and improving throughput when manufacturing thin film transistors, and in turn reducing costs. Inventions have extremely large effects.

Since it has become possible to produce a silicon thin film with excellent crystallinity on an amorphous insulating substrate, this will greatly contribute to the development of SOI technology. The number of photo processes does not increase at all. Since it can be manufactured using a low-temperature process of 600° C. or lower, it is possible to use a glass substrate that is inexpensive and has a low heat-resistant temperature. Even though an excellent silicon thin film can be obtained, the cost does not increase.

When a thin film transistor is fabricated using the large-grain polycrystalline silicon thin film obtained by the present invention, excellent characteristics can be obtained. Compared to the conventional art, the ON current of the thin film transistor increases and the OFF current decreases. In addition, the threshold voltage is also reduced, and transistor characteristics are greatly improved. The imbalance in characteristics between the N channel and the P channel is also improved.

Since it is possible to fabricate a thin film transistor with excellent characteristics on an amorphous insulating substrate, the driver
Sufficient high-speed operation can also be achieved when applied to an active matrix substrate in which circuits are integrated on the same substrate. Furthermore, it has great effects on reducing power supply voltage, reducing current consumption, and improving reliability. In addition, since it is possible to manufacture by a low-temperature process at 600° C. or lower, this is highly effective in reducing the cost and increasing the area of active matrix substrates.

When the present invention is applied to a contact image sensor in which a photoelectric conversion element and its scanning circuit are integrated on the same chip, it is possible to increase the reading speed, increase the resolution, and further increase the gradation. produces a very large effect. Once high resolution is achieved, close-contact images for color reading will become available.
Application to digital sensors is also facilitated. Of course, this has great effects in reducing power supply voltage, reducing current consumption, and improving reliability. Furthermore, since it can be manufactured by a low-temperature process, it is possible to make the contact type image sensor chip long, and a reading device for a large facsimile such as A4 size or A3 size can be realized with a single chip. Therefore, the complicated and unreliable technique of splicing two sensor chips can be avoided, and the mounting yield can also be improved.

[0028] Not only quartz substrates and glass substrates, but also sapphire substrates (Al2O3) or MgO/Al2O3
, BP, CaF2, or the like can also be used.

Although the explanation has been given above using a thin film transistor as an example, devices using thin films such as bipolar transistors or heterojunction bipolar transistors can also be explained.
The present invention can be applied. Further, the present invention can also be applied to elements using SOI technology, such as three-dimensional devices.

Although the present invention has been explained by taking the solid phase growth method as an example, the present invention is applicable not only to the solid phase growth method but also to LPC.
It can also be applied to the case where a thin film semiconductor device is created using a poly-Si thin film formed by the VD method or other methods.

[Brief explanation of the drawing]

FIGS. 1A to 1E are process cross-sectional views of a thin film transistor showing an embodiment of the present invention.

FIGS. 2(a) to 2(c) are process cross-sectional views of a thin film transistor showing an example of the present invention.

FIG. 3 is a characteristic diagram of a thin film transistor showing the effects of the present invention.

[Explanation of symbols]

1-2 Amorphous silicon thin film containing fluorine content of 5 x 1017 cm-3 or less

Claims (1)

[Claims] [Claim 1] Fluorine content is 5 x 1017 cm-3
A thin film semiconductor device comprising the following semiconductor thin film as an active region.