JPH0736525B2 - Output buffer circuit and driving method thereof - Google Patents

Description

Description: BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an output buffer circuit of a semiconductor integrated circuit, and more particularly to an output buffer circuit for converting a digitally input voltage value into an analog signal to drive a large capacity load.

[Conventional technology]

Conventionally, this type of output buffer circuit has a circuit configuration as shown in FIG. In the figure, 20 is a D for D / A converting the digital amplitude value input from the data input group 12.
An / A converter, 1 is an output buffer for driving the large-capacity load 10 with the analog voltage D / A converted by the D / A converter 20, and 2 is a transistor for a constant current source in the output stage of the output buffer 1, The current value is determined by the constant current source reference circuit 8 for current.

The current value determined by the constant current source reference circuit 8 for large current is always given as a constant value that can sufficiently drive the large capacity load 10. Therefore, the output waveform of the output buffer circuit shown in FIG. 4 is, for example, as shown in FIG. 5, the slew rate when the output voltage value a changes to b and the slew rate when the output voltage value b changes to c. The rate is always the same.

[Problems to be Solved by the Invention]

The conventional output buffer circuit described above has a value that can drive the large-capacity load 10 with the maximum output amplitude value of the output buffer circuit for the current flowing through the constant current source transistor 2 shown in FIG. 4 in order to drive the large capacity. Therefore, it is necessary to always give a constant value. However, when the output voltage value of the output waveform of the output buffer circuit shown in FIG. 5 changes from a to b, the amount of voltage change is smaller than when it changes from the output voltage value d to e. Compared to the latter case, the current flowing in the transistor is a large capacity load if it is applied for a short period of time.
Can drive 10. Therefore, in the conventional output buffer circuit, a large amount of current unnecessary for driving a large-capacity load flows, so that the power consumption of the output buffer circuit becomes higher than necessary. In particular, when the conventional output buffer circuit is applied to the case where the driving voltage is high and the driver has multiple outputs, there is a drawback that the power consumption becomes very large.

Therefore, an object of the present invention is to provide an output buffer circuit in which unnecessary current is prevented from flowing when driving a large capacity load and the power consumption of the output buffer circuit is small.

[Means for Solving the Problems]

The output buffer circuit of the present invention is a decoder for pulse width modulation, which receives a digital signal obtained by digitizing an analog voltage and generates a pulse having a pulse width proportional to the magnitude of the amplitude of the digital signal, and its output pulse reference voltage. A ramp voltage generating circuit, a sample hold switch for controlling the sampling time of the output voltage of the ramp voltage generating circuit by the pulse width of the output signal of the pulse width modulation decoder, and an output voltage of the ramp voltage generating circuit. A sample-hold capacitor for sample-holding via the sample-hold switch, and an output buffer having the sample-hold capacitor as an input,
A constant current source transistor that determines the load driving capability of the output stage of the output buffer, and the output stage of the output buffer is driven by a current that can drive the load connected to the output of the output buffer with the maximum amplitude of the output buffer. A high-current constant-current source reference circuit for applying a reference voltage to the constant-current source transistor, and the constant-current source for driving the output stage of the output buffer with a minimum current that can maintain the output voltage of the output buffer. A small current constant current source reference circuit for giving a reference voltage to a transistor and one of the large current constant current source reference circuit and the small current constant current source reference circuit which is switched by the output signal of the pulse width modulation decoder. A constant current source reference switch connected to the constant current source transistor In the phase circuit, the constant current source reference switch outputs the pulse width modulation decoder during a period in which the sample hold switch is closed by the output signal of the pulse width modulation decoder to charge the sample hold capacitor. The high-current constant-current source reference circuit is selected by a signal, and the sample-hold switch is opened by the output signal of the pulse-width modulation decoder and holds the sample-hold capacitor while holding the sample-hold capacitor. The small current constant current source reference circuit is selected by the output signal.

Further, the output buffer circuit driving method of the present invention comprises a pulse width modulation decoder for inputting a digital signal obtained by digitizing an analog voltage and generating a pulse having a pulse width proportional to the magnitude of the amplitude of the digital signal, A ramp voltage generating circuit that generates the output pulse reference voltage, a sample hold switch that controls the sampling time of the output voltage of the ramp voltage generating circuit by the pulse width of the output signal of the pulse width modulation decoder, and the ramp voltage generating circuit. A sample and hold capacitor that samples and holds the output voltage of the circuit through the sample and hold switch, an output buffer that receives the sample and hold capacitor, and a transistor for a constant current source that determines the load driving capability of the output stage of the output buffer. And the output of the output buffer A constant current source reference circuit for supplying a reference voltage to the constant current source transistor so that the output stage of the output buffer is driven by a current capable of driving the load to be driven with the maximum amplitude of the output buffer; Switching between a small current constant current source reference circuit that gives a reference voltage to the constant current source transistor so that the output stage of the output buffer is driven with a minimum current that can maintain the output voltage, and an output signal of the pulse width modulation decoder And a constant current source reference switch connecting either one of the large current constant current source reference circuit and the small current constant current source reference circuit to the constant current source transistor. At the constant current source reference switch, the sample hold switch The sample-hold switch is selected by the output signal of the pulse-width modulation decoder during the period in which the output signal of the pulse-width modulation decoder closes to charge the sample-hold capacitor. Selects the small current constant current source reference circuit according to the output signal of the pulse width modulation decoder during a period in which the pulse width modulation decoder is opened by the output signal of the pulse width modulation decoder to hold the sample hold capacitor. I am trying.

〔Example〕

 Next, the present invention will be described with reference to the drawings.

FIG. 1 is a circuit configuration diagram of an output buffer circuit of a first embodiment of the present invention, and FIG. 2 is a waveform diagram of voltages V1 to V4 at respective points in FIG.

The output buffer circuit of the first embodiment of the present invention includes a ramp voltage generation circuit 5 for generating a reference voltage of an output voltage, a pulse width modulation decoder 7 for pulse width modulation of data input from a data input terminal group. , A D / A converter composed of a sample hold capacitor 3 for sampling and holding the voltage V1 of the ramp voltage generating circuit 5 by the pulse width output voltage V2 of the pulse width modulation decoder 7, and a D / A converter, and its D / A converter. An output buffer 1 that drives the analog voltage V3 of the A converter to a large capacity load 10,
A constant current source reference circuit 8 for large current, a constant current source reference circuit 9 for small current, and a constant current source reference circuit 8 for large current that determine the value of the current flowing through the transistor 2 for constant current source of the output buffer 1. Alternatively, the constant current source reference circuit 9 for small current is composed of a constant current source reference changeover switch 6 which is switched by the output of the pulse width modulation decoder 7.

When the reference voltage is generated by the ramp voltage generating circuit 5, the output voltage V2 of the pulse width modulation decoder 7 pulse width modulated by the data value input to the data input terminal group 12
The sample hold switch 4 is closed and the sample hold capacitor 3 is charged. Now, when the output voltage V2 of the pulse width modulation decoder 7 is OFF, the constant current reference changeover switch of the output buffer 1 is switched to the small current constant current source reference circuit 9, and the output voltage V2 of the pulse width modulation decoder 7 is turned ON. It is assumed that the constant current source reference circuit 8 for large current is sometimes used for switching.

During the period A (FIG. 2) during which the sample-hold capacitor 3 is charged, a current determined by the large-current constant-current source reference circuit 8 flows in the output buffer 1, and the sample-hold capacitor 3 holds the current. Period B (second
In the figure, a current determined by the small current constant current source reference circuit 9 flows. A constant current source reference circuit 8 for large current is set to a current capable of sufficiently driving a large capacity load with the maximum output amplitude. Further, in the constant current source reference circuit 9 for small current, a current that can maintain the output voltage is set.

By doing so, for example, when the output voltage changes from f to g in FIG. 2 or from g to h, a large current flows in the output buffer only during the period A. It can be driven with high current consumption.

FIG. 3 is a circuit configuration diagram of the second embodiment of the present invention. This embodiment shows an example in which the driver of the first embodiment has a multi-output configuration, and 601 to 60n are pulse width modulation. Decoder groups, 701 to 70n are latch groups, and 801 to 80n are shift register groups.

The data transferred by the shift registers 801 to 80n is held by the latches 701 to 70n for a certain period. The reference voltage of the ramp voltage generating circuit 5 is modulated with the pulse width of the output signal of the pulse width modulation decoders 601 to 60n according to the held data value, and the sample hold capacitor 201 is operated.
Charge ~ 20n. Further, similarly to the first embodiment, the large current constant current reference circuit 8 and the small current constant current circuit 9 are switched for each output according to the change of the output voltage to reduce the power consumption.

In this embodiment, the elements necessary for reducing the electric power in spite of the multiple outputs are only required by the two constant current reference circuits and the constant current reference changeover switch added to each output. There is an advantage. Also,
The power consumption can be reduced by the number of outputs, and a large reduction in power consumption can be achieved.

〔The invention's effect〕

As described above, according to the present invention, in an output buffer circuit that converts a digitally input voltage value into an analog value and drives a large capacity load, D / A conversion is performed by a ramp voltage generation circuit and pulse width modulation, and at the same time, pulse width modulation is performed. By switching the constant current source of the output buffer between the large current and the small current according to the period when the output voltage of the output buffer changes, the current consumption can be automatically controlled according to the output voltage. Therefore, there is an effect that the power consumption of the output buffer can be reduced.

[Brief description of drawings]

FIG. 1 is a circuit configuration diagram of an output buffer circuit according to a first embodiment of the present invention, FIG. 2 is a voltage waveform diagram of each portion of FIG. 1, and FIG.
FIG. 4 is a circuit configuration diagram of a second embodiment of the present invention, FIG. 4 is a circuit configuration diagram of a conventional output buffer circuit, and FIG. 5 is an output waveform diagram of a conventional output buffer circuit. V1 ... Output voltage waveform of ramp voltage generation circuit 5, V2 ... Output waveform of pulse width modulation decoder 7, V3 ... Voltage waveform of sample hold capacitor 3, V4 ... Voltage waveform of output terminal 14, V10 ... Output waveform, 1 ... Output buffer, 2 ...
… Transistor for constant current source, 3 …… Sample hold capacitor, 4 …… Sample hold capacitor, 5 ……
Lamp voltage generation circuit, 6 ... Constant current source reference selector switch, 7 ... Pulse width modulation decoder, 8 ... Large current constant current source reference circuit, 9 ... Small current constant current source reference circuit, 10 ... … Large capacity load, 11 …… Decoder reference clock pulse input terminal group, 12 …… Decoder input terminal group, 13 …… Pulse width modulation decoder output, 14 …… Output terminal, 15 …… Latch input, 16 …… Shift Transfer clock for register, 20 …… D / A converter, 101-10n …… Output buffer, 201-20n …… Sample hold capacitor,
301 to 30n …… Sample hold switch, 401 to 40n ……
Transistor for constant current source, 501 to 50n ... Constant current source reference switch, 601 to 60n ... Decoder for pulse width modulation, 701 to 70n ... Latch, 801 to 80n ... Shift register, 901 to 90n ... Output Terminal.

Claims (2)

[Claims] 1. A pulse width modulation decoder for inputting a digital signal obtained by digitizing an analog voltage and generating a pulse having a pulse width proportional to the magnitude of the amplitude of the digital signal, and an output pulse reference voltage thereof. A ramp voltage generation circuit, a sample hold switch for controlling the sampling time of the output voltage of the ramp voltage generation circuit by the pulse width of the output signal of the pulse width modulation decoder, and a sample hold of the output voltage of the ramp voltage generation circuit. A sample-hold capacitor that samples and holds via a switch, an output buffer that receives this sample-hold capacitor, a transistor for a constant current source that determines the load drive capability of the output stage of this output buffer, and an output of the output buffer. Connect the load connected to the output buffer With a large current constant current source reference circuit that gives a reference voltage to the constant current source transistor so that the output stage of the output buffer is driven with a current that can be driven with a large amplitude, and a minimum current that can maintain the output voltage of the output buffer. The small current constant current source reference circuit for giving a reference voltage to the constant current source transistor so that the output stage of the output buffer is driven, and the large current constant current source reference circuit switched by the output signal of the pulse width modulation decoder. And an output buffer circuit including a constant current source reference switch that connects one of the small current constant current source reference circuit to the constant current source transistor, wherein the constant current source reference switch is the sample. A hold switch operates according to the output signal of the pulse width modulation decoder. During the period in which the sample-hold capacitor is being charged, the high-current constant-current source reference circuit is selected by the output signal of the pulse-width modulation decoder, and the sample-hold switch outputs the pulse-width modulation decoder. An output buffer circuit, wherein the small current constant current source reference circuit is selected by the output signal of the pulse width modulation decoder during a period in which the signal is opened to hold the sample hold capacitor. 2. A pulse width modulation decoder for inputting a digital signal obtained by digitizing an analog voltage and generating a pulse having a pulse width proportional to the magnitude of the amplitude of the digital signal, and an output pulse reference voltage for the decoder. A ramp voltage generation circuit, a sample hold switch for controlling the sampling time of the output voltage of the ramp voltage generation circuit by the pulse width of the output signal of the pulse width modulation decoder, and a sample hold of the output voltage of the ramp voltage generation circuit. A sample-hold capacitor that samples and holds via a switch, an output buffer that receives this sample-hold capacitor, a transistor for a constant current source that determines the load drive capability of the output stage of this output buffer, and an output of the output buffer. Connect the load connected to the output buffer A large current constant current source reference circuit that gives a reference voltage to the constant current source transistor so that the output stage of the output buffer can be driven with a current that can be driven with a large amplitude, and a minimum current that can maintain the output voltage of the output buffer. And a small current constant current source reference circuit for applying a reference voltage to the constant current source transistor so that the output stage of the output buffer is driven, and the large current constant current source reference switched by the output signal of the pulse width modulation decoder. A constant current source reference switch that connects one of the circuit and the small current constant current source reference circuit to the constant current source transistor, wherein the constant current source reference switch However, the sample-hold switch is the output of the pulse width modulation decoder. The high-current constant-current source reference circuit is selected by the output signal of the pulse-width modulation decoder during the period in which the signal is closed to charge the sample-hold capacitor, and the sample-hold switch of the pulse-width modulation decoder is selected. A method of driving an output buffer circuit, characterized in that the small current constant current source reference circuit is selected by the output signal of the pulse width modulation decoder during a period in which the sample hold capacitor is held open by the output signal. .