JPS62274930A - Digital-analog converter - Google Patents

Abstract

PURPOSE:To attain a good linearity and to reduce a clock frequency by integrating a linear function signal having a level corresponding to the linear function of time by an integration command signal which is generated a prescribed number of times at the timing corresponding to the value indicated by an input digital signal. CONSTITUTION:A switch driver 5 outputs 2<8> pulses, which have a combination corresponding to input digital data out of individual pulses of a clock signal (b) supplied from the time of generation of a pulse (a), as a turn-on command signal. The output of a lamp voltage generating circuit 11 is supplied to the positive input terminal of an operational amplifier 10. The output voltage of the lamp voltage generating circuit 11 is 0V at the time of generation of the pulse (a) and is raised with a prescribed inclination after disappearance of the pulse (a). The pulse (a) is supplied to the control input terminal of a switch circuit 12. The switch circuit 12 is turned on by the pulse (a) to discharge the charged electric charge of a capacitor C2. The charging voltage of the capacitor C2 is held in a sampling and holding circuit 13 and becomes a D/A conversion output.

Description

[Detailed Description of the Invention] 3. Detailed Description of the Invention
(abbreviated as D/A converter).

As conventional D/A converters, ladder type/A] converters, integral type 0/A converters, etc. are known. The ladder mold/A:l inverter is constructed as shown in FIG. In FIG. 10, TN resistors Ra1, Ra
2, Ra3...RaN are connected in series with each other.

N resistors Rb+, Rb2, Rb3...Rb are connected to one end of the resistor Ra+ and each series connection point of the resistors Ra+ to RaN.
One end of each of N is connected. Resistance Rb+~RbN
At the other end of each of the transistors Q+, Q2, Q3.
...Each emitter of QN is connected. These transistors Q! The bases of ~QN are connected to each other. The bases of these transistors 01 to QN and the resistor RaN
A constant voltage E is applied between the other ends. In addition, a switch circuit S is connected to the collector of each of the transistors 01 to QN.
each of a-electric, Se2, Se2...SaN and resistance RC
A power supply Vcc is supplied through the terminal. switch circuit S
A signal corresponding to each bit of the input digital data of Np[~ is supplied to each control input terminal of at~SaN. When each of the switch circuits Sa+ to SaN is turned on, the resistors Rb1, Rb2, Rb3...RbNN
-1°, the currents i I , 2 i I , 4 i +...
・If the values of the resistors Rat to RaN and Rb1 to RbN are set so that each of Then, D/A conversion is performed.

In the ladder type/A converter as described above, the D/A converter is
△Conversion accuracy depends on the accuracy of each resistor, and in particular when relative accuracy, linearity, and differential linearity for each pitch 1~ are required, such as when used in audio equipment, the laser 1~
This has the disadvantage that rimming and the like are required, making manufacturing difficult.

Further, the integral type D/A converter is constructed as shown in FIG. In FIG. 11, input digital data is supplied to a digital comparator 1 and compared with output data of a counter 2. In FIG.

In the counter 2, the count value changes according to a clock of a predetermined frequency outputted from the clock generation circuit 3. When the output data of the counter 2 matches the input digital data, the digital comparator 1 outputs, for example, a high level match detection signal. This match detection signal is
It serves as a control input for switch circuit sb. A constant current source 11 is connected between one end of the switch circuit sb and ground.

A capacitor C1 is connected between the narrow end of the switch circuit sb and ground. The charging voltage of the capacitor C1 is applied to the 4 non-pull hold circuit 4 and held there. In such a configuration, if the switch circuit sb is assumed to be in an open state when a coincidence detection signal is generated, a charging current is supplied to the capacitor C1 for a time corresponding to the input digital data, and the charging voltage of the capacitor C1 becomes equal to the input digital data. The value corresponding to . The charged voltage of the capacitor C1 is held in the sample bold circuit 4 and becomes an output signal, which is subjected to D/Δ conversion.

In the integral type D/Δ] inverter as described above, linearity and differential linearity are good, but when the sampling frequency of input digital data is 44.1 KI'z and the number of bits is 16, the clock frequency is 2.89G+-
12, the operating frequency J: of logic operation circuits such as T T l-circuits becomes much higher, which has the disadvantage that they cannot be used in digital audio systems.

Therefore, in reality, 16-bit digital data is divided into 8 bits each (upper and lower), and an integral type D/D is applied to each of them.
A method is used in which a 16-bit D/A converter is constructed by converting into an analog value using an Al inverter, adding 28 times weight to the upper 8 bits of the analog value, and then adding both. However, D of such a configuration
/Δ converter, for example, the input digital data ``OOF F'' expressed in hexadecimal is ``0100''.
``If there is an error in the resistance for weighting when the input changes, a change corresponding to the input change will not appear in the output, and good differential linearity cannot be obtained.

Mitsuho An object of the present invention is to provide a D/A converter that has good linearity and can lower the clock frequency.

The D/Δ converter according to the present invention is configured to integrate a linear function signal having a level corresponding to a linear function of time using an integration command signal that is generated a predetermined number of times at a timing corresponding to a value represented by an input digital signal. DESCRIPTION OF THE PREFERRED EMBODIMENTS Hereinafter, embodiments of the present invention will be described in detail with reference to FIGS. 1 to 9.

In Figure 1, for example, the audio signal is
4.4.1 The 16-bit digital data obtained by sampling with a sampling frequency of )-1z is
It is supplied to the switch driver 5 together with the pulse a having a repetition frequency of KH2.

The switch driver 5 is supplied with the clock pulse b output from the clock generation circuit 6.

Note that the frequency of clock pulse b is approximately 22.6 MHz.
(44, IKHzx29>.

The switch driver 5 is configured to output, as an ON command signal, 28 pulses having a combination corresponding to the input digital data among the pulses of the clock pulse b supplied from the generation of the pulse a. The output of this switch driver 5 serves as a control input for a switch circuit 7.

The drain of an FET (field effect transistor) 9 in a lamp current generating circuit 8 is connected to one of the input and output terminals of the switch circuit 7 . Source and power supply of FET9
A resistor Rd is connected between VF6. Also, this F
The source of ET9 is connected to the negative input terminal of operational amplifier 10. The output of the ramp voltage generation circuit 11 is supplied to the positive input terminal of the operational amplifier 10. Further, the output of the operational amplifier 10 is supplied to the gate of the FET 9. For example, the lamp voltage generating circuit 11 outputs a voltage of Qv when pulse a is generated, and this output voltage becomes Qv when pulse a is generated.
After disappearing, it rises at a predetermined slope and overturns.

A capacitor C2 and a switch circuit 12 are connected in parallel between the other input/output terminal of the switch circuit 7 and ground. A pulse a is supplied to a control input terminal of the switch circuit 12. This pulse a turns on the switch circuit 12 and discharges the charge in the capacitor C2. The charging voltage of the capacitor C2 is held in the sample and hold circuit 13, and the D/A conversion ratio is detected.

In the above configuration, the FET 9 has <22
．． The output voltage of the lamp voltage generation circuit 11 changes so that the sawtooth signal current 0 with a period of 7 μs (1/44.1×10′) flows as the drain current.

Here, when the input digital data becomes equal to the data ``' o o o o'' expressed in hexadecimal notation, the pulse b that occurs first among the clock pulses b that are sequentially generated from the generation of the pulse a. It is assumed that each of the pulses from (1) to the 28th generated pulse b (28) is output from the switch driver 5. Then, the output pulse of the switch driver 5 turns on the switch circuit 7, and as shown in FIG. A current as shown by diagonal lines in (A) flows through the switch circuit 7. As a result, a charge as shown in the following equation is charged in the capacitor C2.

Here, ΔIo is the amount of change in current 1o with respect to a change in time for one clock, τd is the time width of clock pulse b, and ■oI is the initial value of current ■0.

Furthermore, when the input digital data becomes equal to the data ``0001'' expressed in hexadecimal notation, the pulse b (1 ) to the (28-1)th pulse b(28-1) and (28-1), respectively.
Assume that the +1)th generated pulse b(28+1> is output from the switch driver 5. Then, the output pulse of the switch driver 5 turns on the switch circuit 7, and the diagonal line in FIG. 3(B) turns on the switch circuit 7. A current as shown flows through the switch circuit 7. As a result, a charge as shown in the following equation is charged to the capacitor C2.

Furthermore, when the input digital data becomes equal to the data "'0002'" expressed in hexadecimal notation, the pulse b (1 ) to (28-2)th generated pulse b(28-2>), the 28th generated pulse b('28), and the (2"+1)th generated pulse b(28+1) are the switches. It is assumed that the signal is output from the driver 5.

Then, the switch circuit 7 is turned on by the output pulse of the switch driver 5, and a current as shown by diagonal lines in FIG. 3(C) flows through the switch circuit 7.

As a result, the capacitor C2 is charged with a charge as shown in the following equation.

Also, when the input digital data becomes equal to the data ``0100'' expressed in hexadecimal notation, the second pulse b(2) of the clock pulses b sequentially generated from the generation of the pulse a. 3 (D ) flows through the switch circuit 7 as shown by diagonal lines.As a result, the capacitor C2 is charged with a charge as shown in the following equation.

× ΔIo Each of the pulse b(2) generated at the second to the 28th pulse b(28) and the pulse b(28+2) generated at the (28+2)th time are output. Then, the switch circuit 7 is turned on by the output pulse of the switch driver 5, and a current as shown by diagonal lines in FIG. 3(E) flows through the switch circuit 7. As a result, the capacitor C2 is charged with a charge as shown in the following equation.

Furthermore, when the input digital data becomes equal to the data ``0200'' expressed in hexadecimal notation, the third pulse b(3) of the clock pulses b sequentially generated from the generation of the pulse a. From <28+2)
Each of the pulses up to the second generated pulse b (28+2) is output from the switch driver 5. Then, the switch circuit 7 is turned on by the output pulse of the switch driver 5, and a current as shown by diagonal lines in FIG. 3(F) flows through the switch circuit 7. As a result, the capacitor C2 is charged with a charge as shown in the following equation.

28 (22+(28+1)) −［□］ 2.

×ΔIoXτd+Io1×28×τd・ (6) Also,
Data in which input digital data is expressed in hexadecimal notation
F F F F ”, the 28th pulse b(2) and (28+2
The switch driver 5 outputs each pulse from the pulse b(2+2) generated at the )th time to the pulse b(29) generated at the 29th time. Then, the switch circuit 7 is turned on by the output pulse of the switch driver 5, and the third
A current as shown by diagonal lines in FIG. 3(G) flows through the switch circuit 7. As a result, the capacitor C2 is charged with a charge as shown in the following equation.

As described above, the electric charge corresponding to the input digital data is charged to the circuit "J-C2", and the voltage corresponding to the input digital data is supplied to the sample and hold circuit 13, and the voltage corresponding to the input digital data is supplied to the sample hold circuit 13.
/A conversion is performed.

FIG. 4 is a diagram showing a specific circuit example of the lamp voltage generation circuit 11. In the figure, pulse a is supplied to gate 1- of FET 14. The source of FET 14 is grounded. Further, a capacitor C3 is connected between the drain of the FET 14 and ground. A constant current source 1 is connected to the connection point between the drain of these FET14 and capacitor "J-03".
5 output current ■2 is supplied. These FET14
The signal derived from the connection point between the drain of the capacitor C3 and the capacitor C3 becomes the output of the lamp voltage generating circuit 11. In this configuration, the FET 14 is turned on by the pulse a, and the charge in the capacitor C3 is discharged. After this,
Due to the output current 2, the charging voltage of the battery C3 gradually increases, and a sawtooth wave signal is formed.

FIG. 5 is a diagram showing a specific circuit example of the switch circuit 7. As shown in FIG. In the figure, pulses output from the switch driver 5 are directly supplied to the gate of the FFT 16 and at the same time are supplied to the gate of the FET 18 via the inverter 17. The sources of the FETs 16 and 18 are connected to each other to form a differential pair. The source common connection point of these FETIs 6 and 18 serves as one input/output end. Further, the drain of the FET 18 is grounded. Also, FE
The drain of T16 is the other input/output terminal.

FIG. 6 is a diagram showing a specific circuit example of the switch driver 5. In the figure, the upper 8 bits of input digital data are supplied to a digital comparator 20 and compared with the output data of an 8-bit binary counter 21. The binary counter 21 is a T-type flip-flop 22
~29. A clock pulse b is supplied to the clock input terminal of the T-type flip-flop 22. Further, a pulse a is supplied to each reset input terminal of the T-type flip-flops 22 to 29. Upper 8 bits of input digital data and binary counter 2
When the output data of 1 and 1 match, the digital comparator 20 outputs a high level match detection signal. This coincidence detection signal serves as a set input to an RS flip-flop 30 consisting of NOR (NOR) gates G1 and G2.

On the other hand, each bit of the lower 8 digits of the input digital data is
Addition circuit 31 via each of inverters IV+ to IVs
The adder circuit 31 outputs data corresponding to the complement of the lower eight digits of the input digital data.

The output data of this adder circuit 31 is supplied to a digital comparator 32 and a 9-bit binary counter 33
is compared with the output data of The binary counter 33 is
It is composed of T-type flip-flops 70 and 34-42, and the output data of the binary counter 33 is formed by the Q output of each of these T-type flip-flops 3/I-42. In addition, T-type flip-flops 34 and 4
The Q output of 2 is directly supplied to the input terminal of AND gate G3, and the T-type flip 70 knob 35~
41 are supplied to the input terminal of AND gate G3 via each of inverters IV9 to TV+s. Further, a pulse a is supplied to each reset input terminal of the T-type flip 70 tabs 34 to 42.

The output of AND gate G3 is the RS flip-flop 30
is supplied to the input terminal of the NOR gate G2 as the reset input terminal of the NOR gate G2. The output of gate G2 as the Q output of RS flip-flop 30 is connected to AND gates G4 and G5.
is supplied to the input terminal of Clock pulse b is supplied to the other input terminal of AND gate G5. The output of this AND gate G5 is supplied to the clock input terminal of the T-type flip-flop 34 as a count pulse of the binary counter 33. Also, AND gate G
Two of the three input terminals of 4 are connected to a digital comparator 32 via a clock pulse b and an inverter IVI6.
, respectively, are supplied with matching detection signals. This AND
The output of gate G4 is the output of switch driver 5.

In the above configuration, when the input digital data is expressed as 'n1n2n3 n4' in hexadecimal notation, when the count value of the binary counter 21 becomes equal to the value corresponding to the upper 8 digits of the input digital data (n+X2' +nz > A coincidence detection signal is output from the digital comparator 20, and the RS flip-flop 30 is set.

Then, the clock pulse b starts to be output from the AND gate G4. At the same time, count pulses begin to be supplied to the binary counter 33. When the count value of the binary counter 33 reaches (28+1), a coincidence detection signal is output from the digital comparator 32, the RS flip-flop 30 is reset, and the output of pulses from the AND gate G4 is stopped. Furthermore, when the count value of the binary counter 33 reaches (28-(n3 Stop temporarily.

By the above-described operation, a switch drive pulse as shown in FIG. 3 is obtained. As shown in Figure 7, the period from when pulse a is generated until clock pulse b starts to be output as a switch drive pulse is ml.
Let m2 be the first period in which clock pulse b is continuously output as a switch drive pulse, m3 be the period in which clock pulse b continues to be output as a switch drive pulse after it has been interrupted, and period m3. This is because the following equations hold true, assuming that the period following , during which no switch drive pulse is output, is m4.

m, +m2+1 +m3 +m4 =29...
(8) m2 + m3= 28 ・
...(9) m+ =n+ X2' +n2
-- (10) m3-=n3 x2' +na
-(11) Furthermore, the following equation holds from equations (9) and (11).

m2 = 2 - (n3 X2' + n4)...
-(12) FIG. 8 is a block diagram showing another embodiment of the present invention. In the figure, input digital data is supplied to a switch driver 5. The switch driver 5 is supplied with the clock pulse b output from the clock generation circuit 6. The drive pulse output from the switch driver 5 is supplied to the control input terminal of the changeover switch 45. The output of the lamp voltage generation circuit 11 is supplied to one of the two input terminals of the changeover switch 45 . The other input terminal of the changeover switch 45 is grounded. The signal derived from the output terminal of the selector switch 45 is supplied to the negative input terminal of the operational amplifier 46 via the resistor Re. The positive input terminal of the operational amplifier 46 is grounded. Further, a capacitor C4 and a switch circuit 47 are connected in parallel between the negative input terminal and output terminal of the operational amplifier 46. The control input terminal of the switch circuit 47 is supplied with a pulse a. The switch circuit 47 is turned on when the pulse a is supplied, and the charge in the capacitor C4 is discharged. These operational amplifiers 46, resistors Re
1 capacitor C4 and a switch circuit 47 form an integrating circuit, and a resistor R is connected via a changeover switch 45.
A signal obtained by integrating the output of the ramp voltage generating circuit 11 supplied to one end of the voltage generator 46 is output to the output terminal of the operational amplifier 46.

The output of this operational amplifier 46 is
It is held as a D/A converted output.

Although it is possible to use a circuit having the configuration shown in FIG. 6 as the switch driver 5, it is also possible to use a circuit configured to output pulses as shown in FIG. 9 as the switch driver 5. In other words, input digital data is expressed in hexadecimal notation "'o o o o"
The first pulse b(1) to the second pulse b(28) of the clock pulses b sequentially generated from the time of pulse a.
The currents shown by diagonal lines in FIG. 9 <A> flow through the switch circuit 7.

Furthermore, when the input digital data becomes equal to the data ``0001'' expressed in hexadecimal notation, the clock pulse b (1) that occurs first among the clock pulses b that are generated sequentially from the generation of the pulse β. (2”1) pulse b (28-1) and (28
+1)th pulse b (28+1) generated is output, and a current as shown by diagonal lines in FIG. 9(B) flows through the switch circuit 7.
flows to

Also, when the input digital data becomes equal to the data "OOO2" expressed in hexadecimal notation, the clock pulse b (1) that occurs first among the clock pulses b that are generated sequentially from the generation of pulse a. (2”1)th pulse b (28-1) and (28+2
)-th generated pulse b(28+2) is output, and a current as shown by diagonal lines in FIG. 9(C) flows through the switch circuit 7.

Furthermore, when the input digital data becomes equal to the data ``0100'' expressed in hexadecimal notation, the first pulse b(1) of the clock pulses b sequentially generated from the generation of pulse a to ( Each of the pulses up to the 28-1)th generated pulse b(28-1) and the 29th generated pulse b(29) are output, as shown in FIG. 9(D).
A current as shown by diagonal lines flows through the switch circuit 7.

Also, when the input digital data becomes equal to the data ``0101'' expressed in hexadecimal notation, the clock pulse b (1) that occurs first among the clock pulses b that are generated sequentially from the generation of pulse a. Each of the pulses b (28-2> generated up to (2"2), the 28th pulse b (28), and the 29th pulse b (29) are output, and FIG. ) flows through the switch circuit 7 as indicated by diagonal lines.

Also, when the input digital data becomes equal to the data ``0200'' expressed in hexadecimal notation, the clock pulse b (1) that occurs first among the clock pulses b that are generated sequentially from the generation of the pulse a. (28-2)th pulse b generated up to (28-2) and (
The pulse b (29-1) generated at the 2''-1)th and the pulse b (29) generated at the 29th are output, and the pulse b (29-1) generated at the 9th
A current as shown by diagonal lines in the figure (F) flows through the switch circuit 7.

In addition, when the input digital data becomes equal to the data "0201" expressed in hexadecimal notation, the clock pulse b (1) that occurs first among the clock pulses b that are generated sequentially from the generation of pulse a. (28-3)th pulse b (28-3) and (2”l)
)th pulse b (28-1), (29-1) generated
The pulse b (2"1) generated at the 2nd time and the pulse b (29) generated at the 29th time are output, and currents as shown by diagonal lines in FIG. 9(G) flow through the switch circuit 7.

Also, when the input digital data becomes equal to the data expressed in hexadecimal notation ``FFFFF'', the pulse a
The 28th pulse b(28) and (2
8+2)th pulse b (28+2) to 2
Each pulse up to the ninth generated pulse b (29) is output, and a current as shown by diagonal lines in FIG. 9(H) flows through the switch circuit 7.

Although the case where the number of bits of input digital data is 16 has been described above, the present invention can be applied to any case where the number of bits of input digital data is 2 or more. Note that if the number of bits B of the input digital data is an even number, the clock frequency F is set to the sampling frequency S.
That is, it is necessary to set the clock frequency so that the value F/S obtained by dividing by the frequency of pulse a becomes a natural number of 2(B+2)/2 or more. Also, if the number of bits B of input digital data is odd, F/S is 2(B+1)/
It is necessary to set the clock frequency to be a natural number greater than 2×f2 by one or more.

As described in detail above, the D/A converter according to the present invention is capable of converting the integral command signal, which is generated a predetermined number of times in synchronization with the timing signal and at a timing corresponding to the value represented by the input digital signal, into one time Since the configuration is such that a linear function signal having a level corresponding to the next function is integrated, the frequency of the clock as a timing signal can be lowered. For example, in an integral D/A converter, the clock frequency is approximately 2.89 GHz.
(44,,1 KHz x 216), in the D/A converter according to the present invention, the clock frequency is set to approximately 22.6 MHz (44,, IKHz x 29>), which is the operating frequency value of the logical operation circuit. can do.

Furthermore, in the D/A converter according to the present invention, when the input digital data changes by 1, one of the predetermined fractions of the total period for integrating the linear function signal is shifted by one clock. Therefore, the differential linearity is good.

Furthermore, in the D/A converter according to the present invention, the accuracy is determined by the linearity of the circuit that generates the linear function signal, but it is also possible to use the circuit shown in FIG. Accuracy can be increased by using a capacitor C3 in the figure with low leakage and by using a capacitor with low gate leakage, such as an FFT input type, as the operational amplifier 10 to which the output of the circuit shown in FIG. 11 is supplied. There is no need to use high-precision parts such as a ladder mold/A converter.

Furthermore, in the D/A converter according to the present invention, when converting multiple channels of digital audio data, the circuit that generates the linear function signal can be shared, thereby reducing the level difference between channels. will be possible.

[Brief explanation of the drawing]

1 is a circuit block diagram showing an embodiment of the present invention, FIG. 2 is a waveform diagram showing the output current of the lamp current generating circuit 8, FIG. 3 is a diagram showing the action of the switch driver 5, and FIG. 4
The figure shows a specific circuit example of the lamp voltage generation circuit 11.
FIG. 5 is a diagram showing a specific circuit example of the switch circuit 7, and FIG.
The figure shows a specific circuit example of the switch driver 5.
The figure shows the action of the switch driver 5, and FIG.
29 A circuit block diagram showing another embodiment of the present invention, FIG.
FIG. 10 is a circuit block diagram showing the action of the switch driver 5, FIG. 10 is a circuit block diagram showing a ladder type/A converter, and FIG. 11 is a circuit block diagram showing an integral type D/A converter. Explanation of symbols of main parts 5...Switch driver 7.47...Switch circuit 8...Lamp current generation circuit 45...Selector switch 46... ...Operation amplifier

Claims (1)

[Claims] linear function signal generating means for generating a linear function signal having a period corresponding to the input timing of an input digital signal of at least one digit and having a level corresponding to a linear function of time; timing signal generating means for generating a timing signal that is generated with a period that is an integer fraction of the period of the linear function signal; comprising a command signal output means for outputting an integral command signal that is generated a number of times, and an integrating means for integrating the linear function signal when the integral command signal is present;
A digital converter that uses the output of the integrating means as an analog output.
analog converter.