JPS62143518A - Power supply circuit - Google Patents

Abstract

PURPOSE:To reduce the power consumption of a semiconductor integrated circuit under a standby state, by providing a switching circuit which selects one out of the 1st and 2nd power supply courses in accordance with the operating state of the semiconductor integrated circuit. CONSTITUTION:Each control signal phi0 and phi3 is set to a level corresponding to the states of devices, namely, standby states and active states of the devices in accordance with commands from a CPU, with the devices being made to correspond to the control signals phi0 and phi3. A switch which is controlled by such control signals supplies voltages of the 1st and 2nd power sources V1 and V2 to one of the devices which is to be set to its active state by the CPU and the voltage of the 1st power source V1 to the other device which is to be set to a standby state b the CPU. The voltage of the 1st power source V1 is sufficient to guarantee the necessary minimum operations of the device under the standby state. Therefore, the power consumption can be reduced without hindering the stability of the system operation.

Description

[Detailed Description of the Invention] [Technical Field] The present invention relates to a power supply circuit, and relates to a technology that is effective when applied to a system including a semiconductor integrated circuit having a standby function such as a RAM (Random Access Memory), for example. It is.

[Background technology]

CPU (Central Processing Unit)
, ROM (read-only memory), memory such as RAM, and microcomputer systems including shift registers, etc., as the number of constituent devices increases and the memory storage capacity increases, lower power consumption is required. By the way, the inventor of the present invention believes that since the constituent devices of such a system are operated by receiving instructions from the CPU, it is necessary for devices with a standby function to be supplied with the minimum operating voltage from the power supply circuit in the standby state. For example, RA where data is not being read or written.
It is sufficient that M receives at least a voltage necessary to hold stored data.

However, conventionally, in systems that include devices with standby functions, a constant power supply voltage was supplied regardless of whether the devices with standby functions were in standby or active states, resulting in wasted power consumption in each device. was.

In addition, as an example of a document describing the reduction of power consumption in microcomputer systems,
Published by OA on January 30th (7) rLSI Handbook J
There is P546.

[Purpose of the invention]

An object of the present invention is to provide a power supply circuit that can reduce power consumption in a system including a semiconductor integrated circuit having a standby function.

The above and other objects and novel features of the present invention include:
It will become clear from the specification and accompanying drawings.

[Summary of the invention]

A brief overview of typical inventions disclosed in this application is as follows.

That is, a first power supply path supplies the semiconductor integrated circuit with the necessary voltage when the semiconductor integrated circuit is in the standby state, and a second power supply path supplies the semiconductor integrated circuit with the minimum voltage necessary for the minimum operation when the semiconductor integrated circuit is in the active state. By providing a switch circuit with a CMO8 circuit configuration that selects the path according to the operating state of the semiconductor integrated circuit,
This reduces the power consumption of the semiconductor integrated circuits that make up the system in a standby state.

[Embodiment 1] FIG. 1 is a circuit diagram showing an embodiment of a power supply circuit according to the present invention. The circuit shown in the figure is applied to a microcomputer system, and includes a control circuit 1 including a CPU.
．． ROM (read/read memory) that stores instructions to be processed.
static RAM that stores data necessary for processing, and DMA (direct memory access) that directly transfers data blocks between the RAM and a peripheral I10 device (not shown) without going through the CPU.
controller), and a counter that counts external pulse signals independently of the operations of the CP and U, and a CTC (counter timer circuit) that operates as a timer based on the system clock. Note that data bus lines, control path lines, and the like that connect the above-mentioned devices are omitted in FIG. 1.

In the above system, the power supply circuit is "1 RAM
, ROM, DMA, and CTC (hereinafter also simply referred to as devices) have a first power supply V1 that supplies a voltage sufficient to guarantee the minimum operation required for them in a standby state. For example, the voltage of the first power supply v1 is sufficient for the static memory cells included in the RAM in the standby state to hold necessary data. Further, in order to supply voltage sufficient to fully drive these devices in their active states, a second power source 2 is connected in series with the first power source.

=4- In the figure, 2 is a switch circuit that selectively supplies the voltage of the first power supply v1 and the voltages of the first power supply v1 and the second power supply v2 to the device, and a switch circuit 2 corresponds to each device. It is composed of switches SWo to SW3. Each of the switches SWa to Sw3 is a P-channel type MO8FET and an N-channel type MO8FE, which are complementary switch-controlled by receiving a control signal at the gate, although not particularly limited thereto.
It is composed of a CMO8 circuit (not shown) consisting of T,
Its output terminal is coupled to a power supply terminal (not shown) of a corresponding device.

Each of the switches SWo to Sw3 receives a control signal φ from the control circuit 1. The switches are controlled in response to signals φ3 to φ3.

Each control signal φ. φ3 to φ3 are set to levels according to the state of the corresponding device, that is, the standby state or active state of the device based on an instruction from the CPU. A switch controlled in response to such a control signal is CP
The voltages of the first power supply v1 and the second power supply ■2 are supplied to the device to be brought into the active state by U, and the CP
The voltage of the first power supply v1 is supplied to the device to be put into standby state by U.

Therefore, during the operation of the system described in 1.
In the step of reading data from and transferring it to the CPU, only the RAM to be activated is supplied with the voltages of the first power supply v1 and the second power supply v2 necessary for its operation, and the rest are placed in a standby state. The voltage of the first power supply v1 is supplied to the device. Also, ROM
In the step of directly transferring a block of data between the ROM and the DMA, the voltages of the first power supply v1 and the second power supply v2 necessary for their operation are supplied only to the ROM and DMA to be activated, and the voltages of the first power supply v1 and the second power supply v2 necessary for the operation are supplied to the ROM and DMA, which are to be activated. The device to be brought into the state is supplied with the voltage of the first power supply (1).

In this way, the device to be placed in the standby state is supplied with the first power supply v1, which has a lower voltage than the device in the active state.
Moreover, the voltage of the first power supply v1 supplied to the devices to be put into standby state is sufficient to guarantee the minimum operation required for them in the standby state, so that the system operation is controlled. Power consumption can be reduced without sacrificing stability. Also,
Of course, the effect of reducing power consumption that occurs when a device is changed from an active state to a standby state is also taken into account.

[Embodiment 2] FIG. 2 is a circuit diagram showing another embodiment of the power feeding circuit according to the present invention. The power supply circuit shown in the same figure includes the second power supply v
A booster circuit V that boosts the voltage of the first power supply v1 instead of V2
ro to vr3, supplies the voltage from the booster circuit to devices to be put into an active state by the CPU, and supplies the voltage of the first power supply v1 to devices to be put into a standby state by the CPU. . A configuration in which such a booster circuit and switch circuit 2 are combined can also reduce power consumption without impairing the stability of system operation, as in the above embodiment. Also,
Although not shown, it goes without saying that similar effects can be obtained even in a circuit configuration having a booster circuit common to a plurality of devices.

〔Effect of the invention〕

According to the invention disclosed in this application, a lower voltage is supplied in the standby state of the semiconductor integrated circuit than in the active state, and the voltage is sufficient to guarantee the minimum operation required in the standby state. Power consumption can be reduced without compromising the stability of the system.

Although the invention achieved by the present inventor has been specifically described above based on examples, the present invention is not limited to the above-mentioned examples, and various modifications can be made without departing from the gist thereof. For example, the devices constituting the system of the above embodiment are not limited to those described above, but can be changed to a dynamic RAM or various other I10 devices.

[Application field]

The above explanation has mainly been about the case where the invention made by the present inventor is applied to microcomputer systems, which is the technical field behind the invention, but the invention is not limited to this, and is applicable to LSI and various other circuits. can be widely used.

[Brief explanation of drawings]

1 is a circuit diagram showing one embodiment of the power supply circuit according to the present invention, and FIG. 2 is a circuit diagram showing another embodiment of the power supply circuit according to the present invention. 1... Control circuit, 2... Switch circuit, SW, -5
W3...Switch, ■1...First power supply, v2...
Second power supply, vr6-Vra... booster circuit.

Claims (1)

[Claims] 1. A circuit that supplies voltage necessary for the operation of a semiconductor integrated circuit, the circuit supplying a relatively low voltage close to the voltage necessary for minimum operation of the semiconductor integrated circuit in a standby state to the semiconductor integrated circuit. A switch circuit is provided that selects a first power supply path for supplying the semiconductor integrated circuit and a second power supply route for supplying the semiconductor integrated circuit with a relatively high voltage necessary in the active state of the semiconductor integrated circuit, depending on the operating state of the semiconductor integrated circuit. A power supply circuit characterized in that it is provided with a power supply circuit. 2. The power supply circuit according to claim 1, wherein the first power supply path has a first power supply, and the second power supply route has a second power supply connected in series with the first power supply. 3. The power supply circuit according to claim 1, wherein the second power supply path includes a booster circuit that boosts the voltage of the first power supply provided in the first power supply path.