JPH0736140B2 - Waveform generator - Google Patents

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a waveform generator that generates a waveform by a digital circuit, and more particularly to a waveform generator whose waveform access rate changes in one cycle of the waveform.

[0002]

2. Description of the Related Art With the progress of digital technology, it has become possible to generate waveform data in a digital circuit and convert the waveform data into an analog signal by a digital-analog converter to generate an analog signal waveform. Waveform generation by such a digital circuit is also used in electronic musical instruments, and electronic musical instruments capable of generating various timbre waveforms have been commercialized.

Conventionally, (a) sine wave synthesizing method is used as a musical tone generating method for an electronic musical instrument by the digital circuit as described above.
There are (b) variable filter system, (c) waveform memory read system, and (d) frequency modulation system.

The above-mentioned (a) sine wave synthesizing method is a method for generating a fundamental wave and a harmonic sine wave signal in a digital circuit and synthesizing the digital waveform signals to generate a musical tone of a desired timbre. This method requires as many calculation channels as the number of kinds of overtones required to obtain a musical tone having a desired overtone structure. Further, in the case of changing the spectrum with time, harmonic control signals of the number of kinds of overtones for varying the amplitude level for each overtone are required. This method has a problem in that the generation circuit becomes large because the above-mentioned calculation channel and the harmonic control signal require circuits of the number of kinds of harmonics, and the generation control of the harmonic control signal becomes complicated.

The variable filter method (b) uses a digital filter and changes the frequency characteristic of the filter by a harmonic control signal. This method has a problem that the circuit of the digital filter becomes large. Furthermore, when a waveform is generated at a fixed sampling rate, that is, when an original sound that is the input to the digital filter is generated at a fixed sampling rate, it is difficult to obtain a waveform with many harmonics, and the harmonic region of the digital filter is therefore difficult to obtain. However, there is a problem that the effect in (1) is halved. Furthermore, this method has a problem of causing aliasing distortion.

The waveform memory reading method of (C) is a method of generating waveform by sequentially reading the waveform data stored in the memory or the like in correspondence with the phase angle. Since the waveform data stored in the above-mentioned waveform memory is musical tone waveform data generated as a musical tone, the spectrum of the waveform is fixed. Therefore, in order to change the spectrum, it is necessary to store the waveform data corresponding to the change in the spectrum in the memory, and further, a control circuit is required to read them out in response to the change in the spectrum. Therefore, this method has a problem that the memory capacity increases and the control circuit becomes complicated. As a disclosure of one development of the waveform memory reading method of (C), there are JP-A-54-61511, JP-A-54-61512 and JP-A-55-164898. . In these disclosed techniques, the frequency information that determines the frequency of the waveform is switched in the middle of one cycle of the waveform, and the waveform (for example, a sine wave) stored in the waveform memory is read as a distorted waveform. Will come out.

However, in this prior art, if the method of distorting the waveform is to be changed, the frequency information must be appropriately changed, and the method of distorting the waveform is changed without changing the frequency of the generated musical tone. Has problems that need to be improved, such as requiring complicated calculations.

As another development of the waveform memory reading method of (C), there is a method using a non-linear conversion table memory. JP-A-54-66826 discloses such a prior art.

According to the technique disclosed in this publication, the sine wave and the triangular wave are non-linearly converted by the non-linear conversion table memory to have variously changed waveforms.

However, in this prior art, the non-linear table memory must first be prepared. Furthermore, it is difficult to intuitively understand how the waveform obtained by non-linear conversion becomes. Further, when it is attempted to change the spectrum with time, it is difficult to understand what kind of parameter should be changed and how to increase / decrease the content rate of the harmonic component. There are various inconveniences.

The method (d) is an application of frequency modulation, and is a method of changing the frequency ratio and the modulation depth by using a carrier wave and a modulation wave, that is, two sine waves to change the overtone. Although this method can control overtones to some extent, it is difficult to obtain a musical tone whose spectrum envelope changes smoothly because each harmonic changes like a Bethel function.

[0012]

SUMMARY OF THE INVENTION The present invention has been made in the background described above, and provides a waveform generator capable of smoothly changing and controlling the spectrum of a waveform according to a modulation signal.

[0013]

A waveform generator of the present invention corresponds to a storage means for storing waveform information and a frequency of a waveform to be generated in order to read the waveform information stored in the storage means. , An address signal generating means for generating an address signal representing a phase angle changing at a uniform rate over one cycle of the waveform, and a half cycle of the waveform represented by the waveform information stored in the storage means. Modulation signal generating means for generating a modulation signal for determining the degree of phase modulation when the waveform information is read as waveform information expressing a waveform having a distorted phase by determining a period for reading the waveform information; An address signal and the modulated signal are input, and while the address signal is stepped through a period designated by the modulated signal, the waveform information of the 1/2 cycle is stored from the storage means. A corrected address signal for projecting is generated, and while the address signal is stepped over at least a part of the remaining period of one cycle excluding the period designated by the modulation signal, 1/2 of the residue is generated. Modifying means for generating a modified address signal for reading cycle waveform information from the memory means, and the memory means for accessing the memory means with the modified address signal generated by the modifying means, and the address signal generating means generating the modified address signal. A waveform having a frequency determined according to the address signal and representing a waveform having a distorted shape from the waveform represented by the waveform information stored in the storage means by an amount according to the modulation signal generated from the modulation signal generation means. And access means for outputting information.

[0014]

According to the present invention, according to the above construction, the modified address signal whose step rate changes in one cycle of the waveform is generated according to the modulated signal, and the modified address signal accesses the waveform information. Therefore, a waveform having a distorted shape is output from the waveform stored in the storage means by an amount according to the modulation signal.

[0015]

The present invention will be described in detail below with reference to the drawings. FIG. 1 is a circuit configuration diagram of an embodiment of the present invention. FIG. 1 shows an embodiment in which the present invention is applied to an electronic musical instrument. The first output of the keyboard 1 is input to the frequency information generation circuit 2, and the second output is input to the harmonic control signal generation circuit 4 and the envelope control signal generation circuit 5. The output of the frequency information generation circuit 2 is applied to the first input terminal of the phase angle calculation circuit 3. The output of the phase angle calculation circuit 3 is the second input terminal and the waveform synthesis circuit 8
Connected to the input terminal A of. Harmonic control signal generation circuit 4
Is connected to the first input terminal of the adder circuit 6. A control signal from another circuit (not shown) is input to the second input of the adder circuit 6. The output of the adding circuit 6 is the waveform synthesizing circuit 8
Input to the input terminal B of. The output terminal C of the waveform synthesis circuit 8 is connected to the first input of the envelope multiplication circuit 7, and the output of the envelope control signal generation circuit 5 is connected to the second input. The output of the envelope multiplication circuit 7 is connected to a digital-analog conversion circuit DAC (not shown).
The keyboard 1 is a circuit that generates the position information of the pressed key and the timing signal of the pressed key. The key position information is sent to the frequency information generating circuit 2 and the key timing signal is sent to the harmonic control signal generating circuit 4, Input to the envelope control signal generation circuit 5, respectively. The frequency information generating circuit 2 is a circuit that generates frequency information, that is, phase angle information corresponding to the key from the position information of the pressed key, and outputs the phase angle information sequentially by a specific clock, for example. The phase angle calculation circuit 3 adds and outputs the information applied to the first input terminal and the second input terminal. Since the output of the phase angle calculation circuit 3 is applied to the second input terminal of the phase angle calculation circuit 3, the phase angle information generated by the frequency information generation circuit 2 is sequentially added to the contents of the phase angle calculation circuit 3 by a specific clock. . That is, the phase angle information generated by the frequency information generating circuit 2 is accumulated by the phase angle calculating circuit 3. The accumulation is performed in units of one cycle, and when the phase angle is one cycle or more, the phase of one cycle is subtracted. In the embodiment of FIG. 1, for example, 2 ¹² is a phase angle of one cycle (that is, equivalent to 2π), and when the value is more than that, a carry is output but the carry is not used. As a result, the phase angle for one cycle is subtracted. The output of the phase angle calculation circuit 3 is input to the input terminal A of the waveform synthesis circuit 8. The timing signal is input to the harmonic control signal generating circuit 4, and is converted by the harmonic control signal generating circuit 4 into a tone color control signal for changing the harmonic component with time. The output, that is, the tone color control signal is added to a control signal from the outside, for example, a control signal for changing the tone color by an external operator in the adding circuit 6. The adder circuit 6 can be omitted if no control signal is input from the outside. The output of the adding circuit 6 is applied to the output terminal B of the waveform synthesizing circuit 8. The waveform synthesizing circuit 8 is a circuit for obtaining a corrected address signal whose rate changes over one period from the address signal which is output from the input terminal A and which represents the phase angle which changes at a uniform rate, and accesses the waveform. The rate changes depending on the control signal input.

For example, the waveform synthesis circuit 8 comprises a division circuit 9 and a waveform memory 10 as shown in FIG. The division circuit 9 divides the phase angle input from the input terminal A by the tone color control signal, that is, the harmonic control signal input from the input terminal B in a specific phase angle range, and further divides it by another value in another specific range. It operates like you do. That is, in the waveform synthesizing circuit 8, the way in which the phase angle advances is not constant over one cycle but changes. As a result, the waveform memory 10 in the waveform synthesis circuit 8 is accessed, and the waveform data is output from the output terminal C. Since the access to the memory at this time is not constant over one cycle but changes within one cycle, waveform data in which the phase of the waveform stored in the waveform memory 10 is distorted is output from the output terminal C.

The timing signal of the keyboard 1 is further input to the envelope control signal generating circuit 5. The envelope control signal generation circuit 5 generates control data for changing the amplitude of the output musical sound. The output, that is, the envelope signal is input to the envelope multiplication circuit 7. On the other hand, the waveform data output from the output terminal C of the waveform synthesizing circuit 8 is input to the envelope multiplying circuit 7, and the envelope multiplying circuit 7 multiplies the waveform data and the envelope signal and outputs the result.

FIG. 3 is a circuit diagram showing in more detail the configuration of the waveform synthesizing circuit 8 of the embodiment of the present invention shown in FIG.
Symbols in the figure are abbreviated, and each symbol a,
c has the configuration shown in b and d. FIG. 4a shows a gate circuit of the FET in b, where the source and drain correspond to the input / output of the gate circuit and the gate corresponds to the control input terminal. FIG. 4c represents the exclusive logic OR gate of the input of d. The input terminal N has a gate group G1 and a gate group G2.
It is connected to the. The other ends of the gate groups G1 and G2 are connected to the exclusive logic OR group EOR1 and the output signals thereof are input via the exclusive logic OR group EOR2 to the inputs A0 to A0 of the divider DIV.
Input in A11. The gate group G1 is connected so that each bit position N0 to N11 of the input terminal N is shifted by one bit to the upper bit, and the least significant bit is connected to input the low level (ground level). The control input terminal of the gate group G2 is connected to the control terminal SAT, and the control input terminal of the gate group G1 is connected to the control terminal SAT via the inverter I1. The control terminal SIP is connected to the first input of the AND gate AND1, the bit N11 of the input terminal N is input to the second input, and its output is commonly used by the second input of the exclusive logic OR group EOR1. Connected.

Bits M0 to M10 of the input terminal M are connected through the exclusive logic OR group EOR3, and bit M11 is connected to the gate G.
3 and the exclusive logical OR group EOR3 to input to the inputs B0 to B11 of the divider DIV. Exclusive logical OR group EOR
The gate G4, the other of which is grounded, is connected to the input corresponding to the bit M11 of 3, and the control terminal SAT is connected to the control input terminal thereof. On the other hand, the SAT is connected to the control input terminal of the gate G3 via the inverter I2.
The outputs of the exclusive logical OR group EOR1 are supplied to the first inputs A11 to A0 of the comparator COMP and the second inputs B11 to
The same signal as that input to the exclusive logic OR group EOR3 is input to B0, and its comparison output OUT is an AND gate AN.
Connected to the first input of D2. AND gate AND2
The control terminal SAT is connected to the second input of, and its output is the exclusive logical OR group EOR2 and the exclusive logical OR group EOR.
Input commonly to the second input of each of the three.

The operation outputs D0 to D11 of the divider DIV are input to the address input of the read only memory ROM via the gate groups G5 and G6. The read-only memory ROM stores the waveform amplitude value of a half wavelength of the cosine wave, and corresponds to -1 when all outputs are at low level and +1 when all outputs are at high level. The control terminal SQU is connected to the control input terminal of the gate group G5 and the control input terminal of the gate group G6 via the inverter I3. The outputs O0 to O10 of the read only memory ROM are output via the exclusive logic OR group EOR4. The control terminal SQU and the bit N11 are respectively input to the AND gate AND3, and the outputs thereof are commonly input to the inputs of the exclusive logic OR group EOR4.

In the embodiment of the invention in FIG. 3,
The input terminals N and M are respectively the waveform synthesis circuit 8 in FIG.
Corresponding to inputs A and B of. That is, as shown in FIG.
12-bit phase angle data N0-N11, for example, is input to the input terminal M, and 12-bit tone color control data, that is, modulation depth data M0-M11 from the adder circuit 6 of FIG. To enter.

As described above, this circuit uses SAT, SI
It has three control terminals P and SQ, and by selecting one of them, that is, by inputting a high level to one of the control terminals, the input terminal M
The waveform changes variously depending on the input signal.

First, when a high level signal is input to the control terminal SAT and a low level signal is input to the control terminals SIP and SQU, a sawtooth wave is generated. When a low level signal is input to the control terminals SIP and SQ, AND gates AND1 and A
The output of ND3 becomes a low level signal, and the exclusive logic OR groups EOR1 and EOR4 operate as a buffer. Since a low level signal is input to the control input terminal of the gate group G5, the gate group G5 is turned off. Further, since a low level signal is input to the inverter I3, its output becomes a high level, and its output, that is, a high level signal is input to the control input terminal of the gate group G6.
Turns on. That is, the outputs D1 to D1 of the divider DIV
1 is the address A0 to A10 of the read-only memory ROM
Enter each in.

On the other hand, since the high level signal is input to the control terminal SAT, the gate group G2 is turned on, and the low level signal is input to the control input terminal of the group G1 which is input via the inverter. , The gate group G1 is turned off. That is, each bit N0 to N11 of the input N is input to the inputs A0 to A11 of the divider DIV in the exclusive logical OR group EOR2.
To enter via. When a high level signal is input to the control terminal SAT, the gate G4 is turned on and the gate G3 is turned off, so that the input of the exclusive logic OR group EOR3 corresponding to the input B11 of the divider DIV becomes low level.

The value input to the input terminal N and the value input to the input terminal M are compared by the comparator COMP.
When the value input to the input terminal N is smaller than the value input to the input terminal M, a low level signal is output from the comparison output OUT, and the low level signal is output to the exclusive logic OR groups EOR2 and EOR3 via the AND gate AND2. input. As a result, the exclusive logical OR groups EOR2 and EOR3 operate as a buffer. When the phase angle advances in sequence and the value input to the input terminal N becomes larger than the value input to the input terminal M, a high level signal is output from the comparison output OUT of the comparator COMP. As a result, the output of the AND gate AND2 becomes high level, and its output is the exclusive logic OR group EO.
Since it is input to R2 and EOR3, the exclusive logic OR groups EOR2 and EOR3 operate as inverters.

That is, when a high level signal is inputted to the control terminal SAT and a low level signal is inputted to the control terminals SIP and SQU, the value generated from the phase angle calculation circuit 3 and inputted from the input terminal N, that is, the phase angle address value NX. On the other hand, the value is distorted by calculation, and the waveform stored in the read-only memory ROM is read out and changed by a new phase angle address value LX after calculation. Figure 5
Shows the waveform diagram. The horizontal axis represents time t, and the vertical axis represents the normalized value of amplitude. In the waveform AX, the modulation depth information MX is MX = T
In the case of / 2, the waveform BX is the case of MX <T / 2, where T represents one period of the waveform. In this operation, the value input to the divider DIV changes depending on the comparison result of the comparator COMP, so one cycle will be described as two conditions. Read-only memory R when NX≤MX
It operates so that the length of 1/2 cycle of the cosine wave stored in the OM becomes the modulation depth information. That is, with respect to the value NX1 of the phase angle address value in this condition, LX1 at this time is LX1 = NX1 / MX · T2 (1). Since the divider DIV is a binary operation and the cycle is a power of 2, the embodiment of the present invention shown in FIG. 3 particularly multiplies T / 2 on the right side of the equation (1). However, the output of the divider DIV is a value below the decimal point, and the output D11 is a binary point below the decimal point.
And the output D10 becomes the second place after the decimal point of binary,
Since the value is shifted to the lower bit by 1 bit and used as the address of the read only memory ROM, the result is equivalently multiplied by T / 2.

When NX> MX, the remaining 1/2 cycle of the cosine wave stored in the read-only memory ROM is T.
-Move to become MX. That is, M in this condition
With respect to the value NX2 of X, the phase angle address value LX2 after calculation at this time satisfies T-LX2 = (T-NX2) / (T-MX) .T / 2 (2).

Since the period T is this power, T-MX = bar MX, T-NX2 = bar NX2, T-LX2 = bar LX2, and the calculated phase angle address value LX2 is LX2 = bar NX2 / It is represented by bar MX · T / 2 (3). Here, "bar" indicates an inversion signal of each signal. In the circuit of FIG. 3, when this condition, that is, NX> MX, the comparator COM
The output of P becomes the high level, and the high level signal is transmitted through the AND gate AND2 to the exclusive logical OR group EOR2, EOR.
Since it is input to OR3, exclusive logical OR groups EOR2, E
The OR3 operates as an inverter, and the dividers DIV input bars MX and NX, respectively. Although its output, that is, LX2, is not inverted, the waveform input to the read-only memory ROM is a cosine wave of ½ wavelength, so the same applies whether LX or bar LX is input. The output is directly input to the address of the read-only memory ROM without being inverted. The waveform data of the read-only memory ROM is output according to the address value. The value is the waveform BX in FIG. As a result, the read-only memory ROM need only store the half wavelength of the cosine wave, and the storage capacity can be half. The waveform read from the read-only memory ROM has a half-wavelength in the range of 0 <NX ≦ MX, and has a half-wavelength in the remaining MX <NX <T. As a result, when MX is smaller than T / 2, a sawtooth wave is formed.

The timbre of the waveform of the sawtooth wave, that is, the spectrum changes depending on MX. 6,
FIG. 7 shows the output waveform a and its spectrum b of the above-described operation in the embodiment of the present invention. 6 shows MX = T /
In the case of 2, the modulation depth at this time is 100%.
FIG. 7 shows the case of MX = T / 8, and the modulation depth is 25%. In FIG. 6a and FIG. 7a, the horizontal axis represents time t and the vertical axis represents amplitude. 6b and 7b, the horizontal axis represents frequency f and the vertical axis represents the amplitude of each frequency. MX in FIG. 6 is 100
When%, the cosine wave stored in the read-only memory ROM is sequentially read out at equal time intervals, so that there is no harmonic component and only the fundamental wave. MX in FIG.
Is 25%, the time interval for reading the cosine wave stored in the read-only memory ROM in units of half a wavelength is different, so that it becomes a sawtooth wave and its spectrum is the fundamental wave and the secondary,
It has high-order harmonics such as third order. Although it has been described only when MX is 25%, the higher harmonics of the higher harmonics are changed by changing the value of MX.

Next, when a high level signal 1 is input to the control terminal SQU and a low level signal is input to the control terminals SAT and SIP, a rectangular wave is generated.

When a low level signal is input to the control terminal SAT, the gate G4 is turned off, and since a high level is input to the control terminal of the gate G3 via the inverter I2, the gate G3 is turned on. Further, since the low level signal is also input to the AND gate AND2, its output also becomes low level, and the exclusive logic OR groups EOR2 and EOR3 operate as a buffer. At this time, the comparator COMP operates, but its output is input to the AND gate AND2 and therefore does not affect the overall operation. As a result, the signal input from the input terminal M is sent to the divider DIV for each bit M0.
.. to M11 correspond to the bits B0 to B11 and are input as they are. On the other hand, since the low level signal is input to the control terminal SIP, the gate group G2 is turned off and the inverter I
Since a high level signal is input to the control terminal of the gate group G1 via 1, the gate group G1 is turned on. Further, since the low level signal is also input to the AND gate AND1, the output of the AND gate AND1 also becomes low level, and the exclusive logic OR group EOR1 operates as a buffer. As a result, the signal input from the input terminal N is input to the divider DIV in which the bits N0 to N10 correspond to the bits A1 to A11. That is, it is shifted by 1 bit and input to the divider DIV. The low level signal is input to the input A0 of the divider DIV because the gate corresponding to the input A0 of the gate group G1 is grounded. Since a high level signal is input to the control terminal SQU, the gate group G5 is turned on, and a low level signal is input to the control terminal of the gate group G6 via the inverter I3, which is turned off. As a result, the divider D is assigned to the addresses A0 to A10 of the read-only memory ROM.
The IV outputs D0 to D10 are correspondingly input. The output D11 of the divider DIV is not used. Furthermore, since a high level signal is also input to the AND gate AND3, M11 of the input terminal N is input to the exclusive logic OR group EOR4 via the AND gate AND3. That is, the input terminal N
The exclusive logic OR group EOR4 operates as a buffer when the top bit N11 of the input data is low level, and operates as an inverter when it is high level.

Here, the value input from the input terminal N is NX in the same manner as described above, and the value before 1/2 cycle, that is, before T / 2 is NX1, and the value after T / 2 is NX2. The upper bits N11 of NX1 and NX2 are different,
N1 is low level for 1 and N11 is high level for NX2.

When NX≤T / 2, the high-order bit N11 becomes low level as described above. As a result, the output of the AND gate AND3 also becomes low level, and since the output is input to the exclusive logic OR group EOR4, the exclusive logic OR group EOR4 operates as a buffer. In this state, when NX≤MX, the address value, that is, the outputs D1 to D11 of the divider D1V access the address of the read-only memory ROM storing the waveform of 1/2 wavelength. Since the high-order bit D11 is open, data stored in all the read-only memory ROMs is designated and output from the read-only memory ROM in this range, that is, NX ≦ T / 2. In this state, since the output of the AND gate AND3 is at the low level, the output of the read-only memory ROM remains unchanged and the terminal C
Will be output. On the other hand, when T / 2 ≧ NX> MX, all the outputs of the divider DIV become high level. This is because the output of the divider DIV outputs a value after the decimal point, and when the value is 1 or more, the circuit is configured so that all of them are at the high level. That is, when T / 2 ≧ NX> MX, the outputs are all at the high level, so the output of the read-only memory ROM is the final value of ½ wavelength stored in the read-only memory ROM. When NX> T / 2, the upper bit N11 becomes high level. As a result, the output of the AND gate AND3 also becomes high level, and since the output is input to the exclusive logic OR group EOR4, the exclusive logic OR group EOR4 operates as an inverter.
In this state, when the value NX 'input from the input terminal N excluding the upper 1 bit, that is, N11 is NX'≤MX, the output of the divider DIV has the same movement as in the case of NX≤MX. However, the read only memory R at this time
The output of the OM is inverted by the exclusive logic OR group EOR4, and the waveform stored in the read-only memory ROM is 1/2 wavelength of the cosine wave, so that the waveform output from the terminal C is NX≤MX. And the opposite. N
When X ≧ MX, all the outputs of the divider DIV become high level and the exclusive logic OR group EOR4 operates as an inverter. Therefore, the value output from the terminal C is the value output from the read-only memory ROM. It will be the opposite value. Figure 8
Shows the waveform diagram.

The horizontal axis shows the time t, and the vertical axis shows the normalized value of the amplitude. The waveform AX is a waveform when the modulation depth information MX is MX = T / 2, and the waveform BX ′ is a waveform when MX <T / 2. As described above, in the half of one cycle, that is, in the first half T / 2, when NX ≦ MX, the phase angle address value LX after calculation is calculated.
1 becomes LX1 = NX1 / MXT / 2 (4) with respect to the value NX1 of NX at this time. Further, when NX> MX, the phase angle address value LX1 'after calculation at this time is LX1 = T / 2 (5) regardless of the NX value NX1' at that time, as described above. As described above, in the embodiment of the present invention of FIG. 3, although not particularly multiplied by T / 2, the divider DIV is a binary operation, and the period T is also a value of this power, The result is equivalently multiplied by T / 2 by the connection of each bit. In the latter half cycle, the values NX2 and LX3 of NX and LX at this time are the same as those in the expressions (4) and (5). Although the operation is almost the same as the first half cycle, the output of the read-only memory ROM is inverted by the exclusive logical OR group EOR4, and therefore its amplitude has an inverted waveform. This results in a rectangular wave such as BX ', and the tone color of the waveform of the rectangular wave, in other words, the spectrum changes with MX.

FIG. 9 shows an output waveform A and a spectrum B when the modulation depth of the above-mentioned operation is 25% in the embodiment of the present invention. In FIG. 9, as in FIGS. 6 and 7, the horizontal axis of A indicates time t and the vertical axis indicates amplitude. The horizontal axis of B shows the frequency f and the vertical axis shows the amplitude of each frequency. When the modulation depth is 100%, that is, MX = T / 2, a cosine wave is obtained, and the waveform and spectrum shown in FIG. 6 are obtained. However, as shown in FIG.
When the modulation depth is less than 100%, harmonics are generated, and the harmonics are odd harmonics such as third, fifth, seventh ... These odd harmonics vary with MX.
Also, in this operation, even harmonics are not generated.

Further, a high level signal is applied to the control terminal SIP,
When a low level signal is input to the control terminals SAT and SQU, an impulse waveform is generated.

When a low level signal is input to the control terminal SAT, the gate G4 is turned off, and since a high level is input to the control terminal of the gate G3 via the inverter I2, the gate G3 is turned on. Further, since a low level signal is also input to the AND gate AND2, its output also becomes low level, and the exclusive logic OR groups EOR2 and EOR3 operate as a buffer. At this time, the comparator COMP operates, but since the output at that time is input to the AND gate AND2, it does not affect the overall operation. As a result, the signal input from the terminal M is input to the divider DIV in which the bits M0 to M11 correspond to the bits B0 to B11. A when a low level signal is input to the control terminal SQ
The output of ND3 becomes low level, and the output, that is, the low level signal is input to the exclusive logical OR group EOR4, so that the exclusive logical OR group EOR4 operates as a buffer. Since a low level signal is input to the control input terminal of the gate group G5, G5 is turned off. Further, since the low level signal is also input to the inverter 13, its output becomes high level, and its output, that is, the high level signal is input to the control input terminal of the gate group G6, so that the gate group G6 is turned on. As a result, the outputs D1 to D11 of the divider DIV are input to the addresses A0 to A10 of the read-only memory ROM, respectively. Also the divider D
The least significant bit D0 of IV is open. Further, a low level is also input to the exclusive logical OR group EOR4, and the exclusive logical OR group EOR4 operates as a buffer. Therefore, the outputs O0 to O11 of the read-only memory ROM are connected to the terminal C.
Will be output.

The input from the control terminal SAT, that is, the low level signal is input to the inverter I1, and the output thereof is input to the gate of the gate group G1, so that the gate group G1 is turned on. At this time, since the gate group G2 is off, the signals N0 to N11 input from the input terminal N are the most significant bit N.
11 are input to the inputs A1 to A11 of the divider DIV through the exclusive logic OR group EOR1. A low level signal is input to the input A0 via the exclusive OR group EOR1. AND gate AND1 has a control terminal S
Since the input of IP, that is, the high level signal is input, and the most significant bit N11 of the input terminal N is input to the other input, the exclusive logic OR group EOR1 has the most significant bit N11 of the input terminal N at the low level. It operates as a time buffer and an inverter when it is at a high level.

When the signal NX input from the input terminal N is smaller than 1/2 of one cycle T, the read-only memory ROM is sequentially accessed when NX≤MX. Thus, during this period, that is, O <NX ≦ MX, a cosine wave having a half wavelength is output from the terminal C. When NX> MX, all the outputs of the divider DIV become high level. This is because, as described above, the output of the divider DIV outputs a value after the decimal point, and when it is 1 or more, the circuit is configured so as to be all at a high level. That is, when NX> MX, all outputs are at high level, so the output of the read-only memory ROM is the final value of 1/2 wavelength stored in the read-only memory ROM. And NX> T /
In the case of 2, the upper bit N11 becomes high level.
As a result, the output of the AND gate AND1 also becomes high level, and since the output is input to EOR1, the exclusive logic OR group EOR1 operates as an inverter. When the inversion value NX 'of the value input from the input terminal N excluding the most significant bit N11 is NX'≥MX, the operation result of the divider DIV is 1 or more, so that the outputs of the divider DIV are all high level. Becomes As a result, the output of the read-only memory ROM during this period becomes the final value of the half wavelength of the cosine wave, and is output from the terminal C. Further, when NX '<MX, NX' becomes smaller as NX sequentially increases. Therefore, in the case of NX <T / 2 described above, the read-only memory ROM is accessed in the reverse order to the case of NX≤MX. To do.

As a result, in the case of MX <NX <T-MX, the output becomes constant, and in the other range, that is, NX <M.
Read-only memory ROM for X, T-MX <NX
The waveform stored in is output.

FIG. 10 shows the waveform diagram. The horizontal axis is time t
And the vertical axis represents the normalized value of the amplitude. When the modulation depth information MX is MX = T / 2, the waveform AX has a waveform MX ″ of MX <T.
It is a waveform in the case of / 2. NX <MX, T-MX <NX
Of the NX values NX1 and NX2 that satisfy the above conditions, the address LX of the read-only memory ROM at that time
1 and LX2 are respectively LX1 = NX1 / MX.T / 2 (6) LX2 = bar NX2 '/ MX.T / 2 (7). Here, NX2 'is the most significant bit N11 of NX2.
It is the value when is set to zero. It is constant when MX <NX <T-MX. The value at this time is the final value of the 1/2 wavelength cosine wave stored in the read-only memory ROM.

FIG. 11 shows the output waveform A and spectrum B when the modulation depth of the above-mentioned operation in the embodiment of the present invention is 25%.
Are shown respectively. In FIG. 11A, the horizontal axis represents time t and the vertical axis represents amplitude. The horizontal axis of B shows the frequency f and the vertical axis shows the amplitude of each frequency. Under this condition, the modulation depth is 100
%, That is, MX = T / 2, a cosine wave is generated, and FIG.
It becomes the waveform and spectrum shown in. However, as shown in FIG. 11, when the modulation depth is less than 100%, a harmonic is generated, and its spectrum is different from the spectrum when the control terminal SAT or the control terminal SQU is set to high level. It does not have higher harmonics such as the 12th, 16th, ...

Although the division circuit is used in the above-described embodiments of the present invention, it is also possible to use a multiplication circuit. Furthermore, various waveforms can be obtained by combining a plurality of waveform generation circuits according to the embodiments of the present invention to synthesize unique waveforms. In the synthesis at this time, various waveforms can be obtained by changing the phase of the fundamental wave. Further, by changing the modulation depth signal, that is, the variable waveform signal with time, it is possible to obtain a signal whose waveform changes correspondingly with time. Therefore, a waveform whose harmonic components change with time can be obtained very easily.

Further, in the embodiment of the present invention, three types, ie, sawtooth wave, rectangular wave, and impulse wave having a basic waveform shape are generated, but it is also possible to generate only one wave. It is possible. Further, in the embodiment of the present invention, the waveform stored in the read-only memory ROM is a cosine wave, but this may be a sine wave or a triangular wave.

[0045]

As described above, the waveform generator of the present invention can control the degree of phase modulation when the waveform is read out according to the magnitude of the modulation signal, and can generate a desired tone color waveform with relatively simple control. Becomes

[Brief description of drawings]

FIG. 1 is a configuration diagram of an embodiment of the present invention.

FIG. 2 is a configuration diagram of the waveform synthesis circuit of FIG.

FIG. 3 is a circuit configuration diagram of a division circuit and a waveform memory of FIG.

FIG. 4 is an explanatory diagram of symbols shown in FIG.

FIG. 5 is a diagram illustrating an example of generated waveforms according to the embodiment of this invention.

FIG. 6 is a diagram showing one output waveform and spectrum according to the embodiment of the present invention.

FIG. 7 is a diagram showing one output waveform and spectrum according to the embodiment of the present invention.

FIG. 8 is a diagram illustrating another example of the generated waveform according to the embodiment of this invention.

FIG. 9 is a diagram showing another output waveform and spectrum according to the embodiment of the present invention.

FIG. 10 is a diagram illustrating another example of the generated waveform according to the embodiment of this invention.

FIG. 11 is a diagram showing another output waveform and spectrum according to the embodiment of the present invention.

[Explanation of symbols]

 4 ... Harmonic control signal generation circuit 6 ... Addition circuit 8 ... Waveform synthesis circuit 9 ... Division circuit 10 ... Waveform memory

Claims (1)

[Claims] 1. Storage means for storing waveform information, and a phase angle corresponding to a frequency of a waveform to be generated and changing at a uniform rate over one cycle of the waveform in order to read the waveform information stored in the storage means. And an address signal generating means for generating an address signal that represents a half of the waveform represented by the waveform information stored in the storage means.
A modulation signal generating means for generating a modulation signal for determining a modulation degree of a phase when the waveform information is read as waveform information expressing a waveform having a distorted phase by determining a period for reading the waveform information of the cycle; A correction for inputting the address signal and the modulation signal, and reading the waveform information of the 1/2 cycle from the storage means while the address signal steps through a period designated by the modulation signal. An address signal is generated, and waveform information of a half cycle of the remaining is generated while the address signal is stepped over at least a part of the remaining period of one cycle excluding the period designated by the modulation signal. Modifying means for generating a modified address signal for reading from the memory means, and accessing the memory means with the modified address signal generated from the modifying means,
A waveform having a frequency determined according to the address signal generated by the address signal generation means and represented by the waveform information stored in the storage means by an amount according to the modulation signal generated from the modulation signal generation means. And an access unit for outputting waveform information representing a waveform having a distorted shape from the waveform generator.