JPS6255793B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a musical tone generation device for an electronic musical instrument in which a waveform is generated by a digital circuit, and in particular, harmonic components vary depending on a modulation signal.

With the advancement of digital technology, it has become possible to generate waveform data using a digital circuit, convert the digital waveform data into an analog signal using a digital-to-analog converter, and generate an analog signal waveform. Waveform generation using such digital circuits is also used in electronic musical instruments, and electronic musical instruments capable of generating waveforms of various tones have been commercialized.

Traditionally, the musical sound generation methods for electronic musical instruments using digital circuits as described above include (a) sine wave synthesis method, and (b)
Variable filter method, (c) waveform memory read method,
(d) There are frequency modulation methods, etc.

The above-mentioned sine wave synthesis method (a) is a method in which a fundamental wave and harmonic sine wave signals are generated by a digital circuit, and the digital waveform signals are synthesized to generate a musical tone with a desired timbre. This method requires channels for calculating the number of types of overtones required in order to obtain a musical tone with a desired overtone composition. Furthermore, when changing the spectrum over time, harmonic control signals for the number of types of overtones are required to vary the amplitude level for each overtone. This method has the problem that the above-mentioned calculation channel and the harmonic control signal require circuits for the number of types of overtones, so the generation circuit becomes large and the generation control of the harmonic control signal becomes complicated.

The variable filter method (b) uses a digital filter, and is a method in which the frequency characteristics of the filter are changed by a harmonic control signal. This method has the problem that the digital filter circuit becomes large. Furthermore, when a waveform is generated at a fixed sampling rate, that is, when the original sound that is input to a digital filter is generated at a fixed sampling rate, it is difficult to obtain a waveform with many harmonics.
Consequently, there is a problem that the effect of the digital filter in the harmonic region is halved. Furthermore, this method has the problem of generating aliasing distortion.

The waveform memory reading method (c) is a method of generating waveforms by sequentially reading out waveform data stored in a memory or the like in advance in accordance with the phase angle. Since the waveform data stored in the aforementioned waveform memory is data of a musical waveform generated as a musical tone, the spectrum of the waveform is fixed. Therefore, in order to change the spectrum, waveform data corresponding to the change in the spectrum must be stored in a memory, and furthermore, a control circuit is required to sequentially read out the data in response to the change in the spectrum. Therefore, this method has the problem of increasing memory capacity and complicating the control circuit. Note that Japanese Patent Laid-Open Publication No. 1983-1989 discloses one development of the waveform memory reading method (c).
Publication No. 61511, Japanese Patent Application Laid-Open No. 1983-61512, Japanese Patent Application Publication No. 1983
-There are publications such as No. 164898. These disclosed technologies switch the frequency information that determines the frequency of a musical tone in the middle of one waveform cycle, and read the waveform (for example, a sine wave) stored in the waveform memory as a distorted waveform. It starts to come out.

However, in this prior art, if you want to change the way the waveform is distorted, you have to change the frequency information appropriately.Moreover, in order to change the way the waveform is distorted without changing the frequency of the generated musical tone, There were problems that needed to be improved, such as the need for complex calculations.

The method (d) applies frequency modulation,
This method uses a carrier wave and a modulating wave, that is, two sine waves, to change the overtones by changing the frequency ratio and modulation depth. Although this method allows overtones to be controlled to some extent, each harmonic changes like a Betzel function, making it difficult to obtain musical tones in which the spectrum envelope changes smoothly.

The present invention was made based on the above-mentioned background, and uses simple control to distort a sine wave or a cosine wave to obtain a waveform like a sawtooth wave, and to adjust the degree of modulation of the phase of the waveform. An object of the present invention is to provide a musical tone generator for an electronic musical instrument that can be set using a modulation signal.

That is, the present invention converts an address signal that changes at a uniform rate over one period of a waveform into a modulated signal from the first phase of one period of a sine wave or a cosine wave using the arithmetic logic of the comparison means and the division means. Specify the phase of 1/2 cycle of the waveform while specifying the phase specified by While specifying the phase, a modified address signal is generated that specifies the phase of the remaining 1/2 period of the waveform, and this modified address signal is used to generate the sine wave or cosine wave stored in the storage means. The distorted waveform described above is obtained by accessing the .

Hereinafter, the present invention will be explained in detail using the drawings.

FIG. 1 is a circuit diagram of an embodiment of the present invention.
FIG. 1 shows an embodiment in which the present invention is applied to an electronic musical instrument. A first output of the keyboard 1 is input to a frequency information generation circuit 2, and a second output is input to a harmonic control signal generation circuit 4 and an envelope control signal generation circuit 5. The output of the frequency information generation circuit 2 is applied to a first input terminal of the phase angle calculation circuit 3. The output of the phase angle calculation circuit 3 is connected to its second input terminal and the waveform synthesis circuit 8.
is connected to input terminal A of. The output of the harmonic control signal generation circuit 4 is connected to a first input terminal of the adder circuit 6. A control signal from another circuit (not shown) is input to the second input terminal of the adder circuit 6. The output of the adder circuit 6 is input to the input terminal B of the waveform synthesis circuit 8. The output terminal C of the waveform synthesis circuit 8 is connected to the first input of the envelope multiplication circuit 7, and the output of the envelope control signal generation circuit 6 is connected to the second input. The output of the envelope multiplication circuit 7 is connected to a digital-to-analog conversion circuit DAC (not shown). The keyboard 1 is a circuit that generates position information of the pressed keys and timing signals of the pressed keys, and the position information of the keys is sent to the frequency information generation circuit 2.
The key timing signal is input to a harmonic control signal generation circuit 4 and an envelope control signal generation circuit 5, respectively. The frequency information generating circuit 2 is a circuit that generates frequency information, that is, phase angle information corresponding to the pressed key from the position information of the pressed key,
For example, phase angle information is sequentially output using a specific clock. The phase angle calculation circuit 3 adds the information applied to the first input terminal and the second input terminal and outputs the sum. Since the output of the phase angle calculation circuit 3 is applied to the second input terminal of the phase angle calculation circuit 3, the phase angle information generated by the frequency information generation circuit 2 is sequentially added to the contents of the phase angle calculation circuit 3 by a specific clock. be done. That is, the phase angle information generated by the frequency information generation circuit 2 is accumulated by the phase angle calculation circuit 3. The accumulation is performed in units of one cycle, and when the phase angle reaches one cycle or more, the phase of one cycle is subtracted. In the embodiment of FIG. 1, for example, 2 ¹² is the phase angle of one period (that is, corresponds to 2π).
When the value exceeds this value, a carry is output, but since the carry is not used, the result is one period's worth of phase angle subtracted. The output of the phase angle calculation circuit 3 is input to the input terminal A of the waveform synthesis circuit 8. The timing signal is input to the harmonic control signal generation circuit 4,
The harmonic control signal generation circuit 4 converts the signal into a tone control signal for changing the harmonic component over time, for example. The output, that is, the timbre control signal, is added in the adder circuit 6 with a control signal from the outside, for example, for changing the timbre by an external operator. The adder circuit 6 can be omitted if no control signal is input from the outside. Addition circuit 6
The output of is applied to the input terminal B of the waveform synthesis circuit 8.
The waveform synthesis circuit 8 is a circuit for accessing the waveform by obtaining a modified address signal whose rate changes over one cycle from a phase angle, that is, an address signal that changes at a uniform rate input from the input terminal A, and accesses the waveform. The rate changes depending on the control signal input from B.

For example, the waveform synthesis circuit 8 includes a division circuit 9 and a waveform memory 10 as shown in FIG. Division circuit 9
divides the phase angle input from input terminal A by the timbre control signal, that is, the harmonic control signal, input from input terminal B in a specific phase angle range, and further divides by a different value in another specific range. make certain movements. That is, the way the phase angle advances in the waveform synthesis circuit 8 is not constant over one cycle, but changes. As a result, the waveform memory 10 in the waveform synthesis circuit 8 is accessed, and the waveform data is outputted from the output terminal C.

Since the memory access at this time is not constant over one cycle but changes within one cycle, waveform data in which the phase of the waveform stored in the waveform memory 10 is distorted is output from the output terminal C.

The timing signal of the keyboard 1 is further input to an envelope control signal generation circuit 5. The envelope control signal generation circuit 5 generates control data for changing the amplitude of the musical tone to be output. The output, ie, the envelope signal, is input to an envelope multiplier circuit 7. On the other hand, the waveform data output from the output terminal C of the waveform synthesis circuit 8 is transmitted to the envelope multiplication circuit 7.
The envelope multiplication circuit 7 multiplies the waveform data and the envelope signal and outputs the result.

FIG. 3 is a first circuit diagram showing the waveform synthesis circuit 8 of FIG. 2 in detail. Input terminal N corresponds to input terminal A in FIGS. 1 and 2, and input terminal M corresponds to input terminal B, respectively. That is, the output of the phase angle calculation circuit 3 shown in FIG. 1, for example, 12-bit phase angle data N ₀ to N ₁₁ is input to the input terminal N, and the input terminal M
For example, 12-bit modulation depth data M ₀ to M ₁₁ from the adder circuit 6 in FIG. Input terminal N
is the comparator COMP and the exclusive logical OR group
Input to divider DIV via EOR ₁ . Each bit N ₀ to _{N 11} of the input terminal N is input corresponding to each bit A ₀ to _{A 11} of the comparator COMP, but the divider
In DIV, each bit _N1 to _N11 is input to each bit _A0 to _A10 . Further, bit _A11 of the divider DIV is grounded.

In addition, the exclusive logical OR group EOR ₁ in Figure 3
~EOR ₃ consists of a plurality of input exclusive logical OR groups, and as shown in FIG. 4, each symbol a has a structure as shown in b.

Input terminal M consists of 11 bits and is a comparator.
COMP and is input to the divider DIV via the exclusive OR group EOR ₂ .

Each bit _M0 to _M10 of input terminal M is a comparator.
Each bit B ₀ to _{B 10} of COMP is inputted corresponding to each bit B ₀ to _{B 10} of the divider DIV. Bit B ₁₁ of the comparator COMP is grounded and the divider
Exclusive logical OR group corresponding to bit B ₁₁ of DIV
The input of EOR ₂ is also grounded.

The comparison output OUT of the comparator COMP is input to exclusive logical OR groups EOR ₁ to _{EOR 3} . The output of the divider DIV is input to the read-only memory ROM via the exclusive OR group EOR ₃ , and the output of the divider DIV
The bits D ₀ to _{D 11} are input corresponding to the bits A ₀ to _{A 11} of the read-only memory ROM. Outputs _O0 to _O10 of the read-only memory ROM are connected to output terminal C.

Therefore, the data input from input terminal N and the data input from input terminal M are connected to a comparator.
COMP compares those values. When the value of data input from input terminal N is greater than the value of data input from input terminal M, a high level is output from comparison output OUT. That is, at this time, the exclusive OR groups EOR ₁ to EOR ₃ operate as inverters. Conversely, when the value of data input from input terminal N is smaller than the value of data input from input terminal M, a low level is output from comparison output OUT, and exclusive logical OR groups EOR ₁ to EOR ₃ are output as buffers. Operate.
Since the data value inputted from the input terminal N is the result of accumulation of phase angle values, the value changes linearly from small to large. Then, after a certain value, ie, the maximum, that value becomes the minimum value again, and this operation is repeated.
In this one movement, when changing from small to large,
The output of the comparator COMP changes from low level to high level. By this change divider DIV
The polarity of the input data is reversed. Also a divider
The polarity of the DIV output is also reversed. The output, that is, the output of the exclusive OR group EOR ₃ , is input to the read-only memory ROM, and the cosine waveform is stored in the read-only memory ROM, so the waveforms sequentially output from the read-only memory ROM are It is a temporally distorted cosine wave.

FIG. 5 shows the waveform diagram. The horizontal axis represents time t,
The vertical axis indicates the normalized value of amplitude. When the modulation depth information MX is MX=T/2, the waveform AX is the waveform BX.
<T/2, where T represents one period of the waveform. In this operation, the comparator
Since the value input to the divider DIV changes depending on the comparison result of COMP, one period will be explained by dividing it into two conditions.

If NX≦MX, read-only memory
It operates so that the length of 1/2 period of the cosine wave stored in the ROM becomes the modulation depth information MX. In other words, for the phase angle address value NX ₁ under this condition, the phase angle address value LX ₁ after the calculation is LX ₁ = (NX ₁ /MX)・T/2 ......(1) Become. Note that the divider DIV is a binary operation and the period is a power of 2, so in the embodiment of the present invention shown in FIG. 3, especially (1)
Although it is not multiplied by T/2 on the right side of the equation, the output of the divider DIV is the value below the decimal point, and the output D ₁₁
is the first decimal place in binary, and the output _D10 is the second decimal place in binary, and that value is used as the address, so the result is equivalently multiplied by T. Furthermore, each bit N ₁₁ to _{N 1} of the input terminal N is input to each bit A ₁₀ to _{A 22} of the divider DIV, and since the low level is input (grounded) to bit A ₁₁ , it is 1/2 at the time of input. The structure is multiplied by . In other words, the result is a division configuration in which the input and output of the divider is multiplied by 1/2.

If NX > MX, read-only memory
It operates so that the length of the remaining 1/2 period of the cosine wave stored in the ROM becomes the length of T-MX. That is, for the modulation depth information MX and phase angle address value NX ₂ under these conditions, the phase angle address value LX ₂ after calculation at this time is T-LX ₂ = (T-NX ₂ )/(T-MX )・T/2
......(2) is satisfied.

Here, one period T is a power of this, so T-
MX=, T-NX ₂ = ₂ , T-LX ₂ = ₂ , and the phase angle address value LX ₂ after the calculation is expressed as LX ₂ =( ₂ /)·T/2 (3). Here, the symbol - above the symbol indicates each inverted signal. The calculation of equation (3) will be performed in this waveform synthesis circuit 8.

By the way, the output of the divider DIV changes from 0 to 0.5 when NX≦MX. Also, when NX > MX, it is 0.5
It changes from 0 to 0. The result is read-only memory
Since the waveform stored in the ROM is a cosine wave, there is a read-only memory for when the output of the divider DIV is inverted and when it is not inverted.
No change in ROM output, exclusive logical OR group
Read-only memory ROM except for EOR ₃
The contents of are read twice each over only half a period of the cosine wave. i.e. comparator
The output of the divider DIV is an exclusive logical OR group by the comparison symbol output from the comparison output OUT of COMP.
No need to invert with EOR ₃ .

The circuit diagram of the second embodiment of the present invention shown in FIG. 6 is an application of the above-described operation, and the same operational output is obtained even without the exclusive logical OR group EOR ₃ shown in FIG. At this time, each bit N ₁₁ to _{N 0} of the input terminal N is input to each bit A ₁₁ to _{A 0} of the divider DIV, so it is compared with the first embodiment of the present invention shown in FIG. 3 described above. Then, the input value will be doubled. However, compared to the embodiment of the present invention shown in FIG. 3, the output of the divider DIV is shifted one bit lower and inputted to the address of the read-only memory ROM. That is, each bit D ₁₁ -D ₁ is added to each bit A ₁₀ -A ₀ of the read-only memory ROM. This is equivalently the same as multiplying by 1/2 as described above. In this way, the read-only memory shown in Figure 6
The storage capacity of ROM is read-only memory as shown in Figure 5.
This is half the storage capacity of ROM. This is because it is sufficient to store only a half cycle of a cosine wave as waveform data in the read-only memory ROM.

Figure 7 shows the read-only memory in Figure 6.
FIG. 4 is a circuit diagram of a read-only memory ROM section when changing the storage waveform of the ROM. As shown in the figure, the first half of the read-only memory ROM at this time stores 1/4 period cosine wave data, and the second half stores the polarity inverted data of the 1/4 period cosine wave. This polarity reversal is equivalently accomplished by inverting the upper bit _D11 of the divider DIV by the exclusive OR group _EOR4 and further inputting it to the adder circuit ADD. read only memory
During the latter quarter period of the ROM, the most significant bit _D11 of the divider DIV goes high, and is input to the most significant bit _A10 of the adder circuit ADD, the carry input C _iN , and the exclusive OR group EOR ₄ . Therefore, the output of the read-only memory ROM is inverted, that is, the polarity is reversed, using the exclusive OR group EOR ₄ , and the amplitude value is equivalently shifted by 1/2 of the amplitude of the cosine wave using the adder circuit ADD. This is the same as the output of the read-only memory ROM in FIG. This means that there are fewer upper bits of memory, so its capacity is reduced.

Figures 8 to 11 show MX = (1/2)・T, (1/4)・
The waveform a and its spectrum b at T, (1/8)・T, and (1/16)・T are shown. The horizontal axis of a in FIGS. 8 to 11 indicates time t, and the vertical axis indicates amplitude.
In FIGS. 8 to 11b, the horizontal axis shows the frequency f, and the vertical axis shows the amplitude of each frequency.

Note that MX=(1/2)T is the modulation depth of 100%. Here, the smaller the modulation depth, the more the waveform becomes a sawtooth waveform, and the spectrum thereof becomes a waveform containing more harmonics. In other words, the spectrum changes smoothly according to changes in the value of MX. Therefore, by changing the value of MX over time, it is possible to obtain a timbre change similar to that obtained when a low-pass filter whose cutoff frequency changes over time is applied to the sawtooth wave voltage in an analog synthesizer. Can be done.

In an embodiment of the present invention, a read-only memory
Although the ROM is a one-cycle or one-half cycle of a cosine wave, it may of course store a one-fourth cycle waveform, and may also store other waveforms other than the cosine wave.

Further, although a division circuit is used in the embodiment of the present invention, this may be a multiplication circuit or the like having a function of calculating. Furthermore, in embodiments of the present invention
Although MX is explained below T/2, MX is T/
It is also possible to use two or more.

As described above, according to the present invention, it is possible to generate a waveform whose spectrum envelope changes smoothly using a simple digital circuit. Furthermore, it is possible to obtain a waveform in which high-order harmonics of the sawtooth wave are removed. Furthermore, by temporally changing the change in the high frequency component, it is also possible to generate a musical tone having a unique timbre.

[Brief explanation of the drawing]

Fig. 1 is a block diagram of an embodiment of the present invention, Fig. 2 is a block diagram of the waveform synthesis circuit in Fig. 1, and Figs. 3, 6, and 7 are the main parts shown in Fig. 1. A circuit configuration diagram, FIG. 4 is an explanatory diagram of symbols in FIGS. 3, 6, and 7, FIG. 5 is an output waveform diagram, and FIGS. 8 to 11a are output waveforms according to embodiments of the present invention. Figure 5b is a spectrum diagram thereof. 4... Harmonic control signal generation circuit, 6... Addition circuit, 8... Waveform synthesis circuit, 9... Division circuit, 10
... Waveform memory, EOR ₁ to EOR ₄ ... Exclusive logical OR group, DIV ... Divider, COMP ... Comparator, ROM ... Read-only memory.

Claims (1)

[Scope of Claims] 1. A storage means for storing waveform information representing at least a part of a sine wave or a cosine wave, and a musical sound waveform to be generated in order to read out the waveform information stored in the storage means. address signal generation means for generating an address signal that corresponds to the frequency of the waveform and changes at a uniform rate over one cycle of the waveform; and reading out the waveform information stored in the storage means as waveform information representing a distorted waveform. a modulation signal generation means that generates a modulation signal that determines the degree of phase modulation at the time; and comparing the address signal generated from the address signal generation means and the modulation signal generated from the modulation signal generation means. Comparing means; According to the comparison result output of the comparing means, either the address signal or its inverted level signal is applied to one end, and either the modulated signal or its inverted level signal is applied. a dividing means applied to the other end and configured to obtain a modified address signal from its output terminal by dividing the input signal to the one end by the input signal to the other end; and the modification outputted from the dividing means. means for reading out waveform information representing the distorted waveform by accessing the storage means in accordance with an address signal, and the modified address signal is configured such that the address signal is one of the sine wave or cosine wave. While specifying the phase from the first phase of one period to the phase specified by the modulation signal, specifying the phase of 1/2 period of the waveform,
and that the address signal specifies the phase of the remaining 1/2 cycle of the waveform while specifying the phase specified by the modulation signal to the final phase of one cycle of the waveform. Characteristic musical tone generator for electronic musical instruments. 2. The musical tone generating device for an electronic musical instrument according to claim 1, wherein the modulation signal generating means generates the modulation signal that changes over time. 3. Claims characterized in that the address signal generating means outputs phase angle information specifying the phase angle of the waveform as the address signal at a uniform rate corresponding to the frequency of the waveform to be generated. The musical tone generating device for an electronic musical instrument according to item 1 or 2.