JPH07322204A - Image coding recording and reproducing device - Google Patents

Abstract

PURPOSE:To obtain the image coding recording and reproducing device with excellent image quality in the usual reproduction mode by decoding coded data with addition of a few additional information or a circuit of simple configuration even in the case for controlling a code quantity over a wide range. CONSTITUTION:Coded data from a 1st bit to, e.g. 28-th bit are written in addresses corresponding to a small area in a low frequency SYNC block in a RAM 13 as 1st data and coded data of 29th and succeeding bits are written in a buffer memory 10. Then the data read from the memory 10 are written in addresses of the RAM 13 corresponding to an idle area of the small area and a high frequency SYNC block. In the case of the reproduction, low frequency SYNC block coded data are read from a RAM 21 as a preprocessing of variable length decoding, and an end location of coded data in a macro block recorded in each small area is detected by an END detection section 23. Then the coded data are subject to inverse quantization at an inverse quantization section 26 based on a quantization parameter detected by a quantization parameter detection section 20, the result is subject to inverse DCT processing and inverse block processing and then a digital video signal is outputted from an output terminal 29.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an image encoding / recording / reproducing apparatus for compressing a video signal of a television or the like and recording it on a VTR or the like.

[0002]

2. Description of the Related Art Variable length coding is generally performed as a method of efficiently compressing information of a digitized image signal. Variable length coding causes distortion due to coding by giving a short code to data with a high probability of occurrence before coding and giving a long code to data with a low probability of occurrence. It is intended to reduce the average code amount without doing so.

Since a digital VTR records in fixed-length sync block units, it is necessary to divide variable-length codes into fixed lengths in order to record a signal compressed by variable-length coding. Therefore, when the variable-length code is simply recorded continuously, it cannot be decoded at the time of reproduction unless it is decoded one code at a time from the beginning of the encoded data.
Therefore, if the decoding of one code fails due to an error even in one bit, it becomes impossible to decode all the data from that point onward. In addition, since sync blocks are reproduced intermittently during search, when data of variable-length code is divided and arranged in sync blocks regardless of code boundaries, all blocks other than the sync block including the beginning of encoded data are decoded. It is impossible to obtain a stable search image.

[0004] For example, the Technical Report Vol. 16, No. 35, pp. In the conventional image coding / recording / reproducing apparatus shown by Nos. 7 to 12, when the DCT is performed for each transform block obtained by blocking the image signal and the variable-length coding is performed, the coding of a plurality of transform blocks is performed. The unit is a macroblock, and the variable length coding is performed by controlling the variable amount such that the code amount for each of the M macroblocks is equal to or less than M times the inner data length in the error correction product code. D of encoded data after encoding is stored in a separate inner data storage area for each macroblock.
Store from C and low frequency components.

At this time, the high frequency component of the macroblock whose code amount is larger than the inner data length and cannot be stored in the inner data storage region is replaced by the empty region of the inner data storage region in which the macroblock having the small code amount is stored. To store. At the time of decoding, decoding is performed for each inner data unit in advance for each code amount control range, the location of the empty area is detected, and then decoding is performed for each macroblock to obtain original data. In this method, D for each macroblock
Since the recording locations of the C component and the low-frequency component are fixed, error propagation is completed in one macroblock for the low-frequency component, and the variable-length code packing unit for the high-frequency component is completed in M macroblocks. It can be suppressed within a macroblock. Further, by forming a sync block with a plurality of inner data, the DC and low frequency components of the macro block are decoded in units of inner data in the reproduced sync block even during a search, and a search image can be obtained.

[0006]

Generally, the larger the code amount control range is, the more optimal the bit allocation to each macroblock is, so that the image quality is improved.

However, in the above-mentioned conventional image encoding / recording / reproducing apparatus, when the code amount control range is enlarged, the data recorded in the data recording area of another macro block is recorded with respect to the macro block having a large code amount. Since the amount of data that must be decoded in advance to detect the location increases, the circuit size and the processing time increase. Therefore, the code amount control range cannot be increased so much, and as a result, there is a problem that the image quality during normal reproduction deteriorates.

It is an object of the present invention to provide an image coding / recording / reproducing apparatus which is excellent in normal reproduction image quality without increasing the circuit scale and processing time.

[0009]

In the image coding recording / reproducing apparatus of the present invention, firstly, a sync block for recording coded data includes a low frequency sync block for storing low frequency data and a high frequency data. A high-frequency sync block to be stored, and means for performing variable-length coding in order from the low-frequency transform coefficient for each macroblock consisting of one or a plurality of transform blocks, and one for every M macroblocks. A low-pass sync block is allocated, the data region of the low-pass sync block is divided into M small regions every N bits, and N bits when the code amount is N bits or more for each of the M macro blocks. Up to the eye, when the code amount is less than N bits, means for storing all the encoded data as the first data in the corresponding one small area in order from the beginning of the encoded data of the macroblock. The coded data other than the first data among the coded data of the M macroblocks is stored in the empty area generated when the code amount of the macroblocks is less than N bits in the M subareas. Means for storing the data as second data, and means for storing data other than the first data and the second data in the encoded data of the M macroblocks as third data in the high frequency sync block. And a means for recording the data stored in each sync block in sync block units.

Secondly, a means for performing variable length coding in order from the low-frequency transform coefficient for each macroblock consisting of one or a plurality of transform blocks, and one for each macroblock. When a sync block is assigned and the code amount of the macro block is N bits or more, up to the N-th bit, and when the code amount of the macro block is less than N bits, all coded data is used as the first data to code the macro block Means for sequentially recording the encoded data in the sync block from the beginning, and encoded data other than the first data in the encoded data of the macro block in units of a plurality of sync blocks storing the first data. As the second data, in each sync block assigned to the plurality of macroblocks, the code amount of the macroblock is N bits or less. And a 1-bit marker information indicating, for each macroblock, whether or not the encoded data of the macroblock is composed of only the first data, A recording unit having a unit for storing the sync block at a predetermined position, a unit for recording the data of the sync block in units of sync block, a unit for detecting the marker information, and encoded data of the macro block The first
And a decoding unit that first decodes a macroblock that is composed of only the above data.

[0011]

With the first configuration, in each macroblock, the low-frequency encoded data is recorded in the predetermined low-frequency sync block, and the high-frequency encoded data is sequentially recorded in the high-frequency sync block. Therefore, only one low-frequency sync block needs to be decoded as a pre-process for decoding the variable-length code. Further, according to the second configuration, by decoding the macro block, which is represented by the marker information and whose encoded data is composed only of the first data, first, the second block can be obtained without performing the decoding process as the pre-process. Since the place where the data is recorded can be detected, all the encoded data can be decoded. Therefore, even when the code amount control is performed over a wide range, the decoding processing circuit can be realized with the same circuit scale as when the code amount control is performed in units of several macro blocks.

[0012]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS Each embodiment of the image encoding / recording / reproducing apparatus of the present invention will be described below with reference to FIGS.

1 to 4 show a first embodiment. In FIG. 1, 1 is a digital video signal input terminal, 2 is a blocking circuit, 3 is a DCT processing circuit, 4 is a code amount control circuit,
5 is a quantization circuit, 6 is a variable length coding circuit, 7 is a packing circuit, 8 is a code amount counter, 9 is a first memory control circuit, 10 is a first buffer memory, 11 is a second buffer memory, 12 is a boundary information generation circuit, 13 is the first RA
M and 14 are recording signal processing circuits, 15 is a recording head, and 16
Is a recording medium, 17 is a reproducing head, 18 is a reproduction signal processing circuit, 19 is a boundary information detecting circuit, 20 is a quantization parameter detecting circuit, 21 is a second RAM, 22 is a second memory control circuit, and 23 is END. A detection circuit, 24 a variable length decoding circuit, 25 an inverse packing circuit, 26 an inverse quantization circuit, 2
7 is an inverse DCT processing circuit, 28 is an inverse blocking circuit, 29
Is a digital video signal output terminal, and 30 is a reproduction control signal input terminal. The operation of the image coding / recording / reproducing apparatus of the first embodiment configured as described above will be described. In the present embodiment, the input signal is a luminance signal "Y" of 720 pixels horizontally and 256 pixels vertically for one field.
For the color difference signals "Pb, Pr", a 4: 2: 2 component signal of half the sampling is used. Also, 1
The video signal of the field is divided into two channels, and is quantized with a quantization parameter such that the code amount is equal to or less than a predetermined code amount for each channel, and then variable-length coded and recorded. The video signal recording area of one channel is composed of 1152 sync blocks, and the size of the data area in one sync block is 86 bytes. The processing of one channel will be described below.

In the blocking circuit 2, the input 4: 2: 2 component signal is output independently of Y, Pb, and Pr.
The line is divided into DCT blocks of every 8 pixels. Therefore, the video signal of one field is per channel, the Y signal is 1440DCT block, and the Pb and Pr signals are 7 each.
It is divided into 20 DCT blocks. In addition, Y signal 2DCT blocks (Y0, Y
1) and the Pb and Pr signals corresponding to the same position as that of 1 DCT block are grouped into one macro block. That is, one channel is composed of 720 macroblocks.

In the DCT processing circuit 3, DCT processing is performed for each DCT block. The code amount control circuit 4 first predicts the initial value of the quantization parameter such that the code amount per channel becomes equal to or less than the target code amount by using the data sampled from the DCT coefficient data for one field. After that, the code amount after variable length coding is monitored, and the quantization parameter is appropriately changed so as not to exceed the target code amount. The quantization circuit 5 quantizes the DCT coefficient data based on the selected quantization parameter. The variable-length coding circuit 6 performs zigzag scanning on the quantized coefficient data for each DCT block and arranges them in order from the low frequency region as shown in FIG. It is converted into a variable length code by two-dimensional Huffman coding in which one code is assigned to a value. In the packing circuit 7, Y0, Y1, coded in order from the low frequency component
With respect to the variable length coded data of 4 DCT blocks of Pb and Pr, one code is taken out in the order of Y0, Y1, Pb, Pr, Y0, ... And arranged, and then divided into 1 byte units and output. FIG. 3 shows an example of the variable length coding result of each DCT block and the data packing result in that case.

In FIG. 3, a0, ..., A7 is Y0.
, B6 are Y1 coding results, c0, ..., C4 are Pb coding results, d0 ,.
..., d3 are the coding results of Pr, and the respective heights represent the code length. Since variable-length coding processing is performed by two-dimensional Huffman coding, as shown in FIG.
The number of codes and the code length differ depending on the CT block. In this case, for each conversion block, one code is extracted from the low frequency band and rearranged. That is, a0, b0, c0, d
Data packing is performed in the order of 0, a1, b1, ..., B6, a7. Here, the code amount of one macroblock is 1
Dummy data of 1 byte or less is added to the end of the data string so that it becomes an integral multiple of bytes.

With respect to the coded data of the macroblocks packed as shown in FIG. 3, lowband data of three macroblocks are recorded in one sync block. FIG. 4 shows a sync block 1152 for recording a video signal for one channel.
The data storage area in each piece is shown. In FIG. 4, SB
1 to SB240 are low-frequency sync blocks, and SB241 to S241.
B1152 is a high frequency sync block. The quantization parameter is set to 7 bits and recorded in each low frequency sync block. Also, boundary information indicating the head position of the data recorded in the high frequency sync block is recorded for every 9 macro blocks. Since the encoded data is recorded in byte units, the boundary information indicates an address in byte units in the video data recording area. Video data recording area is 1152.8
Since it is 6 bytes, the boundary information has 17 bits. The boundary information is recorded in two sync blocks. Also,
The data recording area of the low-frequency sync block is divided into small areas of 28 bytes, and the low-frequency encoded data of one macroblock is recorded. In FIG. 4, 31 is a quantization parameter and 32 is boundary information.

In the encoded data output from the packing circuit 7 for each macroblock, the code amount is counted by the code amount counter 8, and the first to the 28th bit from the beginning are counted.
Data is written in an address corresponding to a small area in a predetermined low-frequency sync block on the first RAM 13, and the coded data of the 29th and subsequent bits is temporarily written in the first buffer memory 10. When the coding amount of the macro block is less than 28 bits, all the coded data is written in the small area in the sync block, and the address of the empty area in which the coded data is not recorded is temporarily stored in the second buffer. Write to the memory 11. After the processing of 3 macroblocks is completed, the address data of the free area is read from the second buffer memory 11, and the encoded data read from the first buffer memory 10 is transferred to the empty area of the low-frequency sync block as a second area. Write as data. The free space is full, or the second buffer memory 1
If the address data is not written in 1, the encoded data written in the first buffer memory 10 is sequentially written as the third data in the address corresponding to the high frequency sync block in the first RAM 13. .
Further, the boundary information generation circuit 12 generates an address on the first RAM 13 in which the first byte data of the encoded data recorded in the high-frequency sync block for every 9 macro blocks is generated, and is set to a predetermined address. Store. First and second buffer memories 10 and 11 and first RAM 13
Is controlled by the first memory control circuit 9.

FIG. 4 shows the encoded data written in the low frequency sync block and the high frequency sync block by the above processing. In FIG. 4, 33 is low-frequency data (first data) for each macroblock, 34 is coded data (second data) written in an empty area, and 35 is high-frequency data (third data). is there. The encoded data for one field, the quantization parameter, and the boundary information are the first R
After being written in the AM 13, the data is read, the recording signal processing circuit 14 adds the synchronization code, the ID, the error correction code, and the recording modulation process, and records the data on the recording medium 16 via the recording head 15.

At the time of reproduction, a reproduction signal processing circuit 18 performs reproduction signal processing such as reproduction equalization, demodulation and error correction from the signal reproduced through the reproduction head 17. The encoded data subjected to the reproduction processing is written in the second RAM 21. The boundary information detection circuit 19 detects the boundary information recorded for every two sync blocks. The quantization parameter detection circuit 20 detects the quantization parameter recorded in each sync block. The decoding process is also performed in units of 3 macroblocks as in the encoding process. First, as pre-processing for variable length decoding,
The encoded data of one low-frequency sync block is read from the second RAM 21, and the end position of the encoded data of the macroblock recorded in each small area is detected by the END detection circuit 23. After detection of the end location, the variable length decoding circuit 24 decodes one macro block at a time. First, the 28-byte encoded data, that is, the first data, written in each small area in the low-frequency sync block is decoded. If it is not possible to decode up to the last data of the macroblock using this first data, the data after the end point in each small area of the low-frequency sync block, that is, the second data
And the data of the high frequency sync block, that is, the third data are read from the second RAM 21 and the decoding is continued. The reading control of the second RAM 21 is performed by the second memory control circuit 22. With respect to the data decoded for each macro block, the inverse packing circuit 25 rearranges the data for each DCT block. The inverse quantization circuit 26 performs inverse quantization on the basis of the quantization parameter detected by the quantization parameter detection circuit 20, performs inverse DCT and inverse blocking, and then outputs from the digital video signal output terminal 29.

At the time of search, the reproduction control signal input terminal 30
A signal indicating that the search reproduction is performed is input, and the search image is reproduced by decoding using only the data of the low frequency sync block.

Even when an error occurs, it is possible to detect boundary information within 1 macroblock in the low frequency data recorded in the low frequency sync block and in the high frequency data recorded in the high frequency sync block. Causes error propagation to stop within 9 macroblocks.

Even when the code amount control is performed over a wide range in this way, the range that needs to be decoded as the preprocessing of the decoding process is several macroblocks. Therefore, when the code amount control is performed in units of several macroblocks. A decoding circuit can be realized with the same circuit scale as

FIG. 5 shows another embodiment of the encoded data written in the low frequency sync block and the high frequency sync block. The structure of the image encoding / recording / reproducing apparatus of the second embodiment is the same as that of the first embodiment shown in FIG. This second
Also in this embodiment, the same input signal as in the first embodiment is used, and the code amount is controlled for each 720 sync blocks per channel, and 1152 sync blocks of 86 bytes are recorded.

In FIG. 5, SB1 to SB240 are low frequency sync blocks, and SB241 to SB1152 are high frequency sync blocks. In the low frequency sync block, low frequency encoded data of 3 macro blocks is recorded. The quantization parameter is set to 7 bits and recorded in each low frequency sync block. Also, 17-bit boundary information indicating the head position of the data recorded in the high frequency sync block is recorded for every 9 macro blocks. Reference numeral 31 is a quantization parameter, and 32 is boundary information.

In the encoded data output from the packing circuit 7 for each macroblock, the code amount counter is applied to the Lth macroblock among the three macroblocks recorded in one low-frequency sync block. In step 8, the cumulative amount of encoded data recorded in the low-frequency sync block is calculated, and stored as first data in an address corresponding to a predetermined low-frequency sync block on the first RAM 13 until L · 28 bytes. , And the subsequent encoded data are temporarily written in the first buffer memory 10. If all the encoded data of the third macroblock can be stored in the low-frequency sync block before the accumulated code amount reaches 3.28 bytes, the encoded data read from the first buffer memory 10 is accumulated. Store until the code amount reaches 3.28 bytes. That is, one low-frequency sync block is recorded in the empty area after recording the low-frequency components of three macro blocks. The data recorded in this empty area is referred to as second data. If the data area of the low-frequency sync block is full,
The remaining encoded data stored in the first buffer memory 10 is converted into the first RA corresponding to the high frequency sync block.
The third data is sequentially stored at the address on M13. Also, for every 6 macroblocks, 1 of the encoded data recorded in the high frequency sync block, that is, the 3rd data
An address on the first RAM 13 in which the byte data is written is generated by the boundary information generation circuit 12 and stored at a predetermined address. Reference numeral 33 is low-frequency data (first data) for each macroblock, 34 is encoded data (second data) written in an empty area, and 35 is high-frequency data (third data).
Data).

The decoding process at the time of reproduction is also performed in units of 3 macroblocks as in the encoding process. First, as preprocessing for variable-length decoding, the encoded data of one low-frequency component recording sync block is read from the second RAM 21, and the END detection circuit 23 detects the end location of the encoded data of the third macroblock. To do. After detecting the end location, the variable length decoding circuit 24
Then, decoding is performed one macroblock at a time. First, the first data recorded in the low frequency component recording sync block is decoded. If the last data of the macroblock cannot be decoded using this data, the second data recorded after the end location in the low frequency component recording sync block and the high frequency component recording sync block are recorded. The read third data is read from the second RAM 21 and decoded. The decoded data is subjected to inverse quantization, inverse DCT and inverse blocking, and output from the digital video signal output terminal 29.

At the time of search, the reproduction control signal input terminal 30
A signal indicating that the search reproduction is performed is input, and the search image is reproduced by decoding using only the data of the low frequency sync block.

Even when the code amount control is performed over a wide range in this way, the range that needs to be decoded as the preprocessing of the decoding processing is several macroblocks, and the place to be detected by the preprocessing is one sync block. Because it is good in the place,
A decoding circuit can be realized with a simple configuration.

In the second embodiment, the data can be stored in units of a plurality of low frequency sync blocks. That is, the second data to be written in the empty area for each of the K low-pass sync blocks is the first of the K · 3 macroblocks assigned to the K low-pass sync blocks.
Coded data other than the above data. In addition, the coded data temporarily written in the first buffer memory 10 is K · 3 coded data for each macroblock, and the second buffer memory 11 stores the positions of the empty areas in the K low-frequency sync blocks. Write temporarily. And on the playback side, EN
The D detection circuit 23 detects the position of the empty area for each of the K low-frequency sync blocks. In this case, the probability that no data will be written in the empty area becomes small. That is, when data is stored in units of one low-frequency sync block, the sum of the code amounts of 3 macroblocks is 28.
If the size is 3 bytes or less, no data is written in the empty area, and if the data is stored in units of K low-pass sync blocks, the sum of the code amounts of K3 macroblocks is K-28.3 bytes. In the following cases, no data is written in the empty area, and the probability of occurrence of the empty area in which no data is written can be reduced due to the deviation of the code amount due to the local feature of the image.

FIG. 6 shows an image coding / recording / reproducing apparatus of the third embodiment. The same components as those in FIG. 1 are designated by the same reference numerals and detailed description thereof will be omitted. In FIG. 6, 36
Is a first memory control circuit, 37 is a first buffer memory, 38 is a second buffer memory, 39 is a marker information generation circuit, 40 is a first RAM, 41 is a second RAM,
42 is a marker information detection circuit, 43 is a third buffer memory, 44 is a second memory control circuit, and 45 is a third RA.
M and 46 are third memory control circuits.

In this embodiment, as in the first embodiment, the input signal for one field is a luminance signal of 720 pixels in the horizontal direction, and a 4: 2: 2 component signal consisting of 256 lines in the vertical direction, and a 720 sync signal. The video signal of one field is divided into two channels and is recorded with the code amount controlled for each channel. However, the video signal recording area of one channel consists of 720 sync blocks, and the size of the data area in one sync block is 136 bytes. FIG. 7 shows a data storage area in 720 sync blocks for recording a video signal for one channel. The 7-bit quantization parameter is obtained for each sync block, and the 17-bit boundary information is obtained for every 4 sync blocks, and recorded in 3 sync blocks. Further, for each sync block, 1-bit marker information indicating whether or not the code amount of the macro block assigned to the sync block is larger than the coded data recording area of the sync block is recorded. In FIG. 7, 31 is a quantization parameter, 47 is marker information, and 32 is boundary information. The size of the encoded data recording area is 134 bytes per sync block. The processing of one channel will be described below.

The operation of the third embodiment constructed as shown in FIG. 6 will be described. Similar to the first embodiment, the packing circuit 7 is added to the output from the variable length coding circuit 6.
Then, data packing as shown in FIG. 3 is performed for each macro block. The code amount counter 8 obtains the code amount for each macro block in byte units. For each macroblock, the encoded data from the beginning to the 134th byte is written as first data at an address on the first RAM 40 corresponding to a predetermined sync block. When the code amount of the macroblock is 135 bytes or more, the data of the 135th byte and thereafter is temporarily written in the first buffer memory 37. If the code amount is less than 134 bytes, the start address of the empty area generated in the sync block is written in the second buffer memory 38. First buffer memory 37
The encoded data written in the second buffer memory 38 is stored as the second data in the empty area based on the address of the empty area written in the second buffer memory 38. The marker generation circuit 39 generates "1" for a macro block having a code amount of less than 135 bytes and "0" for a macro block having a code amount of 135 bytes or more. Also,
The quantization parameter and the boundary information are written in a predetermined address of the first RAM 40. The encoded data written in the sync block by the above processing is shown in FIG. 48 is the first data and 49 is the second data.
First and second buffer memories 37 and 38 and first R
The first memory control circuit 36 controls the AM 40. After reading the data from the first RAM 40, recording signal processing is performed and the data is recorded in the recording medium 16.

At the time of reproduction, the data after the reproduction processing is written in the second RAM 41. In the marker information detection circuit 42, the marker information is “1”, that is, the code amount is 135.
Detect macroblocks less than bytes. The sync block recording the detected macroblock is read first by R
The data is read from the AM 39, and the variable length decoding circuit 23 decodes the variable length code recorded as the first data in the sync block one macro block at a time. Every time one macroblock indicated by the marker information “1” is decoded,
Read address of the second RAM 41 at the end of decoding,
That is, the start address of the place where the second data is recorded is temporarily written in the third buffer memory 43. After the decoding of the macro block indicated by the marker information “1” is completed, the macro block indicated by the marker information “0” is decoded. First, 135 bytes of the first data recorded in a predetermined sync block is decoded, and then the data after the 136th byte from the boundary information and the address stored in the third buffer memory 43, that is, the second data. , The data is read from the second RAM 41 and decoded. The second RAM 41 and the third buffer memory 43 are controlled by the second memory control circuit 44.
Done in. After decoding, the data is depacked and dequantized, and then written in the third RAM 45. The reading from the third RAM 45 is controlled by the third memory control circuit 46 so that the data is output in the order. The data read from the third RAM 45 is subjected to inverse DCT processing and inverse blocking processing, and is output from the digital video signal output terminal 29.

At the time of search, the reproduction control signal input terminal 30
Input a signal that indicates search playback. In this case, the marker image is not detected and only the data in each sync block is decoded to obtain the search image.

In this way, one sync block is assigned to the coded data of one macroblock, the coded data of each macroblock is recorded in each sync block from the low frequency band, and the code of the macroblock having a large code amount is coded. When the encoded data is recorded in the empty area of the sync block assigned to the macro block having a small code amount, the marker information indicating the macro block whose code amount is smaller than the size of the encoded data recording area in the sync block is recorded,
At the time of reproduction, by decoding the macro block indicated by the marker information first, the recording location of the encoded data recorded in the other sync block can be detected with a small amount of additional information and an additional circuit with a simple configuration, and the decoding can be performed. can do.

In this embodiment, one sync block has one
Although the case of allocating macroblocks is shown, it is clear that the same effect can be obtained by recording the marker information for each macroblock even when a plurality of macroblocks are allocated.

It should be noted that although data is stored in byte units in all the embodiments, it is obvious that data can also be stored in bit units. In this case, dummy data becomes unnecessary and recording efficiency can be improved.

Data packing for each macroblock is performed in order from the data indicating the low frequency component of each block, so that Y0, Y1, Pb of one macroblock,
Since the low-frequency component recorded as the first data is equally divided with respect to the data of all the 4DCT blocks of Pr, at the time of high-speed search, 4DC in one macroblock is used.
In all T blocks, the data from the low band to a certain frequency is reproduced on average, and a high quality search image is obtained. Further, the high-frequency components in which the influence of an error propagates to a plurality of blocks are also averagely divided among the 4DCT blocks, and the influence on the error also varies little among the DCT blocks.

Further, although one code is arranged and packed in each DCT block, another packing method can be considered, for example, two codes for Y and two codes for Pb and Pr are arranged.

In the case where an error occurs, the recording location of the low frequency component is predetermined every few macroblocks, and the boundary information of the high frequency component is recorded every few macroblocks. Also, since error propagation stops within several macroblocks, it is possible to realize error tolerance equivalent to code amount control in units of several macroblocks.
It should be noted that when a part of the data is not reproduced due to dropout or the like, it is better that the number of affected macroblocks is as small as possible. If the low frequency component cannot be reproduced due to an error, the macro block data cannot be decoded even if only the boundary information or the high frequency component is reproduced. According to the present invention, since the boundary information is recorded in the sync block in which the low frequency component is recorded, only the boundary information of the macro block in which the low frequency component is not reproduced when an error occurs is not reproduced. When the information is reproduced correctly, the low-frequency component is also reproduced correctly, so that the influence of the error can be limited to as few macroblocks as possible.

[0042]

As described above, according to the present invention, it is possible to decode encoded data by adding a small amount of additional information or a circuit having a simple structure even when the code amount control is performed over a wide range. Become. Therefore, it is possible to realize an image coding / recording / reproducing apparatus excellent in normal reproduction image quality without increasing the circuit scale and the processing time.

[Brief description of drawings]

FIG. 1 is a configuration diagram of an image encoding / recording / reproducing device according to first and second embodiments of the present invention.

FIG. 2 is an explanatory diagram of a zigzag scan according to the first embodiment.

FIG. 3 is a schematic diagram showing data packing of macroblocks according to the first embodiment.

FIG. 4 is a conceptual diagram showing a method of storing coded data of one channel in the first embodiment.

FIG. 5 is a conceptual diagram showing a method for storing coded data for one channel in the second embodiment.

FIG. 6 is a configuration diagram of an image encoding / recording / reproducing device according to a third embodiment.

FIG. 7 is a conceptual diagram showing a method of storing coded data for one channel in the third embodiment.

[Explanation of symbols]

 2 Blocking circuit 3 DCT circuit 4 Code amount control circuit 5 Quantization circuit 6 Variable length coding circuit 7 Packing circuit 8 Code amount counter 9, 22, 34, 44, 46 Memory control circuit 12 Boundary information generation circuit 14 Recording signal processing Circuit 18 Reproduced signal processing circuit 19 Boundary information detection circuit 20 Quantization parameter detection circuit 23 END detection circuit 24 Variable length decoding circuit 25 Inverse packing circuit 26 Inverse quantization circuit 27 Inverse DCT processing circuit 28 Inverse blocking circuit 39 Marker generation circuit 42 Marker detection circuit

─────────────────────────────────────────────────── ─── Continuation of the front page (51) Int.Cl. ⁶ Identification code Internal reference number FI Technical indication H04N 7/24 H04N 7/13 Z

Claims (9)

[Claims] 1. An image signal is subjected to orthogonal transform for each transform block composed of a plurality of pixels, and variable length coded in macroblock units consisting of one or a plurality of transform blocks. In an image coding recording / reproducing apparatus for recording in sync block units, the sync block is composed of a low frequency sync block storing low frequency data and a high frequency sync block storing high frequency data,
A unit for performing variable length coding in order from the low-frequency transform coefficient for each macroblock, and one low-frequency sync block for each of M macroblocks, and a data area of the low-frequency sync block for each N bits. If the code amount is N bits or more, up to the Nth bit, and if the code amount is less than N bits, all encoded data are divided into M sub-regions. 1 data corresponding to 1 from the beginning of the encoded data of the macroblock.
Of the encoded data of the M macroblocks in a vacant area generated when the code amount of the macroblock is less than N bits in the M small areas. Means for storing coded data other than the first data as second data, and means for storing data other than the first data and the second data among the coded data of the M macroblocks. An image coding / recording / reproducing apparatus provided with means for storing the data of No. 3 in a high frequency sync block and means for recording the data stored in each sync block in sync block units. 2. An image signal is subjected to orthogonal transform for each transform block consisting of a plurality of pixels, and variable-length encoded data is encoded in macroblock units consisting of one or a plurality of transform blocks to obtain a fixed-length encoded data. In an image coding recording / reproducing apparatus for recording in sync block units, the sync block is composed of a low frequency sync block storing low frequency data and a high frequency sync block storing high frequency data,
A means for performing variable length coding in order from the low-frequency transform coefficient for each macroblock, and one low-frequency sync block for each of the M macroblocks, and one macroblock for each data area in the low-frequency sync block. When storing the encoded data, L of the M macroblocks is stored.
For the (L = 1, 2, ..., M) th macroblock, the cumulative amount of the encoded data stored in the low-frequency sync block sequentially from the 1st to the Lth becomes L · N bits. Or all the encoded data of the macroblock are stored, a means for sequentially storing the encoded data of the macroblock in the low-pass sync block as first data from the beginning, and the low-pass sync block. The cumulative amount of the first data stored at the end of the storage of the first data of the Mth macroblock is M · N
A means for storing coded data other than the first data out of the coded data of the M macroblocks as second data in a free area generated because the number of bits is less than the number of bits; and the M macros. Means for storing data other than the first data and the second data in the high-frequency sync block in the encoded data of the block as the third data, and the data stored in the sync block in sync block units. And an image encoding / recording / reproducing apparatus provided with means for recording. 3. An image signal is subjected to orthogonal transform for each transform block composed of a plurality of pixels, and variable-length coded in macroblock units consisting of one or a plurality of transform blocks. In an image coding recording / reproducing apparatus for recording in sync block units, the sync block is composed of a low frequency sync block storing low frequency data and a high frequency sync block storing high frequency data,
A means for performing variable length coding in order from the low-frequency transform coefficient for each macroblock, and one low-frequency sync block for each of the M macroblocks, and one macroblock for each data area in the low-frequency sync block. When storing the encoded data, L of the M macroblocks is stored.
For the (L = 1, 2, ..., M) th macroblock, the cumulative amount of the encoded data stored in the low-frequency sync block sequentially from the 1st to the Lth becomes L · N bits. Or all the encoded data of the macroblock are stored, a means for sequentially storing the encoded data of the macroblock in the low frequency sync block as first data from the beginning, and S low frequency sync blocks. In the empty area generated when the cumulative amount of the first data stored at the end of storing the first data of the Mth macroblock is less than M · N bits, S assigned to the block
Of the encoded data of M macroblocks, the first
Storing encoded data other than the first data as second data, and third encoded data other than the first data and the second data among the encoded data of the S · M macroblocks. 2. An image coding / recording / reproducing apparatus comprising at least a means for storing the data in a high frequency sync block as the data and a means for recording the data stored in the sync block in sync block units. 4. Information indicating the recording position on the data recording area of the head of the third data recorded in the high frequency sync block is provided for each of K · M macroblocks.
3. The image coding / recording / reproducing apparatus according to claim 1, further comprising means for storing in a predetermined area in a low-frequency sync block assigned to the KM macro blocks. 5. The information indicating the recording position on the data recording area of the head of the third data recorded in the high frequency sync block is provided for each of K, S, and M macroblocks. 4. The image coding / recording / reproducing apparatus according to claim 3, further comprising means for storing in a predetermined area in a low-frequency sync block allocated to S · M macro blocks. 6. An image signal is subjected to orthogonal transform for each transform block composed of a plurality of pixels, and variable-length encoded data is encoded in a macro block unit consisting of one or a plurality of transform blocks to obtain a fixed-length encoded data. In an image encoding / recording / reproducing apparatus for recording in sync block units, means for variable length coding sequentially from the low-frequency transform coefficient for each macroblock, and one sync block for each macroblock are allocated, When the code amount of the macroblock is N bits or more, up to the Nth bit, and when the code amount of the macroblock is less than N bits, all the encoded data are first
Means for recording in the sync block in order from the beginning of the encoded data of the macroblock as the data of
In units of a plurality of sync blocks that store the data of each of the sync blocks, the coded data other than the first data among the coded data of the macroblock is used as the second data, and each sync is assigned to the plurality of macroblocks. Means for storing in a free area which occurs when the code amount of the macroblock is less than N bits in the block, and the coded data of the macroblock is composed of only the first data for each macroblock. Indicates whether or not 1
A recording unit having means for storing bit marker information in a predetermined position of the sync block, means for recording the sync block data in sync block units, means for detecting the marker information, and the macro. An image coding / recording / reproducing apparatus provided with a reproducing unit having means for first decoding a macroblock in which coded data of a block is composed of only the first data. 7. One bit is assigned to each of a plurality of macroblocks, and one bit indicates, for each macroblock, whether or not encoded data of the macroblock is composed of only the first data. Marker information of
7. The image coding recording / reproducing apparatus according to claim 6, further comprising means for storing the sync block at a predetermined position. 8. For each K macroblocks having the second data, information indicating the recording position in the data recording area at the head of the second data is set to the macroblock K having the second data. 8. The image coding / recording / reproducing apparatus according to claim 6 or 7, further comprising means for storing in a predetermined area in a sync block allocated for each piece. 9. A means for performing variable-length coding for each macroblock in order from a low-frequency coefficient, variable-length coding to variable-length coded data in order from a low-frequency transform coefficient for each conversion block in a macroblock. And a means for retrieving and rearranging variable-length coded data from the low frequency band for each predetermined number of variable-length coded data for each conversion block in the macroblock. The image coding recording / reproducing apparatus according to claim 1, 2 or 3 or 6.