JP3240666B2 - Digital VTR recording system and apparatus - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a recording method and apparatus for recording digital image data into a variable length code and recording the data on a magnetic tape using a recording device such as a VTR.

[0002]

2. Description of the Related Art A conventional example of an image data recording / reproducing apparatus for performing compression is described in I Triple E Transaction on Consumer Electronics, Vol. 35 (1989).
Year 3) Pages 450 to 456 (IEEE Trans. On C
onsumer Electronics, vol.35 (1989), no.3, pp.450-45
6). A general method of compressing image data is to serially perform data conversion, quantization, and variable-length encoding on input image data. According to this method, the degree of data compression can be changed by changing the condition of quantization.
The above conventional example also follows this method. The data transformation of this conventional example is a DCT transformation (discrete cosine transformation) which is a kind of orthogonal transformation. Image data of 8 pixels vertically and 8 pixels horizontally is treated as one block, and two-dimensional DCT is performed for each block.
Conversion is being performed. The result of the data conversion is obtained by viewing the image data in the block on a broad frequency axis. The quantization is performed for each frequency component in consideration of human visual characteristics. Further, the data amount after the variable length coding is predicted by the data amount predictor, and the quantization condition is selected and quantized based on the prediction, whereby the data amount of one block after the variable length coding is reduced. It is kept below a predetermined size.
Then, for one block of code, I
D and an inner code parity are added to form a synchronous block having a fixed size, and an outer code parity is added to a set of a predetermined number of synchronous blocks to form one error correction code block. A sequence of synchronous blocks including these two error correction parities is digitally modulated and recorded on a magnetic tape. According to this method, error detection and correction can be performed using the inner code parity and the outer code parity. Even if an uncorrectable error occurs, each DCT block corresponds to a fixed-length synchronous block. Therefore, the error propagation range can be kept within one synchronous block.

[0003]

However, according to the prior art, irrespective of the magnitude of the entropy of each block (the minimum amount of information required for encoding), each block has a high code length in order to keep the same code length. In a situation where a compression ratio is required, coding distortion concentrates on a block with high entropy, and an excessive amount of data is allocated to a block with low entropy, resulting in inefficiency. Therefore, it is necessary to encode each block with a variable-length code and efficiently distribute the amount of data among the blocks in the screen, and it is necessary to configure and record an error correction code for such an encoding method. is there.

However, if the code length is made variable, simply storing the variable-length code continuously in the error correction code block and adding an error correction parity in the conventional manner would require each data conversion. Since the position of the beginning of the block starting from the error correction code block is not constant, there is a risk that the boundary of the block may be mistaken and the error may be widely propagated. Further, in order to obtain an image whose contents can be grasped, it is necessary to reproduce at least the codes of the DC component and the low frequency component, but at the time of high-speed reproduction, only a few synchronous blocks can be reproduced from the same track. It is necessary to effectively store the code of the low frequency component including the DC component in each synchronous block.

SUMMARY OF THE INVENTION It is an object of the present invention to provide a recording method in which, when an input image is recorded by variable-length encoding, the error propagation is small and the image quality at the time of high-speed reproduction is improved.

[0006]

The capacity of a sync block is approximately equal to the average code length of a macro block, and a variable length code is stored so that the macro block corresponds to the sync block.

[0007] fixed-length code area one sync block, constructed from the variable length code area, the variable length code area for storing a variable length code of sequential alternating component in ascending order of frequency. If the capacity of the sync block is exceeded, the data is stored in the free space of the variable length code area of another sync block constituting the same error correction block .

[0008]

In the reproduction of an image, the codes of the DC component and the low-frequency component of the more important macro block are stored in the corresponding sync block for each macro block, so that an uncorrectable error occurs in a certain sync block. However, the error does not propagate to the DC and low frequency components of other macroblocks. Therefore, even in such a case, an image whose contents can be recognized can be reproduced. In addition, at the time of high-speed reproduction, only a few sync blocks may be reproduced.In such a case, however, one set of DC components and low-frequency components are always included in the first half of one sync block. Thus, data can be efficiently acquired from the reproduced sync block, and an image whose content can be recognized can be reproduced.

[0009]

Embodiments of the present invention will be described below with reference to the drawings.

FIGS. 7 and 8 are basic structural views of an image data recording / reproducing apparatus according to a first embodiment of the present invention. 7 and 8
Indicates signal processing corresponding to the recording mode and the reproduction mode, respectively. A video signal is input from the input terminal 13,
It is input to the image encoding circuit 12 and the timing generation circuit 7. The timing generation circuit 7 generates various timing signals synchronized with the image signal for VTR recording. The image encoding circuit 12 divides each screen of the input video signal into a number of blocks and performs encoding for each block. This encoding is performed in three stages of data conversion, quantization and variable length encoding. The data conversion of the first-stage processing is a process of converting a video signal which is a signal level of each pixel into a frequency component in a broad sense. Quantization, which is the second stage processing, is a process of performing quantization using a quantization step width set for each frequency component. In the variable-length coding at the third stage, the quantized frequency components are rearranged into a one-dimensional sequence according to a certain rule so that they are arranged in order from low-frequency components to high-frequency components. This is a process of generating a variable-length code using a technique such as run-length coding or entropy coding. In the combination of quantization and variable length coding, it is possible to change the compression ratio of the output variable length code by changing the quantization condition.
In the present image data recording / reproducing apparatus, in order to make the data generation amount of each screen constant, encoding is performed by changing the quantization condition adaptively to the input image for each block. The variable-length coded image data (bit stream) is input to the error parity adding circuit 11. Error parity addition circuit 11
Generates a sync block (synchronous code block) by adding a synchronization code, an ID code, and various types of parities for each macro block in which a predetermined number of small units of image data, that is, DC conversion blocks, are collected, and a sequence of sync blocks is generated. I do. The synchronization code indicates a break of the sync block, and the ID code is a code for identifying the sync block. The parity is used to correct an error that occurs when the encoded image data is recorded and reproduced on a recording medium such as a magnetic tape. The row of sync blocks is modulated by the digital modulation circuit 10,
A recording signal is generated and supplied to the magnetic head 1. Using a magnetic head 1, a drum 2, a drum motor 5, a drum motor control circuit 6, a capstan 3, a capstan motor 8, and a capstan motor control circuit 9, a normal VTR recording operation is performed, and image data is transferred to a magnetic tape. Record in 4.

FIG. 1 shows the structure of an error correction code block according to a first embodiment of the present invention.

The error correction block is the largest unit of image data handled by the error parity adding circuit 11,
A predetermined number of error correction code blocks are collected to form one screen. The error correction block is composed of a predetermined number of sync blocks, and the capacity of the sync block is about the average code length of one macroblock as described above, and the average is 1 unit.
One macroblock of image data is stored for a sync block. The error correction code block includes
A two-dimensional product code is formed by including two types of parities, an inner code parity and an outer code parity. The outer code parity is a parity attached to the image data included in one error correction code block in a direction orthogonal to the sync block. On the other hand, the inner code parity is a parity attached in the length direction of the sync block, regardless of whether the content of the sync block is image data or outer code parity.
One for each sync block.

In this embodiment, one sync block corresponds to two sync blocks.
It is composed of different types of code areas, that is, a fixed length code area and a variable length code area. The fixed-length code area is an area for storing a code whose code length is determined in advance, such as a synchronization code, an ID code, a DC component (DC coefficient) of image data, a linkage address, and an inner code parity shown in FIG. This region may start from a discontinuous position in the sync block for each code if its position and size are fixed.
The variable length code area is an area for storing an AC component (AC coefficient) of image data that is variable in length for each macroblock.
Hereinafter, a method of storing the AC coefficient will be described.

In the present embodiment, first, A
The sign of the C component is divided into a low frequency component and a high frequency component. To the error parity adding circuit 11, codes from a low frequency component of a DC component and an AC component to a high frequency component are sequentially input for each macroblock. Each component of the luminance signal and the color signal of the image signal is time-division multiplexed and input. In the present embodiment, for such a bit stream, an AC low frequency component (ACL) is defined as a code within a range that can be stored in one sync block.
The codes thereafter are treated as AC high frequency components (ACH).

Next, image data is stored in an error correction code block in two stages for each of the classified frequency components. As the first stage, the low-frequency components are stored from the start position of the variable-length code area of the sync block corresponding to each macroblock (the position following the DC component in the figure). Since the total code length changes for each macroblock, some macroblocks leave an empty area in the variable-length code area. As a second stage, the high-frequency components of the macroblock are sequentially stored over the sync block by using the empty area. In this embodiment, the average code length of the macroblock is the capacity of the sync block (excluding the synchronization code, the ID code, and the inner code parity), so the macroblock that leaves an empty area in the syncblock and the block that exceeds the capacity of the syncblock Can be balanced, and codes that cannot be stored in one sync block, that is, high-frequency components of the macroblock can be stored in a free area of another sync block. When the high-frequency component is stored across the sync block, the start address of the code connected to the end of the sync block, that is, the linkage address is stored in the fixed-length code area of the current sync block.

FIG. 2 shows a configuration example of the error correction parity adding circuit of the present embodiment.

The switching circuit 33 and the memory 31 switch the bit stream after the variable length encoding inputted from the input terminal 30.
And a code length detection circuit 32. The code length detection circuit 32 detects the total code length of the block, the code length of each of the low frequency and the high frequency from the bit stream, and generates various timing signals such as a block delimiter and a switching timing of the low frequency component and the high frequency component. The data is input to the memory control circuit 34 and the packing management memory 37. The packing management memory 37 holds the code lengths of the low frequency component and the high frequency component of all the blocks of the error correction code block as packing management data. The memory control circuit 34 controls the memories 31 and 38 and the switching circuit 33 as follows based on the timing signal and the packing management data.

First, the memory control circuit 34 switches the switching circuit 33 during the input period of the DC component and the low frequency component, inputs the input signal of the terminal 30 as it is to the memory 38, and performs writing. During the input period, the input signal is not written into the memory 31. While the memory 31 is a first-in first-out memory, the memory 38 is a random access memory, and the memory control circuit 34 generates a write address in accordance with the format shown in FIG. This period is a range in which the data amount is within one sync block, and the address may be increased at a fixed rate after setting the DC component start address. During the input period of the high-frequency component following this,
The input signal is written to the memory 31 instead of the memory 38. The above process is performed for all the macroblocks of the error correction code block.
The sign of the DC component and the sign of the AC low frequency component are stored in the memory 38, and only the high frequency component is stored in the memory 31.

Next, as a second stage, a process of writing the high frequency components of the memory 31 to the memory 38 is performed. In the present embodiment, the free area of each sync block is regarded as continuous, and the data in the memory 31 is written to the memory 38 in order from the free area of the first sync block regardless of the correspondence between the sync block and the macroblock. At this time, the read amount of each macro block from the memory 31 can be known by referring to the packing management memory 37.
The initial value of the write address of each sync block, that is, the head address of the empty area, is also obtained by reading the code length of the low frequency component from the packing management memory 37 and adding a predetermined offset to the value. Subsequent addresses are obtained by sequentially increasing the addresses.
At the start of the high-frequency component of each macroblock, the write address at that time is stored as a linkage address at a predetermined position in the fixed-length code area of the corresponding sync block. Even if the capacity of one sync block is exceeded, the start address of the next free area is stored as a linkage address at a predetermined position in the fixed-length code area of the current sync block, and then a high-frequency component code following the linkage address is stored. I do. This process is repeated for all macroblocks having high frequency components, and image data for one error correction code block is stored.

The parity adding circuit 39 sequentially stores the memory 3
8, data is read out in sync block units, an inner code parity and an outer code parity are added, and output from an output terminal 40 as a bit stream.

The digital modulation circuit 10 performs digital modulation to match the bit stream with the characteristics of the magnetic tape, and reproduces a clock at the beginning and end of a predetermined number of error correction code blocks constituting one track. In addition, a code for enabling synchronization pull-in, that is, a preamble and a postamble are added and recorded on a magnetic tape.

Next, a method of reproducing the image data recorded by the above method will be described.

FIG. 8 is a block diagram at the time of reproduction of the image data recording / reproducing apparatus of the present invention. The same components as those in FIG. 7 are denoted by the same reference numerals. From the magnetic tape 4 using the head 1, the drum 2, the drum motor 5, the drum motor control circuit 6, the capstan 3, the capstan motor 8, the capstan motor control circuit 9, the synchronization detection circuit 21 and the timing generation circuit 7, Of the VTR is reproduced. The signal reproduced by the head 1 is output from a synchronization detection circuit 21.
After extracting various synchronization signals with the digital demodulation circuit 23,
Demodulates the digital image data. By this demodulation, the above-mentioned sequence of sync blocks is obtained. Error correction circuit 2
4 collects a predetermined number of the sync blocks to reconstruct an error correction code block, and detects and corrects an error using the inner code parity and the outer code parity. The error-corrected image data is subjected to the inverse processing of the processing performed by the image data encoding circuit 12 during recording by the image data decoding circuit 25. That is, variable-length code decoding, inverse quantization, inverse data transformation, and inverse blocking. The video signal is reproduced by the above processing and output from the output terminal.

According to this embodiment, the variable-length code is efficiently stored in the sync block and the error correction code is configured by sharing the free area of the sync block with the high-frequency component code of each macro block. Can be. Further, according to the present embodiment, since the DC component and the low frequency component of each macroblock are stored at predetermined positions of the corresponding sync blocks, an error occurring in a certain macroblock causes the DC component of another macroblock and the error to occur. It does not propagate to low frequency components. Further, since the linkage address for the high frequency component is stored in the corresponding sync block for each macroblock, error propagation in the code of the high frequency component can be stopped within one macroblock. Further, according to the present embodiment, even in a situation where only a few sync blocks can be reproduced from the same error correction code block at the time of high-speed reproduction, data of the DC components and low-frequency components of the macro blocks as many as the number of reproduced sync blocks must be obtained. It can reproduce image contents that can be recognized.

Next, a second embodiment of the present invention will be described. This embodiment differs from the first embodiment in the method of storing high-frequency components, in which high-frequency components are stored from an empty area near the corresponding sync block. The method of storing codes other than high-frequency components is the same as in the first embodiment,
The basic configuration of the error correction parity adding circuit is the same as that of the first embodiment (FIG. 2). However, the contents of the packing management memory 37 and the control method of the memory control circuit 34 when storing high-frequency components are different.

FIG. 3 shows a second embodiment. FIG. 3 shows the contents of the packing management 37. Packing management memory 37
Stores the difference between the code length of the macroblock and the capacity of the variable-length code area of the sync block. Assuming that the code bits are independent of each other, this value includes a packing flag (PF) indicating whether or not the sync block is filled with the code of the macroblock as shown in FIG. Excess of the code of the corresponding macroblock, that is, the code amount of the high-frequency component, or the start address (start address) of a free area when the code is not satisfied
(It is necessary to treat a start address by adding a predetermined value.)

The memory control circuit 34 refers to the contents of the packing management memory 37 and finds that the macroblock of PF = 0, that is, the corresponding sync block has no free area, and the macroblock in which data is stored in the memory 31 by the excess amount S. Is read from the memory 31 and written to the sync block in the memory 38 corresponding to PF = 0. Writing is performed from a sync block near PF = 1, and the packing management data is updated as appropriate for both the start address and the excess amount. Therefore, PF =
0 and S = 0. When changing the sync block during the writing of a certain macro block, the start address of the sync block near PF = 1 is read from the packing management memory 37 and written as the linkage address of the current sync block.

According to the present invention, in addition to the features of the first embodiment, since the high-frequency components of each macroblock are stored in the vicinity of the corresponding sync block, more sync blocks in the vicinity reproduced during high-speed reproduction are used. A high-frequency code can be obtained to improve the image quality.

FIG. 4 shows a third embodiment of the present invention.

This embodiment is intended to make the size of the error correction code block common to that of the standard NTSC system in a high-definition television system such as a high-definition television system. In a high-definition television system, there are more macroblocks per screen, and therefore, in order to maintain the size of the error correction code block, one or more macroblocks must be stored per sync block. FIG.
Shows an example in which 26 macroblocks are stored for 15 sync blocks. A maximum of two macro blocks are stored in one sync block. In this embodiment, the capacity of the sync block is no longer the average code length, but the capacity of the entire error correction block is equal to the average value of the total code length of the macro blocks stored therein. The classification of one sync block into a fixed-length code area and a variable-length code area is the same as in the first or second embodiment. The variable-length code area is provided with an area (priority storage area) for preferentially storing the code of each macroblock corresponding to each macroblock stored in the sync block. In FIG. 4, the sync block having two macro blocks is 2
One priority storage area (AC1 ′, AC2 ′, etc.) and one sync block having one macroblock
One priority storage area (such as AC5 '). In this embodiment, the definition of the low-frequency component of each macroblock is a code within a range that can be stored in the corresponding priority storage area, and a linkage address is provided in the fixed-length code area by the number of priority storage areas. Each linkage address indicates the address of the code following the end of each priority storage area. Each priority storage area stores, as in the first or second embodiment, the code of the low frequency component of the corresponding macroblock as far as its capacity permits, and for the code beyond that, that is, the high frequency component, stores the code of the other priority storage area. Store in a free area.

The configuration of the error correction code block circuit of this embodiment is the same as that of the first or second embodiment.

According to the present embodiment, an error correction code is constituted by an error correction code block having the same size as the standard NTSC for a high definition television system such as a high definition television. Similar effects can be obtained.

FIG. 5 shows a fourth embodiment of the present invention. This embodiment is also intended to make the size of the error correction code block common to the high-definition television system such as Hi-Vision as in the third embodiment. In this embodiment, one variable-length code area and one linkage address are provided for each sync block regardless of the number of macroblocks to be stored. The code of the AC component of each macroblock is stored alternately in the variable length area of the sync block storing a plurality of macroblocks. FIG. 6 shows a method of storing codes in the variable-length code area AC1 & 2 'of the first sync block.
ACn-m means the m-th code of the AC component of the n-th macroblock. The codes of the AC components within the range that can be stored in the variable-length code area of the corresponding sync block are defined as the codes of the low-frequency components, and the codes exceeding the range are defined as the codes of the high-frequency components, as in the first to third embodiments. A high frequency component is stored in an empty area of the variable length code area. Also for this high frequency component, if the corresponding sync block stores a plurality of macroblocks, each code is stored alternately for each macroblock. Similarly, the linkage address indicates the address of the code following the end of the variable length code area.

According to this embodiment, as in the third embodiment,
For a high-definition television system such as HDTV, an error correction code is formed by an error correction code block having the same size as the standard NTSC, and the same effect as in the first or second embodiment can be obtained. Since only one linkage address is required per sync block, an error correction code can be configured more efficiently than in the third embodiment.

[0035]

In an image encoding apparatus for compressing and encoding an input image in order to suppress the data amount of one screen to a constant value, in order to improve the image quality, the data amount to be allocated between the screen parts must be reduced. It is effective to perform variable length coding on the image of each part in consideration of the distribution. ADVANTAGE OF THE INVENTION According to the present invention, it is possible to effectively provide an error correction capability to variable-length coded image data and record the image data on a recording medium such as a VTR in which an error is likely to occur. In addition, if this recording method is used, since the code of the DC component and the low-frequency component of one data conversion block is always included in the code sequence of the minimum unit of recording and reproduction, the contents can be grasped even during high-speed reproduction. A reproduced image can be obtained.

[Brief description of the drawings]

FIG. 1 is a diagram showing a first embodiment of the present invention.

FIG. 2 is a basic configuration diagram of an error parity adding circuit (FIG. 7-11) in the first embodiment.

FIG. 3 is a diagram showing a second embodiment of the present invention.

FIG. 4 is a diagram showing a third embodiment of the present invention.

FIG. 5 is a diagram showing a fourth embodiment of the present invention.

FIG. 6 is a diagram illustrating a method of storing an AC component code according to a fourth embodiment.

FIG. 7 is a diagram illustrating an operation at the time of recording of the image encoding device of the present invention.

FIG. 8 is a diagram illustrating an operation at the time of reproduction of the image encoding device of the present invention.

[Explanation of symbols]

 12 image encoding circuit 11 error parity adding circuit 10 digital modulation circuit 23 digital demodulation circuit 24 error correction circuit 25 image decoding circuit

──────────────────────────────────────────────────続 き Continuing from the front page (72) Inventor: Masaru Takahashi 292, Yoshida-cho, Totsuka-ku, Yokohama-shi, Kanagawa Prefecture, Japan Inside the Media Research Laboratory of Hitachi, Ltd. (56) References JP-A-5-217300 (JP, A) ( 58) Field surveyed (Int.Cl. ⁷ , DB name) G11B 20/12 H04N 5/92

Claims (6)

(57) [Claims] 1. A digital image signal is subjected to data conversion for each part, variable-length coding is performed on the converted data, and an error correction code is added to a predetermined number of the coded image parts to generate an error correction code. On magnetic tape as correction code block
In the recording method of the digital VTR to be recorded , the above-mentioned variable length encoding is performed by generating a code in an error correction block.
The amount is controlled to be constant, and a plurality of sync blocks constituting the error correction code block are controlled.
The lock is divided into a fixed-length code area and a variable-length code area.
Are, each sync block in correspondence with an integral number of image portions, the image
The encoded image data for each part is
Data in order of data importance, and
Length code group consisting of fixed length code group and variable length code
A, and the variable length code group A
If the variable length code area of the lock is exceeded,
Classify the excess on the lower necessity side as variable length code group B
Classification means, the corresponding sync block data of the fixed-length code group
Second rank for sequentially storing the beginning of the variable length code region of sync blocks corresponding to the first storage means for storing in the fixed-length code area, data of the variable-length code group A
And pay means, all variable-length code group A of the same error correction code block
After storing the same data in the variable-length code group B gill
-In the free area of the variable length code area in the correction code block ,
Third to store over one or more sync blocks
Digital V which is characterized by providing the storing means, the
TR recording method. 2. A recording method according to claim 1, for each image portion of an integral number of image portions corresponding to one <br/> sync block, the sync priority storage area for storing preferentially provided by dividing the variable length code area in the block, the second storage means stores the variable-length code group a of each image portion in the priority storage area, said third storage means, the Free space in priority storage area
Recording system of a digital VTR, wherein the benzalkonium to store the variable-length code group B. The recording method as claimed in claim 1, further comprising: said second storing means and said third storage means, said variable-length code group A and the plurality of image portions corresponding to one sync block When storing the variable length code group B,
Digital V which comprises carrying out alternately for each image portion
TR recording method. 4. The recording method according to any one of claims 1 to 3, wherein the classification means performs Lud over data conversion converts the digital image signal into frequency components, the sign of the AC component low A digital VTR recording method characterized by classifying into a frequency component and a high frequency component, wherein a code of a low frequency component is a variable length code group A and a code of the remaining high frequency component is a variable length code group B. 5. The recording method according to claim 1, wherein the third storage unit stores the variable length code group B in a variable length of a sync block near a corresponding sync block. A recording method for a digital VTR, wherein data is stored from a free area of a code area. 6. A digital VTR using the recording method according to claim 1.