JPH05234261A - Recording system for digital vtr and device therefor - Google Patents

Abstract

PURPOSE:To effectively impart capability for error correction to picture data which are encoded with a variable length code by storing the direct current component of a macro block corresponding in a fixed length region and storing the variable length code of an alternating current component in the order of increasing frequency in a variable length code region. CONSTITUTION:A video signal is inputted to a picture encoding circuit 12 and a timing generating circuit 7 from an input terminal 13, and various timing signals synchronizing with a picture signal are generated for VTR recording in this circuit 7, each picture of an input video signal is divided into many blocks and encoded at every block. In this case, picture data encoded with a variable length code are inputted to an error parity additional circuit 11, and the strings of sink block are generated at every small unit. Also, each one sink block is formed with the fixed length code region and the variable length code region, the direct current component of a macro block corresponding to a fixed length region is stored and a variable length code of an alternating current component is stored in the order of increasing frequency in a variable length code region.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a recording method and apparatus for variable-length encoding digital image data and recording it on a magnetic tape using a recording device such as a VTR.

[0002]

2. Description of the Related Art A conventional example of an image data recording / reproducing apparatus for performing compression is the I Triple E Transaction on Consumer Electronics, Vol. 35 (1989).
Year No. 3, pp. 450 to 456 (IEEE Trans. On C
onsumer Electronics, vol.35 (1989), no.3, pp.450-45
6). A general method of compressing image data is to serially perform data conversion, quantization, and variable length coding processing on input image data. According to this method, the degree of data compression can be changed by changing the quantization condition.
The above conventional example also follows this method. The data transformation of this conventional example is a DCT transformation (discrete cosine transformation) which is a kind of orthogonal transformation, in which image data of 8 pixels in the vertical direction and 8 pixels in the horizontal direction is made into one block, and a two-dimensional DCT is made for each block.
Converting. As a result of this data conversion, the image data in the block is viewed on the frequency axis in a broad sense. Quantization is performed for each frequency component in consideration of human visual characteristics. In addition, the data amount after variable-length coding is predicted by the data amount predictor, the quantization condition is selected based on the prediction, and the quantization is performed to determine the data amount of one block after variable-length coding. It is kept below a predetermined size.
Then, for the code of one block, I of that block
D and inner code parity are added to form a sync block having a certain size, and outer code parity is added to a set of a predetermined number of sync blocks to form one error correction code block. A sequence of synchronization blocks including these two error correction parities is digitally modulated and recorded on a magnetic tape. According to this method, error detection and correction can be performed by the inner code parity and the outer code parity, and even if an uncorrectable error occurs, each DCT block corresponds to a sync block of a fixed length. Therefore, the error propagation range can be kept within one synchronization block.

[0003]

However, according to the prior art, regardless of the size of entropy (minimum amount of information required for encoding) of each block, in order to suppress each block to the same code length, Under a situation where a compression ratio is required, coding distortion concentrates on a high entropy block, and an excessive amount of data is allocated to a low entropy block, resulting in inefficiency. Therefore, it is necessary to code each block with a variable-length code to efficiently distribute the data amount among the blocks in the screen, and to configure and record an error correction code for such an encoding method. is there.

However, in the case where the code length is variable, if variable length codes are simply stored continuously in an error correction code block and error correction parity is added as in the conventional case, each data conversion is performed. Since it is not fixed at which position of the error correction code block the head of the block starts, there is a risk that the boundary of the block is mistaken and the error propagates widely. Also, in order to obtain an image whose content can be grasped, it is necessary to reproduce at least the code of the DC component and the low frequency component, but during high speed reproduction, only a few sync blocks can be reproduced from the same track. , It is necessary to effectively store the sign of the low frequency component including the DC component in each synchronization block.

An object of the present invention is to provide a recording method which is effective in improving image quality during high-speed reproduction with little error propagation when an input image is variable length coded and recorded.

[0006]

A capacity of a sync block is set to about an average code length of a macro block, and a variable length code is stored by associating the macro block with the sync block.

One sync block is composed of a fixed length code area, a variable length code area, and a linkage address,
The DC component of the macro block corresponding to the fixed length area is stored, and the variable length code of the AC component is sequentially stored in the variable length code area in ascending order of frequency. If the capacity of the sync block is exceeded, it is stored continuously in the free space of the variable length code area of other sync blocks that make up the same error correction block, and the start address is used as the linkage address for the fixed length code in the sync block. Store in area.

[0008]

In the reproduction of the image, since the codes of the DC component and the low frequency component of the macro block, which are more important, are stored in the sync blocks corresponding to each macro block, an uncorrectable error occurs in a certain sync block. However, the error does not propagate to the DC and low frequency components of other macroblocks. Therefore, even in such a case, an image whose content can be recognized can be reproduced. It is possible that only a few sync blocks are played during high-speed playback, but even in such a case, the first half of one sync block always contains a set of DC components and low-frequency components. , It is possible to efficiently acquire data from the reproduced sync block and reproduce an image whose content can be recognized.

[0009]

Embodiments of the present invention will be described below with reference to the drawings.

7 and 8 are basic configuration diagrams of an image data recording / reproducing apparatus according to the first embodiment of the present invention. 7 and 8
Shows the signal processing corresponding to the recording mode and the reproduction mode, respectively. Input the video signal from the input terminal 13,
It is input to the image coding circuit 12 and the timing generation circuit 7. The timing generation circuit 7 generates various timing signals synchronized with the image signal for VTR recording. The image encoding circuit 12 divides each screen of the input video signal into a large number of blocks and encodes each block. This encoding is performed in three stages of data conversion, quantization and variable length encoding. The data conversion in the first stage processing is a process of converting a video signal, which is a signal level of each pixel, into a frequency component in a broad sense. Quantization, which is the processing in the second stage, is a process of performing quantization using the quantization step width set for each frequency component. The variable length coding in the third stage rearranges the quantized frequency components into a one-dimensional sequence according to a certain rule so that the quantized frequency components are arranged from the low frequency component toward the high frequency component. This is a process of generating a variable length code by using a method such as run length coding or entropy coding. In the combination of quantization and variable length coding, it is possible to change the compression ratio of the output variable length code by changing the quantization condition.
In this image data recording / reproducing apparatus, in order to keep the amount of data generated on each screen constant, the quantization is adaptively changed for each block in the input image for encoding. This variable length coded image data (bit stream) is input to the error parity adding circuit 11. Error parity adding circuit 11
Is a small block of image data, that is, a sync block (sync code block) is formed by adding a sync code, an ID code, and various kinds of parity for each macro block obtained by collecting a predetermined number of DC conversion blocks, and a sequence of sync blocks is generated. To do. The sync code indicates a sync block delimiter, and the ID code is a code for identifying the sync block. The parity is for correcting an error that occurs when the encoded image data is recorded / reproduced on / from a recording medium such as a magnetic tape. The sequence of sync blocks is modulated by the digital modulation circuit 10,
A recording signal is generated and supplied to the magnetic head 1. Using the magnetic head 1, the drum 2, the drum motor 5, the drum motor control circuit 6, the capstan 3, the capstan motor 8, and the capstan motor control circuit 9, a normal VTR recording operation is performed, and image data is recorded on the magnetic tape. Record at 4.

FIG. 1 shows the structure of an error correction code block according to the first embodiment of the present invention.

The error correction block is the maximum unit of image data handled by the error parity adding circuit 11,
A predetermined number of error correction code blocks are collected to form one screen. The error correction block is composed of a predetermined number of sync blocks, and the capacity of the sync block is set to approximately the average code length of one macro block as described above, and the average code length is 1
The image data of one macroblock is stored in the sync block. In the error correction code block,
A two-dimensional product code is configured by including two types of parity, an inner code parity and an outer code parity. The outer code parity is a parity attached to the image data included in one error correction code block in a direction orthogonal to the sync block. On the other hand, the inner code parity is a parity attached in the length direction of the sync block, regardless of whether the content of the sync block is image data or outer code parity.
Add one for each sync block.

In this embodiment, one sync block has two
It is composed of various types of code areas, that is, a fixed length code area and a variable length code area. The fixed-length code area is a storage area for codes, such as the synchronous code, the ID code, the DC component (DC coefficient) of image data, the linkage address, and the inner code parity shown in FIG. This area may start from a discontinuous position in the sync block for each code if its position and size are fixed.
The variable length code area is an area for storing an AC component (AC coefficient) of image data having a variable length for each macroblock.
The method of storing the AC coefficient will be described below.

In this embodiment, first, A of each macroblock is
The sign of the C component is divided into a low frequency component and a high frequency component. The codes of the low-frequency component of the DC component and the high-frequency component of the AC component are sequentially input to the error parity adding circuit 11 for each macroblock. The luminance signal and the color signal components of the image signal are time-division multiplexed and input. In the present embodiment, for such a bit stream, the AC low frequency component (ACL) is defined as a code within a range that can be stored in one sync block.
The subsequent codes are treated as AC high frequency components (ACH).

Next, the image data is stored in the error correction code block in two steps for each of the classified frequency components. As a first step, the low frequency component is stored from the start position of the variable length code area of the sync block corresponding to each macro block (position following the DC component in the figure). Since the total code length changes for each macroblock, some macroblocks leave an empty area in the variable-length code area. As a second step, by utilizing this empty area, the high frequency components of the macro block are sequentially stored over the sync block. In this embodiment, the average code length of the macroblock is the capacity of the sync block (excluding the sync code, the ID code, and the inner code parity). Therefore, the capacity of the macroblock leaving a free space in the sync block and the capacity of the sync block are exceeded. Can be balanced, and the code that cannot be stored in one sync block, that is, the high frequency component of the macro block can be stored in the empty area of another sync block. When storing the high frequency component across the sync block, the start address of the code connected to the end of the sync block, that is, the linkage address, is stored in the fixed length code area of the current sync block.

FIG. 2 shows a configuration example of the error correction parity adding circuit of this embodiment.

The bit stream after variable length coding input from the input terminal 30 is switched to the switching circuit 33 and the memory 31.
And to the code length detection circuit 32. The code length detection circuit 32 detects the total code length of the block and the code length of each of the low frequency and high frequency from the bit stream, generates various timing signals such as block delimiters, switching timing of the low frequency component and the high frequency component, and outputs these timing signals. Input to the memory control circuit 34 and the packing management memory 37. The packing management memory 37 holds the code lengths of low frequency components and high frequency components of all blocks of the error correction code block as packing management data. The memory control circuit 34 controls the memories 31 and 38 and the switching circuit 33 as follows based on the timing signal and the packing management data.

First, the memory control circuit 34 switches the switching circuit 33 during the input period of the DC component and the low frequency component, inputs the input signal of the terminal 30 to the memory 38 as it is, and performs writing. During the input period, the input signal is not written in the memory 31. The memory 31 is a first-in / first-out memory, whereas the memory 38 is a random access memory, and the memory control circuit 34 generates a write address according to the format of FIG. 1 and performs memory writing. During this period, the amount of data is within one sync block, and the address may be increased at a constant rate after setting the DC component start address. During the input period of the high frequency component that follows,
The input signal is written to the memory 31 instead of the memory 38. The above process is performed for all macroblocks of the error correction code block, and as the first step,
The memory 38 stores the signs of the DC component and the AC low frequency component, and the memory 31 stores only the high frequency component.

Next, as a second step, a process of writing the high frequency component of the memory 31 into the memory 38 is performed. In this embodiment, the empty area of each sync block is regarded as continuous, and the data in the memory 31 is written in the memory 38 in order from the empty area of the first sync block regardless of the correspondence between the sync block and the macro block. The amount of each macro block read from the memory 31 at this time can be known by referring to the packing management memory 37.
The initial value of the write address of each sync block, that is, the start address of the empty area is also obtained by reading the code length of the low frequency component from the packing management memory 37 and adding a predetermined offset to the value. Subsequent addresses are obtained by sequentially increasing the address.
At the start of the high frequency component of each macroblock, the write address at that time is stored as a linkage address at a predetermined position in the fixed length code area of the corresponding sync block. Even when the capacity of one sync block is exceeded, the start address of the next empty area is stored as a linkage address in a fixed position in the fixed-length code area of the current sync block, and then the high-frequency component code following the linkage address is stored. To do. This process is repeated for all macroblocks having a high frequency component, and the image data for one error correction code block is stored.

The parity adding circuit 39 sequentially operates the memory 3
Data is read in sync block units from 8, the inner code parity and the outer code parity are added, and output from the output terminal 40 as a bit stream.

The digital modulation circuit 10 digitally modulates the bit stream to match the characteristics of the magnetic tape, and reproduces a clock at the beginning and end of a predetermined number of error correction code blocks constituting one track at the time of reproduction. And a code for enabling the pull-in of synchronization, that is, a preamble and a postamble are added and recorded on the magnetic tape.

Next, a method of reproducing the image data recorded by the above method will be described.

FIG. 8 is a block diagram of the image data recording / reproducing apparatus of the present invention during reproduction. The same numbers are attached to the same components as those in FIG. 7. From the magnetic tape 4 using the head 1, the drum 2, the drum motor 5, the drum motor control circuit 6, the capstan 3, the capstan motor 8, the capstan motor control circuit 9, the synchronization detection circuit 21, and the timing generation circuit 7, VTR signal reproduction is performed. The signal reproduced by the head 1 is the sync detection circuit 21.
After extracting various synchronization signals with the digital demodulation circuit 23
To demodulate the digital image data. By this demodulation, the above-mentioned sequence of sync blocks is obtained. Error correction circuit 2
Reference numeral 4 collects a predetermined number of these sync blocks to reconstruct an error correction code block, and detects and corrects an error using the inner code parity and the outer code parity. The image data that has undergone error correction is subjected to the reverse process of the process performed by the image data encoding circuit 12 at the time of recording by the image data decoding circuit 25. That is, variable-length code decoding, inverse quantization, data inverse transformation, and inverse blocking. The video signal is reproduced by the above processing and output from the output terminal.

According to the present embodiment, the code of the high frequency component of each macroblock shares the empty area of the sync block, so that the variable length code can be efficiently stored in the sync block to form the error correction code. You can Further, according to the present embodiment, since the DC component and the low frequency component of each macroblock are stored at the predetermined positions of the corresponding sync blocks, the error generated in a certain macroblock is It does not propagate to low frequency components. Further, since the linkage address for the high frequency component is stored in the corresponding sync block for each macro block, error propagation in the code of the high frequency component can be stopped within one macro block. Further, according to the present embodiment, even in the situation where only a few sync blocks can be reproduced from the same error correction code block at the time of high speed reproduction, the data of the DC component and the low frequency component of the macro blocks are always obtained by the number of the reproduced sync blocks. The image content that can be recognized can be reproduced.

Next, a second embodiment of the present invention will be described. The present embodiment differs from the first embodiment in the method of storing the high frequency component, and the high frequency component is stored from an empty area near the corresponding sync block. The method of storing codes other than high frequency components is the same as in the first embodiment,
The basic configuration of the error correction parity adding circuit is the same as that of the first embodiment (FIG. 2). However, the contents of the packing management memory 37 and the control method of the memory control circuit 34 when storing high frequency components are different.

FIG. 3 shows a second embodiment. FIG. 3 shows the contents of the packing management 37. Packing management memory 37
The difference between the code length of the macroblock and the capacity of the variable-length code area of the sync block is stored in. Considering this value independently of the code bits, as shown in FIG. 3, a packing flag (PF) indicating whether or not the sync block is filled with the code of the macro block, and a packing flag (PF) when it is filled, The excess of the code of the corresponding macroblock, that is, the code amount of the high frequency component, or the start address (start address) of the empty area when it is not satisfied
Is shown (the start address must be handled by adding a predetermined value).

The memory control circuit 34 refers to the contents of the packing management memory 37, and there is no free area in the macro block of PF = 0, that is, the corresponding sync block, and the macro block in which the excess amount S of data is stored in the memory 31. The high frequency component code of is read from the memory 31 and written in the sync block in the memory 38 corresponding to PF = 0. Writing is performed from the sync block near PF = 1, and the packing management data is appropriately updated for both the start address and the excess amount. Therefore, PF =
0 and S = 0. When changing a sync block in the middle of writing a certain macro block, the start address of the sync block near PF = 1 is read from the packing management memory 37 and written as the linkage address of the current sync block.

According to the present invention, in addition to the features of the first embodiment, since the high frequency components of each macroblock are stored in the vicinity of the corresponding sync block, more sync blocks are reproduced from the nearby sync blocks reproduced during high speed reproduction. It is possible to obtain a high frequency code and improve the image quality.

FIG. 4 shows a third embodiment of the present invention.

This embodiment is for making the size of the error correction code block common to the standard NTSC system in a high definition television system such as a high definition. In a high-definition television system, there are more macroblocks per screen, and therefore one or more macroblocks must be stored per sync block in order to maintain the size of the error correction code block. Figure 4
Shows an example in which 26 macro blocks are stored for 15 sync blocks. Up to two macroblocks are stored in one sync block. In this embodiment, the capacity of the sync block is no longer the average code length, but the capacity of the entire error correction block is equal to the average value of the total code lengths of the macro blocks stored therein. Classifying one sync block into a fixed length code area and a variable length code area is the same as in the first or second embodiment. The variable-length code area is provided with an area (priority storage area) for preferentially storing the code of each macroblock, corresponding to each macroblock stored in the sync block. In FIG. 4, a sync block having two macro blocks has two
A sync block including one priority storage area (AC1 ′, AC2 ′, etc.) and having one macroblock is one.
It consists of one priority storage area (AC5 ', etc.). In the present embodiment, the definition of the low frequency component of each macroblock is a code within a range that can be stored in the corresponding priority storage area, and linkage addresses are provided in the fixed length code area as many as the number of priority storage areas. Each linkage address indicates the address of the code following the end of each priority storage area. Similar to the first or second embodiment, each priority storage area stores the code of the low frequency component of the corresponding macroblock as long as its capacity permits, and the codes exceeding it, that is, the high frequency component, are stored in the other priority storage areas. Store in an empty area.

The structure of the error correction code block circuit of this embodiment is the same as that of the first or second embodiment.

According to the present embodiment, the error correction code is composed of the error correction code block having the same size as the standard NTSC for the high definition television system such as high-definition television. The same effect can be obtained.

FIG. 5 shows a fourth embodiment of the present invention. This embodiment is also for making the error correction code block size common to a high definition television system such as a high-definition television as in the third embodiment. In this embodiment, one variable length code area and one linkage address are provided for each sync block regardless of the number of macro blocks stored. In the variable length area of the sync block that stores a plurality of macroblocks, the codes of the AC components of the macroblocks are alternately stored. FIG. 6 shows a code storage method for the variable-length code areas AC1 & 2 ′ of the first sync block.
ACn-m means the mth code of the AC component of the nth macroblock. The AC component code in the range that can be stored in the variable-length code area of the corresponding sync block is defined as the low frequency component code, and the code exceeding the range is defined as the high frequency component code, as in the first to third embodiments. A high frequency component is stored in an empty area of the variable length code area. Also for this high frequency component, if the corresponding sync block stores a plurality of macroblocks, each code is stored alternately for each macroblock. Similarly, the linkage address also indicates the address of the code following the end of the variable length code area.

According to this embodiment, as in the third embodiment,
For a high-definition television system such as a high-definition television, an error-correcting code block is formed by an error-correcting code block having the same size as the standard NTSC, and the same effect as that of the first or second embodiment can be obtained. Since only one linkage address is required for each sync block, an error correction code more efficient than the third embodiment can be constructed.

[0035]

EFFECT OF THE INVENTION In an image coding apparatus for compressing and coding an input image in order to suppress the data amount of one screen to a constant value, in order to improve the image quality, in order to improve the image quality, Considering distribution, it is effective to perform variable-length coding on the image for each part. According to the present invention, it is possible to effectively provide an error correction capability to variable-length coded image data and record the image data on a recording medium such as a VTR in which an error easily occurs. In addition, when this recording method is used, the code of the minimum unit of recording and reproduction always contains the code of the DC component and the low frequency component of one data conversion block, so the contents can be grasped even during high-speed reproduction. A reproduced image can be obtained.

[Brief description of drawings]

FIG. 1 is a diagram showing a first embodiment of the present invention.

FIG. 2 is a basic configuration diagram of an error parity adding circuit (FIG. 7-11) in the first embodiment.

FIG. 3 is a diagram showing a second embodiment of the present invention.

FIG. 4 is a diagram showing a third embodiment of the present invention.

FIG. 5 is a diagram showing a fourth embodiment of the present invention.

FIG. 6 is a diagram showing a method of storing an AC component code according to a fourth embodiment.

[Fig. 7] Fig. 7 is a diagram for describing an operation at the time of recording of the image encoding device of the present invention.

[Fig. 8] Fig. 8 is a diagram explaining an operation at the time of reproduction of the image encoding device of the present invention.

[Explanation of symbols]

 12 ... Image coding circuit 11 ... Error parity addition circuit 10 ... Digital modulation circuit 23 ... Digital demodulation circuit 24 ... Error correction circuit 25 ... Image decoding circuit

 ─────────────────────────────────────────────────── ─── Continuation of the front page (72) Inventor Masashi Takahashi 292 Yoshida-cho, Totsuka-ku, Yokohama-shi, Kanagawa Ltd.

Claims (7)

[Claims] 1. A digital image signal is converted into data for each part, variable length coding is performed on the converted data, and an error correction code is added to a predetermined number of the coded image parts to generate an error. In a digital VTR having means for forming a correction code block, a code of image data is composed of a fixed-length code group consisting of fixed-length codes and two variable-length code groups A having different degrees of importance for each image portion.
And a unit for classifying into B, and a minimum unit of recording and reproduction, that is, a sync block and an integer number of image parts are associated with each other,
The sync block is classified into two code areas, that is, a fixed length code area and a variable length code area, and the code of the fixed length code group of the image portion is stored in the fixed length code area of the corresponding sync block. After storing the variable length code group A having higher importance than B sequentially from the head position of the variable length code area of the corresponding sync block, and after storing all the variable length code groups A in the same error correction code block ,
A means for storing the code of the variable-length code group B in the empty area of the variable-length code area over a plurality of sync blocks, and a code storage start position of the change destination when the storage is performed by replacing the sync block with the current sync block. Of the digital V, characterized by having means for storing in a fixed length area of
TR recording method. 2. The recording method according to claim 1, wherein a variable length code area in the sync block is divided into a priority storage area for preferential storage for each of a plurality of image portions corresponding to one sync block. Means for storing the variable-length code group A of each image portion in the area, and storing the variable-length code group B in the empty area irrespective of the above correspondence, and the area for each priority storage area A digital V characterized by storing the position of the code following the end of the
TR recording method. 3. The recording method according to claim 1, wherein the variable length code groups A and B of a plurality of image portions corresponding to one sync block are stored alternately for each image portion. Digital VTR recording method. 4. The recording method according to any one of claims 1 to 3, wherein conversion data conversion for converting into a frequency component is performed, the sign of the AC component is classified into a low frequency component and a high frequency component, and the sign of the low frequency component is changed. A digital VT characterized in that a long code group A and a high frequency component code are a variable length code group B
R recording method. 5. The recording method according to claim 4, wherein a low-frequency code until a variable-length code area of one sync block is filled is a variable-length code group A, and codes of AC components thereafter are variable-length. A recording method of a digital VTR characterized in that a code group B is used. 6. The digital recording method according to claim 1, wherein the variable-length code group B is stored from an empty area of a variable-length code area of a sync block near a corresponding sync block. VTR recording method. 7. A digital VTR using the recording system according to claim 1.