JP3152729B2 - Bandwidth compression processor - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an apparatus for converting a video signal or the like into a digital signal and performing band compression by combining intra-frame coding and inter-frame coding.
When the output signal is recorded on a tape in a helical scan system and transmitted to a recording / reproducing apparatus for reproducing the same, a good reproduced image can be easily obtained, particularly at the time of high-speed reproduction.

[0002]

2. Description of the Related Art As is well known, in digitally transmitting a video signal, band compression is performed by a transmission method using a variable length coding system, or by combining intra-frame coding and inter-frame coding. Transmission methods and the like are being studied. Among these, the technology of performing band compression by combining intra-frame encoding and inter-frame encoding and transmitting the data is disclosed in, for example, the document IEEE Trans.on Broadcasting.
Woo Paik described in Vol.36 NO.4 DEC 1990: “Digit
al compatible HD-TV Broadcast system ”is a band compression technology as shown in the figure.

In FIG. 24, a video signal input to an input terminal 11 is supplied to a subtraction circuit 12 and a motion evaluation circuit 13, respectively. In the subtraction circuit 12, a subtraction process described later is performed, and the output is input to a DCT (discrete cosine transform) circuit 14. The DCT circuit 14 captures 8 pixels in the horizontal direction and 8 pixels in the vertical direction as a unit block (8 × 8 pixels = 64 pixels), and outputs coefficients obtained by converting the pixel array from the time domain to the frequency domain. Then, each coefficient is quantized by the quantization circuit 15. In this case, the quantization circuit 15 has 10 or 32 types of quantization tables, and individual coefficients are quantized based on the selected quantization table. The quantization circuit 15
Is provided with a quantization table so that the amount of generated information and the amount of transmitted information fall within a certain range.

The coefficient data output from the quantization circuit 15 is zigzag-scanned from the low band to the high band for each unit block and extracted.
6 and is subjected to variable-length coding with a set of a subsequent number of zero coefficients (run length) and a non-zero coefficient. The encoder is a variable-length encoder having a different code length depending on the frequency of occurrence of Huffman codes or the like. Then, the variable-length coded data is input to a FIFO (first-in first-out) circuit 17 and is read out at a specified speed. [Control signal, audio data, synchronization data (SYN
C), which multiplexes NMP and the like, which will be described later]. The FIFO circuit 17 serves as a buffer for absorbing the difference between the generated code amount and the transmitted code amount because the output of the variable length coding circuit 16 is a variable rate and the transmission line rate is a fixed rate. .

The output of the quantization circuit 15 is input to an inverse quantization circuit 19 and is inversely quantized. Further, the output of the inverse quantization circuit 19 is input to the inverse DCT circuit 20 and returned to the original signal. This signal is input to the frame delay circuit 22 via the addition circuit 21. The output of the frame delay circuit 22 is supplied to a motion compensation circuit 23 and the motion evaluation circuit 13, respectively. Motion evaluation circuit 13
Is the input signal from the input terminal 11 and the frame delay circuit 2
2 to detect the overall motion of the image, and control the phase position of the signal output from the motion compensation circuit 23. In the case of a still image, compensation is performed so that the original image matches the image one frame before. The output of the motion compensation circuit 23 can be supplied to the subtraction circuit 12 via the switch 24, and can also be fed back from the addition circuit 21 to the frame delay circuit 22 via the switch 25.

Next, the basic operation of the above system will be described. The basic operation of this system includes an intra-frame encoding process and an inter-frame encoding process. The intra-frame encoding process is performed as follows. When this process is performed, the switches 24 and 25 are both off. The video signal at the input terminal 11 is converted from the time domain to the frequency domain by the DCT circuit 14 and quantized by the quantization circuit 15. This quantized signal is output to the transmission path via the FIFO circuit 17 after being subjected to the variable length encoding process. The quantized signal is supplied to an inverse quantization circuit 19
The signal is returned to the original signal by the inverse DCT circuit 20 and is delayed by the frame delay circuit 22. Therefore, at the time of the intra-frame encoding processing, it is equivalent to the information of the input video signal being subjected to variable-length encoding as it is. This intra-frame processing is performed at appropriate intervals in scene changes of the input video signal and in predetermined blocks. The processing in the periodic frame will be described later.

Next, the inter-frame encoding process will be described. When the inter-frame encoding process is performed, the switches 24 and 25 are both turned on. Therefore, a signal corresponding to the difference between the input video signal and the video signal one frame before is obtained from the subtraction circuit 12. This difference signal is
The signal is input to the DCT circuit 14, converted from the time domain to the frequency domain, and then quantized by the quantization circuit 15. Further, since the difference signal and the video signal are added to the frame delay circuit 22 by the addition circuit 21 and input,
A predicted video signal that predicts the input video signal from which the difference signal is generated is generated and input.

FIG. 25 shows a line signal in a state in which a video signal of a high-definition television signal has been subjected to the intra-frame processing and the inter-frame processing as described above, and is transmitted on a transmission path. This signal is a signal of a transmission line, and is shown in a state where a control signal, an audio signal, a synchronization signal (SYNC), a system control signal, an NMP, and the like are multiplexed. FIG. 25A shows the signal of the first line, and FIG. 25B shows the signal of the second and subsequent lines. If this video signal has been processed in a frame, a normal video signal can be obtained by performing inverse conversion. However, in the case of a video signal that has been subjected to an inter-frame encoding process, even if this signal is inversely transformed, only a difference signal is reproduced. Therefore, a normal video signal can be reproduced by adding the video signal (or predicted video signal) reproduced one frame before to this difference signal.

According to the above-mentioned system, the signal processed in the frame has all information variable-length coded, and the signal processed in the inter-frame after the next frame transmits differential information, and the This means that compression has been achieved.

Next, the definition of a set of pixels to be processed by the above band compression system will be described. That is, a block: an area of 64 pixels composed of 8 pixels in the horizontal direction and 8 pixels in the vertical direction. Super block: A region composed of four blocks in the horizontal direction and two blocks in the vertical direction of the luminance signal. This area includes one block each of the color signals U and V.
Further, the image motion vector obtained from the motion evaluation circuit 13 is included in a super block unit. Macro block: 11 super blocks in the horizontal direction. When a code is transmitted, the DCT coefficient of the block is converted into a code determined by the number of consecutive zero coefficients and the amplitude of the non-zero coefficient, and transmitted as a set. Finally, an end-of-block signal is added. Then, the motion vector of the motion correction performed in units of super blocks is added and transmitted in units of macro blocks.

[0011] The transmission signal shown in FIG.
Particularly relevant matters will be further explained. First
The line synchronization (SYNC) signal indicates a frame synchronization signal in the decoder, and all the timing signals of the decoder are generated using one synchronization signal per frame. The NMP signal on the first line indicates the number of video data from the end of this signal to the beginning of the macroblock of the next frame. This is because the code is configured by adaptively switching between the intra-frame encoding process and the inter-frame encoding process, so that the code amount of one frame is different for each frame, and the code position is different. It is to come. Therefore, the position of the code corresponding to one frame is indicated by the NMP signal.

Further, as a countermeasure when the user changes the channel, periodic intra-frame processing is performed. That is, in this band compression system, as described above, the eleven super blocks in the horizontal direction are called macroblocks, and there are 44 super blocks in one screen in the horizontal direction. That is, there are a total of 240 macroblocks in one frame, including 4 macroblocks in the horizontal direction and 60 macroblocks in the vertical direction. Then, in this band compression system, FIGS.
As shown in FIGS. 27A to 27C, refresh is performed for each column of a superblock in units of four macroblocks, and all superblocks are refreshed every 11 frames. That is, as shown in FIG. 27D, by storing 11 frames of refreshed super blocks, intra-frame processing is performed in all areas.
For this reason, for example, during normal reproduction of a VTR (video tape recorder) or the like, the above-described intra-frame processing is performed at a period of 11 frames, so that a reproduced image can be viewed without any problem.

Note that head data is inserted at the head of the macroblock. This head data includes
A motion vector, a field / frame determination, a PCM / DPCM determination, a quantization level, and the like of each superblock are inserted together.

By the way, the above-mentioned band compression system has:
It is used as an encoder for band compression of a television signal, and its decoder is used on the receiving side. Here, it is considered that the transmission signal is recorded on a VTR.
A general VTR is a method in which a video signal of one field is converted into a fixed-length code, a certain amount of information is generated, and recorded on X tracks (X is a positive integer).

On the other hand, when recording and reproducing on a VTR using the transmission signal obtained by the band compression system as it is, a variable length code is used as it is for the intra-frame processing and inter-frame processing code. The position where the code processed in the frame is recorded is not fixed, and blocks that are not refreshed are generated at the time of high-speed reproduction.

More specifically, FIG. 28
Helical recording of variable-length coded signals on magnetic tape 26
This shows a track pattern when recorded. Trad
Pattern T₁~ T₁₁In the figure, the part shown by the thick line
Room F₁~ F₁₁Indicates the switching position of. Frey
Mu F₁~ F₁₁It is possible that the switching positions of
This is because the record data is created using variable length codes.
You. Then, this magnetic tape 26 is normally reproduced by a VTR.
In this case, all the track patterns T₁~ T ₁₁Is magnetic
Since the head is sequentially scanned by the head, its playback output
Pass through the decoder to ensure normal video without any problems.
The signal can be reproduced. That is, during normal playback
Is the in-frame processing recorded on the magnetic tape 26.
It is possible to reproduce both the code and the code processed between frames.
Because it is possible to compose an image using all codes
It is.

However, in a VTR, there are cases where only a limited number of tracks are reproduced, for example, in a double-speed reproduction mode in special reproduction. At this time, the magnetic head jumps the track and picks up the recording signal. In this case, there is no problem if the tracks of the signal subjected to the intra-frame encoding processing are successively reproduced, but if the track subjected to the inter-frame encoding processing is reproduced, only an image based on the difference signal is obtained.

FIG. 29 shows trace loci X _{1 to} X ₁₁ of the magnetic head in the case of performing 2 × speed reproduction. FIG.
In FIG. 9, since the signals subjected to the intra-frame encoding processing are dispersedly recorded in the frames F _{1 to} F ₂₄ , the position of the intra-frame processing portion reproduced in the screen is undefined. FIGS. 30 (a) to 30 (h) and FIGS. 31 (a) to 31 (c) show intra-frame processed signals that can be reproduced at 2 × speed reproduction. And these 1
When one frame is accumulated, as shown in FIG.
There is no code that has undergone periodic intra-frame processing, that is, there is a portion where a refreshed super block does not exist, and a portion where a reproduced image cannot be formed occurs.

[0019]

As described above, the helical scan recording / reproducing apparatus provided with the conventional band compression system has a problem that high-speed reproduction such as double-speed reproduction becomes difficult.

Therefore, the present invention has been made in view of the above circumstances, and has as its object to provide an extremely good band compression processing apparatus capable of easily obtaining a good reproduced image at high speed reproduction.

[0021]

A band compression processing apparatus according to the present invention provides a video signal of one screen with a number (a is a positive integer).
The video signal is subjected to an intra-frame encoding process using the information within the frame, and an inter-frame encoding process is performed using the difference information between the frames. Band compression means for generating an inter-frame processed signal, performing intra-frame coding processing after the intra-frame coding processing, and adaptively repeating this signal processing method according to the motion evaluation of the input video signal; Refresh encoding processing means for periodically performing intra-frame encoding processing on signals of b image areas out of a areas for each frame with a period of f (f is an integer of f ≧ 2); A circuit for calculating the generated code amount of the refresh block which has been subjected to the refresh coding processing, and a refresh block for preventing a predetermined number of refresh blocks from exceeding a predetermined maximum code amount. Dividing the code click into a plurality of code divided into a plurality, in which so as to record the code of the low-frequency component or the quantization bit MSB in a predetermined area.

Further, the band compression processing apparatus according to the present invention forms a (a is a positive integer) image area in a video signal of one screen, and uses information in a frame for this video signal. An intra-frame processing signal subjected to intra-frame encoding processing and an inter-frame processing signal subjected to inter-frame encoding processing using difference information between frames are created. A band compression unit that performs an encoding process and adaptively repeats this signal processing method according to the motion evaluation of the input video signal; and f frames (f is f ≧ 2).
Of the a region for each frame
A refresh coding processing means for periodically performing intra-frame coding processing on the signal of each image area, a circuit for calculating the generated code amount of the refresh block which has been subjected to the refresh coding processing, and In the refresh block, the code of the refresh block is divided into a plurality of codes so as not to exceed a predetermined maximum code amount, and the code amount of the MSB of the low-frequency component or the quantized bit among the divided codes is set to a predetermined number. The code amount of the low-frequency component or the MSB of the refresh block is controlled and divided so as not to exceed a predetermined maximum code amount in the refresh block.

[0023]

According to the above configuration, a signal subjected to intra-frame encoding processing can be obtained accurately at the time of high-speed reproduction, so that a good reproduced image can be obtained.

[0024]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment of the present invention will be described below in detail with reference to the drawings. In this embodiment, since the intra-frame encoding process is performed on 2640 regions per screen in 11 frames, the number of regions a per screen is a = 2640 and the intra-frame encoding processing period f = 11 frames. Here, an example in which a = 2640 regions do not overlap each other is used, but they may overlap. further,
In order to explain the case where one track is divided into 10 and the average video code for one frame is recorded in one track, the number of divisions d per track = 10, the number of tracks for recording the average video code for one frame Let c = 1. Therefore, the number of recording medium areas is d × c × f = 10 × 1 × 11 = 110. The correspondence between the screen area and the recording medium area will be described in the case of equal distribution. Note that, in the present invention, it is not always necessary to equally allocate. Therefore, the number of screen areas e = a / d × c × f = 2640 that enters one recording medium area
/ 10 × 1 × 11 = 24 pieces, and e = 24 pieces are replaced by d
The case of associating with × c × f = 110 regions will be described.

In FIG. 1, the same portions as those in FIG. 24 are denoted by the same reference numerals, and the description will focus on the portions different from the conventional system. FIG. 2 shows the operation timing of this system. Here, this embodiment will be described with reference to a block diagram on the encoder side for the sake of simplicity, but it can also be realized on the decoder side receiving the transmission data shown in FIG. FIG. 1 will be described. The input terminal 27 is supplied with a synchronization signal SYNC of the input video signal. This synchronization signal SYNC is S
The signal is input to the YNC signal detection circuit 28 and detected. SY
The NC signal detection circuit 28 generates a SYNC pulse synchronized with the synchronization signal SYNC to generate the track formation signal generation circuit 2
9. In the case where the synchronization signal SYN in the transmission data shown in FIG.
C may be detected and input to the SYNC signal detection circuit 28.

FIG. 2A shows an input video signal, Y indicates a luminance signal, U and V indicate chrominance signals, and the numbers written in the frames indicate the frame numbers. FIG.
(B) SY obtained from the SYNC signal detection circuit 28
An NC pulse is generated in synchronization with a frame switching point of the input video signal shown in FIG. FIG. 2C shows a track forming signal obtained from the track forming signal generating circuit 29. A and B attached to the track formation signal designate a period in which the A head and the B head alternately form a track. A
As shown in FIG. 1, the head and the B head are mounted at a position facing the rotary drum 30 by 180 °. Here, a case will be described in which heads are attached one by one, but if the amount of code that can be recorded in one track is small, p (p is a positive integer) opposed heads should be arranged. Good. In this embodiment, the SY shown in FIG.
The generation timing of the NC pulse and the switching timing of the track forming signal shown in FIG. 2C are synchronized. FIG. 2D shows a track formed by the A head and the B head, and the numbers written in the frames indicate the track numbers.

The track forming signal output from the track forming signal generating circuit 29 is supplied to a track forming control circuit 31. This track formation control circuit 31
Controls the rotation phase of the rotating drum 30 and
The timing of supplying recording signals to the head and the B head is controlled. In this embodiment, since the average code generation amount of one frame corresponds to one track, the rotating drum 3
The case where the number of rotations of 0 is 900 rpm will be described. However, the average generated code of one frame may be recorded on c tracks (c is a positive integer) by c magnetic head scans, and the rotation speed of the rotating drum 30 may be set to a different rotation speed such as 1800 rpm.

Next, a description will be given of a code permutation method used in this embodiment to enable high-speed reproduction of a VTR. First, multiplexers 37 combine the respective signals obtained by passing the color signals U and V supplied to the input terminals 32 and 33 through the decimators 34 and 35 and the luminance signal Y supplied to the input terminal 36. The input video signal is supplied to the subtraction circuit 12 and the motion evaluation circuit 13, and the variable length coding circuit 16 outputs a band-compressed video code.

Here, in the conventional band compression system shown in FIG. 24, the video signal is transmitted after being coded in a variable length manner, and as shown in FIG. Is different. FIG.
The NMP signal shown in (h) indicates a switching point of a frame of the video signal. Conventionally, 2640 superblocks exist in one frame, and the 2640 superblocks are included in one frame period indicated by the NMP signal in FIG.

Conventionally, four macroblocks exist in a horizontal direction on one screen, and these macroblocks are composed of 11 super blocks. In addition, one superblock in a macroblock per frame forcibly uses intra-frame processing. The sequence for forcibly using the intra-frame processing is included in the system control signal of FIG. Here, the super block for which the intra-frame processing is forcibly performed is referred to as a refresh block, and the super block for which the intra-frame processing is not forcibly performed is referred to as a non-refresh block.

In other words, as a definition of the term, refresh block: When the intra-frame processing is forcibly performed one super-block at a time in one frame period among the macro blocks, the super-block which has performed the intra-frame processing is called a refresh block. Since a macro block is composed of 11 super blocks, 1
Intra-frame processing is forcibly performed in one frame cycle. Non-refresh block: A super block other than the above-described refresh block. In this super block, there are a block that has undergone intra-frame processing and a block that has performed inter-frame processing, depending on the contents of an image. For example, when a scene change or the like occurs in an input video signal, in-frame processing may be used, but this is also a non-refresh block.

Here, there are 240 refresh blocks (= 2640 ＝ 11) in one frame period. Therefore, conventionally, there are 240 refresh blocks in one frame period shown in FIG. 2H, as shown in FIG. 2G. Then, the conventional signal is directly used as VT
When recording with R, the position of the refresh block cannot be determined, and high-speed reproduction cannot be performed as described above.

FIGS. 3A and 3B show video signals of frame numbers F ₅ and F ₆ , respectively. In the figure, the portions indicated by G ₅ and G ₆ indicate refresh blocks, and the portions indicated by H ₅ and H ₆ indicate non-refresh blocks. Thereafter, between the frame number, the refresh block number, and the non-refresh block number, the refresh block number of the frame having the frame number F _n (n is an integer) is G _n , and the non-refresh block number is H _n .

In the present invention, the arrangement of the refresh blocks and the non-refresh blocks on the track is made different.

This embodiment shows a case where one track is divided into ten parts for recording. When one track is divided into ten, high-speed reproduction can be performed up to 10 times speed. At the time of high-speed reproduction of 11 times or more, all the refresh blocks cannot be reproduced, and thus, as in the diagram shown in FIG. 31D, an area where an image cannot be formed occurs. If it is desired to realize high-speed reproduction of 20 times speed as a VTR specification, one track may be divided into 20. Furthermore, when it is desired to realize fast high-speed reproduction, refresh blocks may be arranged at equal intervals on a track.

FIG. 2E shows a timing pulse for dividing one track into ten parts. One track period shown in FIGS. 2B and 2C is equally divided into ten parts.
The divided one period is called a sector.

In other words, as a definition of the word, a sector: 1 track period is almost equally divided by d (in this case, 1
0) Refers to the divided period.

In this embodiment, as shown in FIG. 2F, 24 refresh blocks are put in one sector. In this case, since one track includes 10 sectors, 240 refresh blocks are inserted in one track, which is equal to the number of refresh blocks in one frame of the video signal. That is, the number e of refresh blocks included in one sector is defined as b, where b is the number of super blocks in which intra-frame processing is periodically performed.
If b intra-frame processing signals are recorded on c tracks, e = b / c × d (in this case, 240/1 × 10
= 24).

By performing the code exchange as described above, the refresh block for one frame is arranged in one frame period indicated by the NMP signal in the related art, but the refresh block for one frame is arranged in one track period. It can be arranged to be present.

FIG. 4 shows a track pattern. That is, the tracks T _{1 to} T ₁₁ on the magnetic tape 26
G ₁ was filled in the frame of ~G ₁₁ corresponds to the refresh block number G _n described above. The relationship between the refresh blocks and the track T _n is the number in the track T _n G
The relationship is that _n refresh blocks are recorded. Further, H ₁ to H ₁₁ filled out in the frame of the track T ₁ through T ₁₁ are non-refresh block number H mentioned above
Corresponds to _n . The switching point of the non-refresh block is a thick line portion shown in the frame of the tracks T _{1 to} T ₁₁ .

Track 38 in FIG. 4 shows the relationship between the sector and the track. The track 38 is divided into 10 and d =
It is divided into ten sectors. In this one sector,
e = 24 refresh blocks are arranged. The non-refresh block is inserted while the refresh block is arranged.

[0042] Here, if the track T _5, T ₆ will be described in detail as an example, the track T ₅ to record refresh blocks G ₅ of the frame F _5. Also, track T
The ₆ records the refresh block G ₆ of the frame F _6. A non-refresh block is recorded in the empty portion where the refresh block is arranged. The track T ₅ records non refresh block H _5, H _6, the track T ₆ records the non-refresh block H _6, H _7.

Therefore, in order to realize the above-mentioned recording mode, the video code subjected to the band compression encoding obtained from the variable length encoding circuit 16 in FIG. 1 is supplied to the code exchanging circuit 39 again. The refresh block control circuit 40 generates a code position signal of the above-described refresh block. The code position signal is supplied to the code replacement circuit 39. The code permutation circuit 39 rearranges refresh blocks and non-refresh blocks based on the input video code and code position signal.

That is, a process of inserting 24 refresh blocks into each of 10 sectors provided in one track is performed. This processing is realized by temporarily storing codes in a memory (not shown) and reading the codes from the memory so that 24 refresh blocks are included in one sector.

The output of the transposition circuit 39 is
It is supplied to the index insertion circuit 41. The index insertion circuit 41 inserts an index signal into the control data section of each sector so that it can be detected at the time of reproduction that a non-refresh block is partially separated and recorded. The index signal is prepared by an index generation circuit 42 to which a code position signal from the refresh block control circuit 40 is supplied. Then, the output of the index insertion circuit 41 is
The data is supplied to the A head and the B head via the multiplexer 43 and is recorded on the magnetic tape 26.

In the case where the refresh block and the non-refresh block are exchanged in the decoder, the PCM / DPC of the head data existing at the head of the macroblock inside the video code shown in FIG.
The refresh sequence code included in the M determination code and the system control signal may be detected and used as an output signal of the refresh block control circuit 40.

FIGS. 5A and 5B show trace loci X _{1 to} X ₁₁ of the head during 2 × speed reproduction. Note that within the framework of each track T ₁ through T _22, refresh similar to FIG. 4 blocks G _n and non-refresh block H
Indicates _n . In the head trace at the time of double speed reproduction shown in FIG. 5, reproducible refresh blocks are shown in FIGS. 6 (a) to 6 (h) and 7 (a) to 7 (c). FIGS. 6A to 6H and FIGS.
Frames 1 to 11 shown in (c) correspond to frames 2 to 11 shown in FIG.
Speed indicates playable refresh block at a head trace loci X ₁ to X ₁₁ at the time of reproduction.

[0048] In example frame 1, by performing the head trace X _1, displays a refresh block G1 in the upper half of the screen, it is possible to display the refresh block G ₂ in the lower half of the screen. Similarly, in frames 2 to 11, the refresh block G ₃
It is possible to play up to ~G _22. Therefore, if reproducible refresh blocks are accumulated in frames 1 to 11, codes in all screen areas can be reproduced as shown in FIG. 7D.

The codes subjected to the inter-frame processing and the codes subjected to the intra-frame processing according to the contents of the image are included between the codes subjected to the intra-frame encoding processing periodically. These codes have no correspondence between the image area and the recording medium area.

In the present invention, the correspondence between a image areas and d × c × f recording medium areas is 1: 1.
Or a 1: 2, 2: 1 correspondence,
Any correspondence may be used, such as a correspondence in which a blank is inserted in the area of the recording medium. The recording medium is not limited to the magnetic tape 26, but may be applied to a video disk. In this case, one round of the disk corresponds to one track of the tape.

High-speed reproduction can be performed by inserting a refresh block in a predetermined area on the track of the VTR, but it is necessary to prevent the code amount from exceeding the code amount recordable in the predetermined area.

The code amount of a predetermined refresh block is
If the recordable code amount in a predetermined area of the recording medium is exceeded, refresh is not performed at a position on the screen corresponding to the exceeded code.

Even if this is not avoided, since refresh is performed from a certain fixed position on the image, it is highly possible that the content of the image can be determined, but the refresh is performed more reliably. Requires control of the amount of code generated in the refresh block.

In this example, the code of the refresh block is divided into a plurality of parts, so that the low-frequency component of the refresh block or the MSB is stored in a predetermined area on the track of the VTR.
Insert the sign.

Therefore, the code amount of the refresh block will be described in detail.

The two-dimensional DCT circuit will be described.

First, the image is divided into small blocks (N × N) each including N pixels in the horizontal and vertical directions, and each block is subjected to two-dimensional DCT. The size of N at this time is set to 8 to 16 from the conversion efficiency. In this embodiment, N =
8 is used.

The transform coefficient of the two-dimensional DCT is given by Formula 1, and its inverse transform formula is given by Formula 2.

[0059]

(Equation 1) Here, F (0,0) represents a DC component coefficient,
(U, v) includes high frequency horizontal frequency components as u increases, and high frequency vertical frequency components as v increases.

First, the nature of the coefficient of the DC component of F (0,0) will be described. F (0,0) corresponds to a DC component representing an average luminance value in an image block, and its average power is usually considerably larger than other components.

Further, when the DC component is roughly quantized, noise (block distortion) peculiar to the orthogonal transformation that visually perceives large image quality deterioration occurs. Then, F (0,0)
Is assigned a large number of bits (usually 8 bits or more) and is equally quantized.

Next, the conversion coefficient F (u, v) excluding the DC component
State the nature of The average value of F (u, v) is given by Equation 1,
It becomes "0" except for the DC component F (0,0).

When a small number of bits are allocated to a small block of an image in order to perform efficient coding, a large number of bits are allocated to transform coefficients of low-frequency components, and conversely, By performing coding by allocating a small number of coding bits to the transform coefficient of the high-frequency component, it is possible to reduce deterioration in image quality and perform coding at a high compression rate.

The image is converted into a small block of 8 × 8 = 64 pixels consisting of 8 pixels in both the horizontal and vertical directions,
When the CT is performed, the converted coefficients for each frequency component are 8 × 8 = 64 two-dimensional coefficients as shown in FIG. In FIG. 8, the upper left is a DC coefficient (DC component). The other 63 are AC coefficients (AC components), and the spatial frequency increases toward the lower right. Since the AC component has a two-dimensional spread, it is converted to one-dimensional by zigzag scanning shown in the order of 0 to 63 upon encoding and transmission.

Here, the coefficients of the 64 DCTs are represented by DCT _i
It is represented by [i = 0 to 63].

The number of quantization bits for quantizing each pixel is often 8 bits in the case of an image signal.

In some cases, the DCT coefficient of the output obtained by subjecting the 8-bit pixel to DCT conversion is represented by 12 bits.

Next, quantization will be described.

The 64 DCT coefficients described above are linearly quantized with a different step size for each coefficient position, using a quantization table that defines a quantization step size for each coefficient.

Although there are two methods for setting the quantization step, they are basically the same.

The first method is a method of transmitting a code indicating a quantization table using a quantization table in which a quantization step is determined for each of 64 DCT coefficients.

FIG. 9 shows an example of the quantization table. In the figure, q = 0 to q = 9 are quantization table codes representing a quantization table, and the decoder can perform inverse quantization by transmitting this code.

The 64 numbers arranged in a square indicate the number of quantization bits, and have a correspondence with the 64 two-dimensional coefficients shown in FIG. For example, 7 in the upper left of the quantization table of q = 0 indicates that the DC component is quantized by 7 bits.

Hereinafter, each coefficient is similarly quantized by the number of bits indicated in the quantization table.

In the second method, first, 64 DCT coefficients are weighted using a weighting matrix.

Thereafter, the quantization width data QS (Quantize-S
This is a method in which each coefficient is uniformly divided and then quantized using cale). At the time of transmission, a code corresponding to the quantization width data is sent. The weight matrix has a default value. Furthermore, a specific type of weighting matrix can be transmitted.

As an example, MPEG. In I, 5 bits are assigned to the code of the quantization width data QS, and 32 types can be designated. Therefore, this value is referred to as QS _j [j
= 0-31].

Here, the quantization width data QS _{j is} defined.

The case of quantizing the DCT coefficient value with the maximum number of quantization bits is represented by j = 0, and QS ₀ = 1.

The case where the coefficient value of the DCT is not transmitted is represented by j = 31, and in this case, the number of quantization bits described later is QL ₃₁ = 0.

Here, j is referred to as a quantization level.

FIG. 10 shows MPEG. The default value of the weighting matrix of the luminance signal used in I is shown.

In the figure, 64 numbers of 8 × 8 are:
There is a correspondence with the 64 two-dimensional coefficients shown in FIG.
The weighting value for each DCT coefficient is shown.

In the encoder, each coefficient of the DCT is divided by the corresponding weight value and quantization width data QS.

The coefficients of the 64 DCTs are represented by DCT _i [i = 0
~ 63], and each value of the weighting matrix is represented by WEIG
HT _i [i = 0 to 63] Each value after quantization is represented by Q _i [i = 0 to
63]

[0086]

(Equation 2) Is represented by

The number of quantization bits at this time is

[0088]

(Equation 3) Is represented by

An example is shown below.

MPEG. I in the vertical direction of the luminance signal of I
The AC component is represented by DCT ₁ in FIG. 8 described above.

The value corresponding to DCT ₁ in the weighting matrix is WEIGHT ₁ = 16. This is shown in FIG.
Corresponds to the part marked with a circle. When the quantization width data QS ₀ = 1,

[0092]

(Equation 4) Since the coefficient of DCT _i is represented by 12 bits, log ₂ D
The maximum value of CT _i is 12. The number of quantization bits at this time is

[0093]

(Equation 5) Becomes

FIG. 11 shows the required maximum number of quantization bits after passing through the weighting matrix when QS ₀ = 1. This figure is a matrix representing 8 × 8 = 64 quantization bit numbers, and each number indicates the quantization bit number corresponding to each position of the DCT coefficient shown in FIG.

FIGS. 12 and 13 quantitatively show nine representative quantization tables among the quantization tables when 32 types of quantization width data QS _j are set.

In order to explain the case where the above-described second method regarding the quantization table is used, this table is based on the quantization width data QS.

Here, j = 31 is an example in which no data is generated, and corresponds to quantizing all coefficients with 0 bits. Also, j = 0 is the quantization width data QS ₀ = 1
Therefore, it is equivalent to quantization with a weighting table. That is, in this case, the bits are allocated by the weighting table shown in FIG.

In FIGS. 12 and 13, the horizontal axis represents DCT.
These 64 coefficients correspond to the order of the zigzag scan shown in FIG. The vertical axis is D
In each coefficient of CT, the number of bits to be transmitted is shown.

When quantizing DCT coefficients, M
From SB (Most Significant Bit) to LSB (Least Sign)
ificant Bit) is present. When limiting the number of bits to be transmitted, naturally, the MSB is transmitted with priority.

As described above, if the number of quantization bits for the DC component is reduced, block distortion and the like become conspicuous, so that the DC component is treated separately, and there is an example in which a fixed number of quantization bits is allocated. Here, it is assumed that 8 bits are allocated.

MPEG. In the case of the example of the luminance signal of I, the maximum value of the AC component is 8 bits as described above.

Referring to FIG. 12 and FIG. 13, the number of quantization bits and quantization width data will be quantitatively described.

The generated code amount is maximized when j = 0, and as j increases, the generated code amount decreases.
It becomes 0 at 31 and no sign is generated.

It is possible to control the amount of code generated by controlling the quantization width data.

There are two types of code amount control methods. The first method is a method of controlling the quantization level as described above. In this case, the generated code amount of the refresh block is suppressed, so that the image quality of the refresh block itself is deteriorated. However, in the next frame, the difference between the in-frame processing signal of the refresh block and the video signal of the next frame is sent, so that the image quality only drops momentarily.

The second method is to divide the code once quantized into two, and to determine the amount of code of the MSB or low-frequency component by VTR.
This is a method of reducing the amount of codes that can be read out at the time of high-speed reproduction on a recording medium such as this.

On the other hand, when special reproduction is realized using a refresh block on a recording medium such as a VTR, the refresh rate of the screen can be surely maintained at a constant cycle by controlling the code amount of the refresh block to a predetermined code amount. .

Regarding this, Japanese Patent Application No. 3-250671 is disclosed.
It is described in the issue.

There are the following two methods according to the technique of the special reproduction of the VTR.

The first method is a method using DTF as a VTR servo method.

When the maximum recording code amount that can be recorded on P tracks formed in one scan is α, and when a video signal is recorded by c head scans per frame, 1 / c of the video of one frame is recorded. It is necessary to keep the maximum code amount of the refresh block in the area at or below α.

The second method is a case where DTF is not used.

When the DTF is not used, the high-speed reproduction speed is i
In the case of (1), the area of 1 / i of the P tracks formed in one scan is traced.

As described above, when the maximum code amount that can be recorded on P tracks formed in one scan is α, and a video signal is recorded by c scans per frame,
It is necessary to keep the maximum code amount in the 1 / c × i area of the refresh block of one frame to α / i or less.

In this case, the case where an extremely wide head is not used as the special reproduction head is shown.

FIG. 14 is a diagram showing another embodiment of the present invention.

Although the present embodiment will be described using an example on the encoder side, it can also be realized in a decoder. In that case, it can be realized by extracting necessary signals from the output of the variable length decoding circuit of the decoder or from the inside.

First, the output signal of the quantization circuit 15 is passed through a zigzag scan circuit 44 and then input to a code arrangement circuit 45.

The zigzag scan circuit 44 rearranges 8 × 8 DCT coefficients by the scan method shown in FIG.

The purpose of the operation of the code arrangement circuit 45 is the same as that of the code replacement circuit 39 described with reference to FIG. 1, and the arrangement of the code is such that the refresh block signal is recorded in a predetermined area on the tape. is there.

Particularly, in the present embodiment, the code of the refresh block is divided so that the code amount that can be recorded in a predetermined area on the tape is reduced, and the code corresponding to the low-frequency component or the MSB component is recorded in the predetermined area. It is characterized by doing.

In the code arrangement circuit 45, the refresh block separation circuit 46 first performs a refresh block selection 46a and a non-refresh block selection 46b.

The non-refresh block 46b is subjected to variable-length coding by the variable-length coding circuit 47 and temporarily stored in the memory 48, as in the conventional example.

Refresh block code division circuit 49
Is a low frequency or MSB extraction circuit 49a and a high frequency or L
And an SB extraction circuit 49b. This output signal is stored in the memory 48 through the variable length coding circuits 50 and 51, respectively. In the low frequency or MSB extraction circuit 49a, VT
The low band of the refresh block or the MSB so that it falls within the code amount of the predetermined area to be reproduced during the special reproduction of R.
Is extracted. This extraction method will be described later in detail.

The memory 48 reads the code of the low-frequency component or the MSB component of the refresh block by exchanging the code so that special reproduction is possible.

Next, a method of dividing the code of the refresh block will be described.

First, the features of the conventional refresh block will be summarized. 1) The refresh block is a super block that has been forcibly subjected to intra-frame processing. 2) The super block includes eight luminance signal blocks and two chrominance signal blocks. The DC components of the eight luminance signal blocks are converted into DPCM and Huffman-coded. 3) The AC component of the luminance signal and the chrominance signal are zigzag scanned and Huffman coded.

The method of dividing the refresh block is 4
There are types.

This will be described with reference to FIGS.

The code of the non-refresh block is not divided and is processed in the same manner as in the conventional example.

FIGS. 15 to 18 show the respective coefficients obtained by arranging the DCT coefficients by zigzag scanning on the horizontal axis, similarly to FIGS. 12 and 13. The vertical axis indicates the number of bits used for quantization.

FIG. 15A, FIG. 16A, FIG.
7 (a) and FIG. 18 (a) show the number of quantization bits before code division. Here, a case where the quantization level j = 0 before division is shown.

The first method is a method of dividing a DC component and an AC component of a refresh block as shown in FIG.

That is, the code in FIG. 15A is divided into a DC component (FIG. 15B) and an AC component (FIG. 15C). Then, a code is transmitted so that the DC component (FIG. 15B) is recorded in the trick sector.

Here, words are defined. Trick sector: An area on a recording medium obtained by dividing a tape track into a plurality of sections is called a sector, and a sector to be played back during trick play is called a trick sector.

As a method of minimizing the change from the circuit of the conventional example, there is a method of recording only the DC component of the luminance signal in the trick sector.

The remaining codes shown in FIG. 15C are recorded in places other than the places where the codes in FIG. 15B are arranged.

Since the DC components of the conventional example are all quantized with the same bit, additional information indicating the number of quantization bits is not required.

If the code amount of the DC component of the refresh block exceeds the maximum recording code amount of the trick sector on the tape, the bit on the MSB side of the DC component is transmitted, and the additional information indicating the quantization level is transmitted. There are also transmission methods.

In the second method, a low-frequency component (FIG. 16B) and a high-frequency component (FIG. 16C) of the refresh block are used.
Is a method of dividing Non-refresh blocks are not divided.

In this case, the DC component of the refresh block and the AC component on the low frequency side as shown in FIG. 16B are recorded in the trick sector on the track, and the rest of the refresh block is recorded in other portions. The high-frequency component and the code of the non-refresh block are recorded.

In the non-trick sector, the AC component on the high frequency side of the refresh block and the code of the non-refresh block are recorded.

The low-frequency AC component shown in FIG.
The zigzag scan is performed halfway, after which a code of EOB (End of Block) indicating the end point of the block is forcibly inserted and transmitted as a code of one block.

In the example of FIG. 16B, the sign of EOB is inserted after the first to ninth coefficients of the DC and AC components of the zigzag scan.

Next, the AC on the high frequency side shown in FIG.
The components will be described. Here, since the component corresponding to the low-frequency component transmitted in FIG. 16B has already been transmitted,
The amplitude becomes 0. Therefore, after assigning the Huffman code indicating the number of consecutive 0s, Huffman coding is performed by indicating the number of consecutive 0s and the amplitude of the non-zero coefficient, as in the conventional example.

At the time of normal reproduction and slow reproduction, the low-frequency component of the refresh block recorded in the trick sector and the high-frequency component of the refresh block recorded elsewhere are combined to reproduce at high resolution. Get a picture.

In the synthesizing method, low-frequency components and high-frequency components of a refresh block are each subjected to Huffman decoding, and when performing an inverse zigzag scan, respective codes are arranged to obtain DCT coefficient values.

At the time of high-speed reproduction, a high-speed reproduction image is obtained by using the low-frequency component of the refresh block reproduced from the trick sector.

Since the high-frequency AC component is not used, the resolution falls, but there is no problem in locating the screen.

The third method is a method of recording the MSB side of a code in a trick sector.

In the conventional quantization table determination method, first, a weighting coefficient is multiplied, and then quantization width data is further multiplied. The quantization level j corresponding to the quantization width data is transmitted.

In this method, the code of the quantization level j = 0 shown in FIG.
After the transform coefficients of the DCT are obtained, a value having a large quantization level number j, that is, j for transmitting the MSB side at the time of quantization is set.

Here, as shown in FIG. 17 (b), the code having the input quantization level j = 0 is created with a code of j = 16 and recorded in the trick sector. Also, this quantization level j = 16 is recorded. This code corresponds to a code obtained by increasing the number of quantization levels and coarsely quantizing the content of an image. Thus, as can be seen by comparing FIG. 17A and FIG. 17B, the code at the quantization level j = 16 represents the MSB side of the code at the quantization level j = 0.

The code shown in FIG. 17C is a code corresponding to the difference between the quantization levels j = 0 and j = 16, and represents the LSB side of j = 0. This code is Huffman-coded.

17B except that the code of the quantization level j = 16 in FIG. 17B is recorded in the trick sector.
Record the code of (c).

At the time of normal reproduction and slow reproduction, the coarsely quantized code of FIG. 17B reproduced from the trick sector and the code of FIG.
By obtaining the signal (a), an image with less quantization noise is obtained.

At the time of special reproduction, a coarse and quantized code reproduced from a trick sector is output. Although a large amount of quantization noise is generated, it is possible to perform cueing in a VTR.

The fourth method is a method of recording a code on the MSB side in a low frequency band in a trick sector.

FIG. 18B shows the distribution of the number of quantization bits in the quantization table. As a quantization table for high-speed reproduction, a table is prepared for finely quantizing the low band and coarsely quantizing the high band.

Then, in the trick sector, a code (FIG. 18B) using a quantization table for high-speed reproduction is recorded.

The input code shown in FIG.
FIG. 18C shows the sign of the difference from FIG.

This code and the code of the non-refresh block are recorded at a position other than the position where the code of FIG. 18B for special reproduction is recorded.

By using such a quantization table, it is possible to suppress the amount of generated codes and to improve the image quality in the second place.
With this method, it is possible to obtain a slightly better image quality.

The encoding method is the same as that of the third method. A code is formed by the quantization bit number distribution shown in FIG. 18B, and is recorded in a trick sector. Further, FIG.
Huffman coding of the code shown in FIG.
Record in a place other than the place where the code was recorded.

As described above, the code of the refresh block is divided into the low band or the MSB component and the high band or the LSB component, and the low band or the MSB component is recorded in the trick sector. Since the refresh block is performed, the image quality of the special reproduction image can be improved.

Next, the device according to claim 4 will be described.

FIG. 19 is a diagram showing still another embodiment of the present invention.

In the figure, the same components as those of the conventional example include
The same numbers are given. In addition, although the present embodiment considers minimizing the difference from the conventional example, the minimum change is made.However, it is possible to variously change the block configuration without changing the gist of the present invention. Needless to say.

The gist of the present invention is to divide a refresh block to be subjected to intra-frame processing into the entire area of the screen at intervals of f frames and to reduce the amount of generated codes of low-band or MSB codes by VCR.
Or the like, or a predetermined code amount determined from the recording medium.

In order to realize this purpose, in the present embodiment, the code amount of the low band or the MSB code of the refresh block is calculated independently, and the division level of the refresh block is determined using this value. As described above, there are four types of code division methods, and in each of them, it is possible to control the amount of low-band or MSB code. The case of dividing into a band and a high band code will be described.

As the configuration, the refresh block code amount detection circuit 52, the refresh block low band code amount calculation circuit 53, and the refresh block division level setting circuit 54 are used as main components other than the above-described embodiment.

First, in each refresh block code amount detection circuit 52, a refresh block is input from the refresh block separation circuit 46, and the number of continuous 0-coefficients and the amplitude of non-zero coefficients of DCT coefficients of each block inside the refresh block are determined. To detect. The number of consecutive 0 coefficients and the amplitude of the non-zero coefficient are stored in a table as shown in FIG.
The data is input to the OM, and the code amount of each refresh block is calculated.

FIG. 20, which is also used in the conventional example, shows the amplitude of the non-zero coefficient on the horizontal axis and the number of consecutive 0 coefficients on the vertical axis. The number in the frame indicates the number of bits of the code. By adding the number of bits of this code,
The generated code amount can be calculated in block units or super block units.

By comparing the calculated code amount with the target low-band code amount of each refresh block, the division level is set by the refresh block division level setting circuit 54 and input to the refresh block code division circuit 49. The target low-band code amount of the refresh block may be a constant value.

Further, in order to improve the control accuracy of the low-band code amount, a refresh block low-band code amount calculation circuit 53 may be used.

The refresh block low band code amount calculation circuit 53 calculates the low band code amount of the refresh block in a predetermined period.

As a VTR servo, no DTF is used.
In the case where a video signal is recorded by c = 1 head scan per frame and i = 2 × speed is realized as a special reproduction speed, refreshing of 1 / c × i = １ ／ region of video of one frame is performed. A case where the code amount of a block is calculated will be described.

If the code amount of this refresh block is the maximum recordable code amount α that can be recorded on P tracks formed in one scan, the code amount of the refresh block in a half area of one frame is α / c. The division level is set by the refresh block division level setting circuit 54 so that × i = α / 2 or less.

FIG. 21 shows a setting method for setting the quantization level based on the output signal of the refresh block low band code amount calculation circuit 53. In this example, a case is described in which the head scan of the VTR is one scan and the average code amount of the video signal of one frame is recorded. Also, a case will be described in which the trick play speed is doubled. In the embodiment, since there are 240 refresh blocks per frame, 120 refresh blocks are recorded per sector. This will be described in detail.

FIGS. 22 (a) and 22 (b) show a refresh block in one screen and a dividing method when the refresh block is further divided. F _n shown in FIG. 22 in (a) shows the screen of the n-th frame. G _n indicates a refresh block in the n-th frame. This refresh block is 240
Exists. In addition, G shown on the left side of the screen
_n (0) and G _n (1) indicate refresh blocks obtained by equally dividing the 240 refresh blocks in the vertical direction. That is, G _n (0) indicates 120 refresh blocks existing above the screen among the G _n refresh blocks. G _n (1) is
It shows the refresh blocks in the lower area of the screen, and includes 120 refresh blocks.
FIG. 22B shows a refresh block of frame number F _{n + 1} , and the definitions of G _{n + 1} (0) to G _{n + 1} (1) are the same as those in FIG. .

Next, the track pattern of the VTR will be described. FIG. 23 shows a track pattern on the magnetic tape 26. T _{0 to} T ₁₁ indicate tracks recorded using the rotary head 30. Here, a case where the average generated code amount of one frame is recorded on one track will be described. That is, a case where c = 1 described above will be described. This corresponds to the case where b = 240 refresh blocks are recorded on one track. In other words, the refresh block G of the frame number F _n
n it will be recorded in the track T _n.

In this configuration, when performing double speed reproduction, the reproducing head crosses two tracks. Therefore, one track is divided into two equal parts.
While reproducing the area No. 2, a reproduction signal is obtained over two tracks. Here, if one divided portion is referred to as a sector, one track is formed per frame, so two sector numbers S ₀ and S ₁ are assigned as shown in FIG.

In general, an area obtained by dividing one track into substantially equal parts d is referred to as a sector.

In order to realize i-time high-speed reproduction, the head straddles i tracks, so that one track reproduces an area of 1 / i. Then, assuming that the highest high-speed reproduction speed is i _max , i _max ≦
Set to the relationship of d. Then, the sector names are S _{0 to} S _d-1.
Expressed by

Next, the relationship between a refresh block and a sector will be described. When recording the refresh block G _n of the frame number n in one track T _n, G _n (0)
.. S ₀ , G _n (1)... S ₁ are recorded.

Here, assuming that the number of refresh blocks included in one sector is evenly arranged, the number of refresh blocks included in one sector is as follows. That is, 1
Assuming that the number of refresh blocks per frame is b, the number of tracks for recording the b refresh blocks is c, the number of track divisions is d, and the number of refresh blocks within one sector is e, e = b / c × d. Become. That is, e = 240/1 × 2 = 120.

In FIG. 23, the head traces of X _{0 to} X ₄ represent the head trajectory at double speed. That is, in the head trace of X ₀ , the sector S ₀ of the track T ₀ (refresh block G ₀ (0)) and the sector S ₁ of the track T ₁ (refresh block G _0
1 (1)), indicating that sector S ₀ (refresh block G ₂ (0)) of track T ₂ can be reproduced.

Since the recording capacity that can be recorded in the sectors S ₀ and S ₁ of the recording medium on the tape is fixed,
Within this recording capacity, the refresh block G _n (0),
The generated code amount of G _n (1) must be suppressed.

In FIG. 21, the horizontal axis indicates the refresh block number. In the present embodiment, the refresh block number of sector 0 and the refresh block number of sector 1 are shown in order to record a refresh block of one frame in two sectors. Further, in this example, the recording code amount α / 2 of one sector is not exceeded in 120 refresh blocks.

The vertical axis of FIG. 21 indicates the code amount of the refresh block. The maximum code amount is α / 2 as described above.
Set to. Here, it is assumed that α / 2 = 250K bits. In FIG. 21A, a solid line A is a target low-band code amount of the refresh block, and the generated code amount is controlled so as not to exceed this line. Since the solid line A is an example for control, it does not need to be a straight line, and what is necessary is to suppress the generated code amount per sector to α / 2. A polygonal line B is a line indicating an example of a change in the accumulated amount of low-frequency code of the refresh block. This shows an output signal of the refresh block low band code amount calculation circuit 53. Refresh block low band target code amount (solid line A)
The division level is determined so as not to exceed.

Since the output signal of each refresh block code amount detection circuit 52 is input to the refresh block division level setting circuit 54, the refresh block target code amount is compared with the refresh block low band code accumulated code amount. It is possible to select a split table so as not to exceed.

Here, in the case where the low-frequency code and the high-frequency code are divided as shown in FIG. 16, a position for dividing the zigzag scan coefficients for determining the division level is determined when sequentially scanning.

This will be described in detail with reference to FIG.

FIG. 21 (b) is an enlarged view of the horizontal axis of FIG. 21 (a). Refresh block number 80 to 8
How to determine the division level into 1 will be described with reference to FIG. First, it is assumed that the code amount up to the refresh block number 80 has been calculated from the refresh block low band code amount calculation circuit 53, and the code amount is indicated by C in FIG. 21B. It is also assumed that the target code amount is determined by the refresh block number, and the refresh block number 81 has the code amount indicated by D in FIG. 21B.

Since the signal of the coefficient obtained by DCT of the refresh block is input to the refresh block division level setting circuit 54 as the output signal of each refresh block code amount detection circuit 42, the generated code amount can be calculated.

Zigzag scan numbers ω = 6, 7, 8, 9 corresponding to refresh block division levels (FIG. 8)
Assuming that the code amount on the low-frequency side becomes E to H in FIG. 21B, the code amount ω = 7 of the generated code of F which does not exceed the target value D is selected.

As a result, the amount of low-frequency code of the refresh block can be controlled to the amount of code included in the trick sector, so that high image quality can be obtained even during high-speed reproduction.

It should be noted that the present invention is not limited to the above embodiments, but can be implemented in various modifications without departing from the spirit and scope of the present invention.

[0199]

As described in detail above, according to the present invention,
It is possible to provide an extremely good band compression processing device that can easily obtain a good reproduced image at the time of high-speed reproduction.

[Brief description of the drawings]

FIG. 1 is a block diagram showing an embodiment of a band compression processing apparatus according to the present invention.

FIG. 2 is a timing chart shown for explaining the operation of the embodiment.

FIG. 3 is a diagram showing a relationship between refresh blocks and non-refresh blocks of frame numbers F ₅ and F _{6 in} the embodiment.

FIG. 4 is a view showing a track pattern in the embodiment.

FIG. 5 is a diagram showing a head trace trajectory during double-speed playback in the embodiment.

FIG. 6 is an exemplary view showing reproducible refresh blocks of frames 1 to 8 in the embodiment.

FIG. 7 is a view showing refreshable refresh blocks of frames 9 to 11 and refresh blocks in which 11 frames are stored in the embodiment.

FIG. 8 is a diagram showing a scan order when zigzag scanning DCT coefficients.

FIG. 9 is a diagram showing an example of a quantization table.

FIG. 10 is a diagram showing an example of a weighting table.

FIG. 11 is a diagram showing an example in which the weighting table is converted into the number of bits.

FIG. 12 is a diagram showing the number of bits generated by a quantization table.

FIG. 13 is a diagram showing the number of bits generated by a quantization table.

FIG. 14 is a block diagram showing another embodiment of the present invention.

FIG. 15 is a diagram showing division of codes in the embodiment.

FIG. 16 is a diagram showing division of codes in the embodiment.

FIG. 17 is a diagram showing division of codes in the embodiment.

FIG. 18 is a view showing division of codes in the embodiment.

FIG. 19 is a block diagram showing still another embodiment of the present invention.

FIG. 20 is a diagram showing a code amount of the embodiment.

FIG. 21 is a view showing the operation of the embodiment.

FIG. 22 is a diagram showing a relationship between refresh blocks and non-refresh blocks of frame numbers F ₅ and F _{6 in} the embodiment.

FIG. 23 is a view showing a track pattern of the embodiment.

FIG. 24 is a block diagram showing a conventional band compression system.

FIG. 25 is a view showing a format of a signal transmitted from the conventional system.

FIG. 26 is a diagram showing refresh blocks that can be reproduced from frames 1 to 8 during normal reproduction in the conventional system.

FIG. 27 is a diagram showing reproducible refresh blocks of frames 9 to 11 and refresh blocks in which 11 frames are accumulated during normal reproduction in the conventional system.

FIG. 28 is a view showing a track pattern in the conventional system.

FIG. 29 is a diagram showing a head trace locus at the time of double speed reproduction in the conventional system.

FIG. 30 is a diagram showing reproducible refresh blocks of frames 1 to 8 during double speed reproduction in the conventional system.

FIG. 31 is a view showing reproducible refresh blocks of frames 9 to 11 and refresh blocks in which 11 frames are accumulated in double speed reproduction in the conventional system.

[Explanation of symbols]

11 input terminal, 12 subtraction circuit, 13 motion estimation circuit, 14 DCT circuit, 15 quantization circuit, 16 variable length coding circuit, 17 FIFO circuit, 18 output terminal,
19: inverse quantization circuit, 20: inverse DCT circuit, 21: addition circuit, 22: frame delay circuit, 23: motion compensation circuit,
24, 25 switch, 26 magnetic tape, 27 input terminal, 28 SYNC signal detection circuit, 29 track formation signal generation circuit, 30 rotating drum, 31 track formation control circuit, 32, 33 input terminal, 34, 35 ... decimator, 36 ... input terminal, 37 ... multiplexer, 38
... Track, 39 ... code replacement circuit, 40 ... refresh block control circuit, 41 ... index insertion circuit
42 ... index generation circuit, 43 ... multiplexer,
44: zigzag scan circuit, 45: code arrangement circuit, 4
Reference numeral 6: refresh block separating circuit, 47: variable length coding circuit, 48: memory, 49: refresh block code division circuit, 50, 51: variable length coding circuit, 52: refresh block code amount detection circuit, 53: refresh Block low band code amount calculation circuit, 54... Refresh block division level setting circuit.

──────────────────────────────────────────────────続 き Continued on the front page (58) Field surveyed (Int.Cl. ⁷ , DB name) H04N 5/91-5/956 H04N ^7/ 24-7/68 G11B 20/10-20/12

Claims (6)

(57) [Claims] 1. A frame obtained by forming a image area (a is a positive integer) in a video signal of one screen and performing an intra-frame encoding process on the video signal using information in the frame. An intra-processed signal and an inter-frame processed signal that has been subjected to inter-frame encoding using the difference information between frames are created. After the intra-frame encoding, the inter-frame encoding is performed. A band compression unit that adaptively repeats a processing method according to a motion evaluation of an input video signal; and b frames out of the a regions in each of f frames (f is an integer of f ≧ 2). A refresh coding processing means for periodically performing the intra-frame coding process on the signal in the image area; a circuit for calculating a generated code amount of the refresh block having been subjected to the refresh coding process; Tsu so as not to exceed the predetermined maximum code amount shoe block, dividing the code of a refresh block into a plurality of code divided into a plurality of low-frequency component or the quantization bit MSB
A band compression processing device for recording the code of (b) in a predetermined area. 2. The signal processing means having the code amount control means for a refresh block is provided in a magnetic recording / reproducing apparatus, and the predetermined maximum code amount is one of the heads.
2. The band compression processing apparatus according to claim 1, wherein the recording code amount is a recording code amount α of a P track formed by scanning. 3. An apparatus for recording a high-speed reproduction speed i (i is a positive integer), a high-speed reverse reproduction speed k = 2-i, and recording an average code amount per frame by c scan.
For the recording code amount α per scan of the head, α / c
2. The band compression processing apparatus according to claim 1, wherein the generated code amount of b / c.times.i refresh blocks out of said b blocks is suppressed within the maximum code amount of .times.i. 4. A frame in which a (a is a positive integer) image area is formed in a video signal of one screen, and the video signal is subjected to an intra-frame encoding process using information in the frame. An intra-processed signal and an inter-frame processed signal that has been subjected to inter-frame encoding using the difference information between frames are created. After the intra-frame encoding, the inter-frame encoding is performed. Band compression means for adaptively repeating the processing method according to the motion evaluation of the input video signal; and b frames out of the a regions for each frame with f frames (f is an integer of f ≧ 2) A refresh coding processing means for periodically performing the intra-frame coding process on the signal in the image area; a circuit for calculating a generated code amount of the refresh block having been subjected to the refresh coding process; In Tsu shoe block, so as not to exceed a predetermined maximum code amount,
The code of the refresh block is divided into a plurality of parts, and the MSB of a low-frequency component or a quantized bit among the divided codes.
A band compression processing apparatus characterized in that the code amount of a refresh block is controlled and divided so that the code amount of the refresh block does not exceed a predetermined maximum code amount for a predetermined number of refresh blocks. 5. A signal processing means having said refresh block code amount control means is provided in a magnetic recording / reproducing apparatus, and said predetermined maximum code amount is one of a head.
5. The band compression processing apparatus according to claim 4, wherein the recording code amount is a recording code amount α of a P track formed by scanning. 6. An apparatus for recording a high-speed reproduction speed i (i is a positive integer), a high-speed reverse reproduction speed k = 2-i, and recording an average code amount per frame by c scan.
For the recording code amount α per scan of the head, α / c
5. The band compression processing apparatus according to claim 4, wherein the generated code amount of b / c * i refresh blocks of the b blocks is suppressed within the maximum code amount of * i.