JP3184011B2 - Band compression signal processor - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an apparatus for converting a video signal or the like into a digital signal and performing band compression by combining intra-frame coding and inter-frame coding.
When the output signal is recorded on a tape in a helical scan system and transmitted to a recording / reproducing apparatus for reproducing the same, a good reproduced image can be easily obtained, particularly at the time of high-speed reproduction. In addition, the present invention relates to a device which can record a wideband signal such as a high definition TV for a long time.

[0002]

2. Description of the Related Art As is well known, in digitally transmitting a video signal, band compression is performed by a transmission method using a variable length coding system, or by combining intra-frame coding and inter-frame coding. Transmission methods and the like are being studied. Among these, the technology of performing band compression by combining intra-frame encoding and inter-frame encoding and transmitting the data is disclosed in, for example, the document IEEE Trans.on Broadcasting.
Woo Paik described in Vol.36 No.4 DEC 1990: “Digit
al compatible HD-TV Broadcast system ", which is a band compression technique, and its characteristic portion will be described below. In FIG. 59, the video signal input to the input terminal 11 is And a motion evaluation circuit 13. The subtraction circuit 12 performs a subtraction process described later, and outputs the result to a DCT (discrete cosine transform) circuit 14. The DCT circuit 14 is connected to a horizontal direction. 8 pixels, 8 images in the vertical direction are unit blocks (8 × 8
(Pixels = 64 images), and outputs coefficients obtained by converting the pixel array from the time domain to the frequency domain. And
Each coefficient is quantized by the quantization circuit 15. in this case,
The quantization circuit 15 has 32 types of quantization tables, and individual coefficients are quantized based on the selected quantization table. The quantization circuit 15 is provided with a quantization table so that the amount of generated information and the amount of transmitted information fall within a certain range.

[0003] The coefficient data output from the quantization circuit 15 is subjected to a high-frequency zigzag scan from a low frequency to a high frequency for each unit block.
6 and is subjected to variable-length coding with a set of a subsequent number of zero coefficients (run length) and a non-zero coefficient. The encoder is a variable-length encoder having a different code length depending on the frequency of occurrence of Huffman codes or the like. Then, the variable-length coded data is input to a FIFO (first-in first-out) circuit 17 and is read out at a specified speed. [Control signal, audio data, synchronization data (SYN
C), multiplex NMP and the like, which will be described later], and send it out to the transmission path. The FIFO circuit 17 serves as a buffer for absorbing the difference between the generated code amount and the transmitted code amount because the output of the variable length coding circuit 16 is a variable rate and the transmission line rate is a fixed rate. .

The output of the quantization circuit 15 is input to an inverse quantization circuit 19 and inversely quantized. Further, the output of the inverse quantization circuit 19 is input to the inverse DCT circuit 20 and returned to the original signal. This signal is input to the frame delay circuit 22 via the addition circuit 21. The output of the frame delay circuit 22 is supplied to a motion compensation circuit 23 and the motion evaluation circuit 13, respectively. Motion evaluation circuit 13
Is the input signal from the input terminal 11 and the frame delay circuit 2
2 to detect the overall motion of the image, and control the phase position of the signal output from the motion compensation circuit 23. In the case of a still image, compensation is performed so that the original image matches the image one frame before. The output of the motion compensation circuit 23 can be supplied to the subtraction circuit 12 via the switch 24, and can also be fed back from the addition circuit 21 to the frame delay circuit 22 via the switch 25.

Next, the basic operation of the above system will be described. The basic operation of this system includes an intra-frame encoding process and an inter-frame encoding process. The intra-frame encoding process is performed as follows. When this process is performed, the switches 24 and 25 are both off. The video signal at the input terminal 11 is converted from the time domain to the frequency domain by the DCT circuit 14 and quantized by the quantization circuit 15. This quantized signal is output to the transmission path via the FIFO circuit 17 after being subjected to the variable length encoding process. The quantized signal is supplied to an inverse quantization circuit 19
The signal is returned to the original signal by the inverse DCT circuit 20 and is delayed by the frame delay circuit 22. Therefore, at the time of the intra-frame encoding processing, it is equivalent to the information of the input video signal being subjected to variable-length encoding as it is. This intra-frame processing is performed at appropriate intervals in scene changes of the input video signal and in predetermined blocks. The processing in the periodic frame will be described later.

Next, an inter-frame encoding process will be described. When the inter-frame encoding process is performed, the switches 24 and 25 are both turned on. Therefore, a signal corresponding to the difference between the input video signal and the video signal one frame before is obtained from the subtraction circuit 12. This difference signal is
The signal is input to the DCT circuit 14, converted from the time domain to the frequency domain, and then quantized by the quantization circuit 15. Further, since the difference signal and the video signal are added to the frame delay circuit 22 by the addition circuit 21 and input,
A predicted video signal that predicts the input video signal from which the difference signal is generated is generated and input.

FIG. 60 shows a line signal in a state where a video signal of a high-definition television signal is subjected to the intra-frame processing and the inter-frame processing as described above, and is transmitted on a transmission path. This signal is a signal of a transmission line, and is shown in a state where a control signal, an audio signal, a synchronization signal (SYNC), a system control signal, an NMP, and the like are multiplexed. FIG. 60A shows a signal on the first line, and FIG. 60B shows a signal on the second and subsequent lines. If this video signal has been processed in a frame, a normal video signal can be obtained by performing inverse conversion. However, in the case of a video signal that has been subjected to an inter-frame encoding process, even if this signal is inversely transformed, only a difference signal is reproduced. Therefore, a normal video signal can be reproduced by adding the video signal (or predicted video signal) reproduced one frame before to this difference signal.

[0008] According to the above system, the signal processed in the frame has all information variable-length coded, and the signal processed in the inter-frame after the next frame transmits the difference information, and This means that compression has been achieved.

Next, the definition of a set of pixels to be processed by the above band compression system will be described. That is, a block is an area of 64 pixels composed of 8 pixels in the horizontal direction and 8 pixels in the vertical direction. Super block: A region composed of four blocks in the horizontal direction and two blocks in the vertical direction of the luminance signal. This area includes one block each of the color signals U and V.
Further, the image motion vector obtained from the motion evaluation circuit 13 is included in a super block unit. Macro block: 11 super blocks in the horizontal direction. When a code is transmitted, the DCT coefficient of the block is converted into a code determined by the number of consecutive zero coefficients and the amplitude of the non-zero coefficient, and transmitted as a set. Finally, an end-of-block signal is added. Then, the motion vector of the motion correction performed in units of super blocks is added and transmitted in units of macro blocks.

[0010] The transmission signal shown in FIG.
Particularly relevant matters will be further explained. First
The line synchronization (SYNC) signal indicates a frame synchronization signal in the decoder, and all the timing signals of the decoder are generated using one synchronization signal per frame. The NMP signal on the first line indicates the number of video data from the end of this signal to the beginning of the macroblock of the next frame. This is because the code is configured by adaptively switching between the intra-frame encoding process and the inter-frame encoding process, so that the code amount of one frame is different for each frame, and the code position is different. It is to come. Therefore, the position of the code corresponding to one frame is indicated by the NMP signal.

As a countermeasure when the user changes the channel, periodic intra-frame processing is performed. That is, in this band compression system, as described above, the eleven super blocks in the horizontal direction are called macroblocks, and there are 44 super blocks in one screen in the horizontal direction. That is, there are a total of 240 macroblocks in one frame, including 4 macroblocks in the horizontal direction and 60 macroblocks in the vertical direction. In this band compression system, FIGS. 61 (a) to 61 (h)
As shown in FIGS. 62 (a) to 62 (c), refreshing is performed for each column of a superblock in units of four macroblocks, and all superblocks are refreshed every 11 frames. That is, as shown in FIG. 62D, by storing 11 frames of refreshed super blocks, intra-frame processing is performed in all regions.
For this reason, for example, during normal reproduction of a VTR (video tape recorder) or the like, the above-described intra-frame processing is performed at a period of 11 frames, so that a reproduced image can be viewed without any problem.

Note that head data is inserted at the head of the macroblock. This head data includes
A motion vector, a field / frame determination, a PCM / DPCM determination, a quantization level, and the like of each superblock are inserted together.

By the way, the above-mentioned band compression system includes:
It is used as an encoder for band compression of a television signal, and its decoder is used on the receiving side. Here, it is considered that the transmission signal is recorded on a VTR.
A general VTR is a method in which a video signal of one field is converted into a fixed-length code, a certain amount of information is generated, and recorded on X tracks (X is a positive integer).

On the other hand, if it is attempted to record and reproduce on a VTR using the transmission signal obtained by the above band compression system as it is, the variable-length code is used as it is for the intra-frame processing and inter-frame processing code. The position where the code processed in the frame is recorded is not fixed, and blocks that are not refreshed are generated at the time of high-speed reproduction.

More specifically, FIG. 63 shows a track pattern in the case where the signal which has been subjected to the variable length encoding as described above is helically recorded on the magnetic tape 26. In the track patterns T _{1 to} T ₁₁ , the portions indicated by thick lines indicate the switching positions of the frames F _{1 to} F ₁₁ . The switching position of the frame F ₁ to F ₁₁ are not aligned is that the recording data is created by the variable-length code. When the magnetic tape 26 is normally reproduced by a VTR, all the track patterns T _{1 to} T ₁₁ are sequentially scanned by a magnetic head. Video signals can be reproduced. That is, at the time of normal reproduction, all of the codes processed on the intra-frame and the codes processed on the inter-frame, which are recorded on the magnetic tape 26, can be reproduced, so that an image can be formed using all the codes.

However, in a VTR, there are cases where only a limited number of tracks are reproduced, for example, in a double speed reproduction mode in special reproduction. At this time, the magnetic head jumps the track and picks up the recording signal. In this case, there is no problem if the tracks of the signal subjected to the intra-frame encoding processing are successively reproduced, but if the track subjected to the inter-frame encoding processing is reproduced, only an image based on the difference signal is obtained.

FIG. 64 shows trace loci X _{1 to} X ₁₁ of the magnetic head when performing double speed reproduction. FIG.
In FIG. 4, since the signals subjected to the intra-frame encoding processing are dispersedly recorded in the frames F _{1 to} F ₂₄ , respectively, the position of the intra-frame processing portion reproduced on the screen is undefined. FIGS. 65 (a) to (h) and FIGS. 66 (a) to (c) show in-frame processed signals that can be reproduced at 2 × speed reproduction. And these 1
When one frame is accumulated, as shown in FIG.
There is no code that has undergone periodic intra-frame processing, that is, there is a portion where a refreshed super block does not exist, and a portion where a reproduced image cannot be formed occurs.

[0018]

As described above, the helical scan recording / reproducing apparatus provided with the conventional band compression system has a problem that high-speed reproduction such as double-speed reproduction becomes difficult.

Therefore, the present invention has been made in view of the above circumstances, and has as its object to provide an extremely good band compression signal processing apparatus capable of easily obtaining a good reproduced image at the time of high-speed reproduction. It is another object of the present invention to provide an apparatus capable of recording a wideband signal such as a high definition TV for a long time.

[0020]

According to the present invention, there is provided a band compression signal processing apparatus comprising: a number (a) for forming one frame;
Means for forming the image area of the positive integer), the image of successive
For the video signal set in the image, the video signal of the current image is
Interframe coding using difference between predicted image and video signal
An inter-frame coded signal configured by
Intra-frame encoding of video signal using intra-frame information
Using an intra-frame coded signal
Video signal with a period of f frames (f is an integer of f ≧ 2)
Is refreshed by intra-frame encoding
Means for generating a scheduled transmission during a normal transmission period.
In order, from the band compression encoder,
Fresh signal, inter-frame coded signal and in-frame
Means for outputting a coded signal transmission, after transmission, the output
Refresh signal, inter-frame coded signal and frame
Means for inputting an intra-system encoded signal to a band compression decoder
If, means for obtaining a decoded picture, the decoded
When recording the signal with the recording means, it is set for each frame.
Of each of the c regions (c is an integer of a ≧ c ≧ 0)
Each of the c areas on the frame
And means for adding an address signal indicating the position of les, 1
Refresh signal for one image area, inter-frame coded signal
Signals and intra-frame coded signals in a predetermined transmission order.
During high-speed playback processing that allows transmission
Means to indicate special playback mode using lag
And refresh in accordance with the address signal in the scheduled order.
Refresh signal to the band compression decoder that displays the
Address signal indicating the position on the frame with the signal
Means for inputting a flag on the recording medium.
When recording and playing back the decoded signal
When transmitting signals, high-speed playback mode and high-speed reverse playback mode
Signal processing for instructing special playback mode including
Is to be generated by

[0021]

[0022]

SUMMARY OF] According to the above configuration, since the obtained accurately fast intraframe coding signal at the time of reproduction, it is possible to obtain a good reproduced image.

[0023]

Embodiments of the present invention will be described below in detail with reference to the drawings. The new configuration is indicated by a double frame in the block diagram. 1. Basic Configuration FIG. 1 is a diagram showing a basic configuration in the present invention.

To the video input terminals 27, 28 and 29, a luminance signal Y and color signals U and V of a high quality TV or the like are inputted.

After performing necessary pre-processing on these signals, a block having a pixel configuration described later in Chapter 2 is formed by the blocking circuit 30 and input to the input terminal 11.

The video signal input to the input terminal 11 is supplied to a subtraction circuit 12 and a motion evaluation circuit 13, respectively. In the subtraction circuit 12, a subtraction process described later is performed, and the output thereof is supplied to a DCT (discrete cosine transform) circuit 14.
Is input to The DCT circuit 14 has 8 pixels in the horizontal direction and 8 pixels in the vertical direction as a unit block (8 × 8 pixels = 64 pixels).
And outputs a coefficient obtained by converting the pixel array from the time axis domain to the frequency domain. Then, each coefficient is quantized by the quantization circuit 15. In this case, the quantization circuit 15
Has 10 or 32 types of quantization tables, and individual coefficients are quantized based on the selected quantization table. The quantization circuit 15 is provided with a quantization table so that the amount of generated information and the amount of transmitted information fall within a certain range.

The coefficient data output from the quantization circuit 15 is zigzag-scanned from the low band to the high band for each unit block and extracted.
6 and is subjected to variable-length coding with a set of a subsequent number of zero coefficients (run length) and a non-zero coefficient. The encoder is a variable-length encoder having a different code length depending on the frequency of occurrence of Huffman codes or the like. Then, the variable-length coded data is input to a FIFO (first-in first-out) circuit 17 and is read out at a specified speed. [Control signal, audio data, synchronization data (SYN
C), multiplex NMP and the like, which will be described later], and send it out to the transmission path. The FIFO circuit 17 serves as a buffer for absorbing the difference between the generated code amount and the transmitted code amount because the output of the variable length coding circuit 16 is a variable rate and the transmission line rate is a fixed rate. .

The output of the quantization circuit 15 is input to the inverse quantization circuit 19 and inversely quantized. Further, the output of the inverse quantization circuit 19 is input to the inverse DCT circuit 20 and returned to the original signal. This signal is input to the frame delay circuit 22 via the addition circuit 21. The output of the frame delay circuit 22 is supplied to a motion compensation circuit 23 and the motion evaluation circuit 13, respectively. Motion evaluation circuit 13
Is the input signal from the input terminal 11 and the frame delay circuit 2
2 to detect the overall motion of the image, and control the phase position of the signal output from the motion compensation circuit 23. In the case of a still image, compensation is performed so that the original image matches the image one frame before. The output of the motion compensation circuit 23 can be supplied to the subtraction circuit 12 via the switch 24, and can also be fed back from the addition circuit 21 to the frame delay circuit 22 via the switch 25.

Next, the basic operation of the above system will be described. 2. Pixel Configuration A signal input to the input terminal 11 collects a plurality of effective pixels in one screen to form a block, a super block, and a macro block. This configuration is compatible with DigiCipher
Of MPEG, DSC-HDT
It goes without saying that the block configuration used in the V: Zenith + ATT system or the like may be used.

The definition of the block configuration will be described with reference to FIG.

One screen: FIG. 2A is composed of 1050 scanning lines and is interlaced.

The effective pixels are composed of 1408 pixels in the horizontal direction and 960 pixels in the vertical direction.

A video signal of one screen is processed by four processors.

FIG. 3 shows one screen and a super block address (hereinafter, abbreviated as SBA = Super Bro-ck Address).
The relationship is shown below.

There are 44 superblocks in the horizontal direction and 60 superblocks in the vertical direction. Therefore, there are 2640 super blocks in one screen. The address S.P. B. Assign A.

Assuming that the superblock address in the horizontal direction is x and that in the vertical direction is y. B. A = 60 × x + y

Block: As shown in FIG. 2D, a block of 64 pixels composed of 8 pixels in the horizontal direction and 8 pixels in the vertical direction.

Super block: As shown in FIG. 2C, a super block is a region composed of four blocks in the horizontal direction and two blocks in the vertical direction of the luminance signal. In this area, the color signals U, V
Is included for each block. The image motion vector obtained from the motion evaluation circuit 13 can be set in units of super blocks.

Macro block: As shown in FIG. 2B, 11 super blocks in the horizontal direction. When a code is transmitted, the DCT coefficient of the block is converted into a code determined by the number of consecutive zero coefficients and the amplitude of the non-zero coefficient, and transmitted as a set. Finally, an end-of-block signal is added. Then, the motion vector of the motion correction performed in units of superblocks is added and transmitted as overhead data in units of macroblocks.

That is, in this band compression system, as described above, the eleven super blocks in the horizontal direction are called macroblocks, and four super blocks in one screen in the horizontal direction.
There are 4 superblocks. That is, one frame includes 4 macroblocks in the horizontal direction and 60 macroblocks in the vertical direction.
There will be a total of 240 macroblocks of macroblocks. In this band compression system, FIG.
(A) to (h) and FIGS. 5 (a) to (c),
Refreshing is performed for each row of the superblock in units of four blocks, and all superblocks are refreshed every 11 frames.
That is, as shown in FIG. 5D, by storing 11 frames of refreshed super blocks, intra-frame processing is performed in all areas. 3. Intra-frame / inter-frame coding The first basic operation of this system is an intra-frame coding process and an inter-frame coding process.

The intra-frame encoding process is performed as follows. When this processing is performed, the switch 24,
25 are both off. The video signal at the input terminal 11 is D
The time axis domain is converted to the frequency domain by the CT circuit 14,
The quantization is performed in the quantization circuit 15. This quantized signal is output to the transmission path via the FIFO circuit 17 after being subjected to the variable length encoding process. The quantized signal is returned to the original signal by the inverse quantization circuit 19 and the inverse DCT circuit 20, and is delayed by the frame delay circuit 22. Therefore, at the time of the intra-frame encoding processing, it is equivalent to the information of the input video signal being subjected to variable-length encoding as it is. This intra-frame processing is performed at appropriate intervals in scene changes of the input video signal and in predetermined blocks. The processing in the periodic frame will be described later.

Next, the inter-frame encoding processing will be described. When the inter-frame encoding process is performed, the switches 24 and 25 are both turned on. Therefore, a signal corresponding to the difference between the input video signal and the video signal one frame before is obtained from the subtraction circuit 12. This difference signal is
The signal is input to the DCT circuit 14, converted from the time domain to the frequency domain, and then quantized by the next quantization circuit 15. Further, since the difference signal and the video signal are added to the frame delay circuit 22 by the addition circuit 21 and input,
A predicted video signal that predicts the input video signal from which the difference signal is generated is generated and input.

Generally, the generated code amount of an image processed in a frame is larger than the generated code amount of an image processed in an inter-frame. 4. Intra-frame / inter-frame switching processing 4.1 Image adaptive intra-frame processing The switching between the intra-frame encoding processing and the inter-frame encoding processing is controlled by an intra-frame / inter-frame determination circuit 31. There are two control methods.

First, according to the first method, a signal having a correlation between frames is subjected to inter-frame processing according to the content of the input video signal, and an intra-frame processing is performed to a signal having no correlation between frames. Method. When a scene change or the like occurs, intra-frame processing is performed.

The intra-frame / inter-frame determination circuit 31 compares the energy of the current signal with the prediction error energy between the signal of the current frame from the input terminal 11 and the prediction signal output from the motion compensation circuit 23.

In FIG. 6, input terminals 11, 32, 33
And output terminals 34 and 35 are input terminals 11 and 3 of FIG.
2, 33 and the output terminals 34, 35.

The current signal is input to the input terminal 11. This current signal is input to the energy comparison circuit 36,
Input to the subtraction circuit 37. A prediction signal output from the motion compensation circuit 23 is input to an input terminal 33, and a subtraction circuit 37 obtains a prediction error which is a difference between the current signal and the prediction signal.

The current signal is a current signal energy calculating circuit 36a.
The prediction error is obtained by the prediction error energy calculation circuit 36b, and the energy is compared. An example of the energy calculation formula for the current signal and the prediction error is as follows.

[0049]

(Equation 1) FIG. 7 shows an example of a method for discriminating between / in a frame in the energy comparison circuit 36.

In the figure, the horizontal axis represents the energy of the current signal, and the vertical axis represents the energy of the prediction error. Also,
The solid line drawn from the origin 0 shows the case where the energy of the prediction error is equal to the energy of the current signal.

Since the energy of the prediction error is smaller in the area below the solid line, the inter-frame processing is performed. Since the energy of the current signal is smaller than the solid line, the intra-frame processing is performed.

The output of the energy comparison circuit 36 outputs an in-frame / inter-frame discrimination signal adapted to the input signal, and is synthesized by the addition circuit 38 and output from the output terminal 34. 4.2 Forced Intra-Frame Processing (Refresh) The second method is a method of forcibly performing intra-frame processing irrespective of the correlation of video signals. In this case, the intra-frame processing is periodically performed on a predetermined area of the screen. This forced intra-frame processing has two purposes.

1. This is necessary so that the image can be recognized within a certain time when the user changes the channel. This is to enable special reproduction to be realized on a recording medium such as a VTR or a disk.

This forced intra-frame processing is called refresh. The time required for a predetermined area to be refreshed is referred to as a refresh time.

The refresh generation circuit 39 is configured as shown in FIG.
As shown in (1), a synchronization signal is input from the input terminal 32, and an intra-frame selection signal is generated at a predetermined cycle in synchronization with the synchronization signal. This signal and the intra-frame / inter-frame discrimination signal of the energy comparison circuit 36 are added by the adding circuit 38, and an intra-frame / inter-frame switching signal is output from the terminal 34. 5. Refresh Next, refresh of each system will be described in detail. 5.1 DigiCipher Refresh In DigiCipher, as described above, 11 super blocks in the horizontal direction are called macroblocks, and 44 super blocks exist in the horizontal direction of one screen. That is, there are a total of 240 macroblocks in one frame, including 4 macroblocks in the horizontal direction and 60 macroblocks in the vertical direction. In this band compression system, FIGS. 4 (a) to 4 (h) and 5 (a) to 5 (a)
As shown in (c), refreshing is performed for each column of a superblock in units of four macroblocks, and all superblocks are refreshed every 11 frame periods. That is, as shown in FIG. 5D, by storing 11 frames of refreshed super blocks, intra-frame processing is performed in all areas.

The advantage of this refresh is that since the refresh is performed evenly for each frame, the capacity of the rate buffer can be small.

FIG. 8 shows the refresh of the DigiCipher using the super block address shown in FIG.

In the figure, the vertical axis indicates the super block address, the horizontal axis indicates the frame number, and the solid black portion indicates the portion processed in the frame. In the figure, only refresh is shown.

In the figure, frame numbers F _{0 to} F ₁₀
Is refreshed in all the superblocks of one screen in 11 frames.

Since the same processing is performed by four processors, the refresh operation of one processor shown in FIG. 8 will be used to explain the refresh operation of DigiCipher with reference to FIG.

That is, S.I. B. Address = 0 to 659
Will be described.

In FIG. 9A, the portion subjected to the refresh and the processing within the image adaptive frame is indicated by black coloring.

For example, at F ₀ , assuming that a scene change has occurred, S.P. B. Intra-frame processing has been performed on all areas at addresses 0 to 659. In addition, the F _14, S. B. In-frame processing is performed in the area of addresses 0 to 59.

FIG. 9B shows the refresh time of DigiCipher. Since a part of the area is refreshed per frame, and the refresh is completed in a period of 11 frames, the refresh time is 11 frames. In this refresh, the refresh of one screen is completed in any 11-frame period. That is, the refresh in 11 frame periods F ₁ to F ₁₁ in 11 frame periods F ₀ to F ₁₀ is completed.

As shown in FIG. 9C, the minimum acquisition time is one frame period, and is obtained when initialization starts when a scene change occurs.

The maximum acquisition time shown in FIG. 9D is a case where no image adaptive intra-frame processing is performed, and is 11 frame periods.

When high-speed reproduction is realized using only refresh blocks by recording on the VCR, at each refresh block address, as shown in FIG. This is the recording interval of the VCR. 7. The DCT two-dimensional DCT circuit (14 in FIG. 1) will be described.

First, an image is divided into small blocks (N × N) each including N pixels in the horizontal and vertical directions, and each block is subjected to two-dimensional DCT. The size of N at this time is set to 8 to 16 from the conversion efficiency. In this embodiment, N =
8 is used.

The transform coefficient of the two-dimensional DCT is given by Equation 1, and its inverse transform equation is given by Equation 2.

[0070]

(Equation 2) Here, F (0,0) represents a DC component coefficient,
(U, v) includes high frequency horizontal frequency components as u increases, and high frequency vertical frequency components as v increases.

First, the nature of the coefficient of the DC component of F (0,0) will be described. F (0,0) corresponds to a DC component representing an average luminance value in an image block, and its average power is usually considerably larger than other components.

Further, when the DC component is coarsely quantized, noise (block distortion) peculiar to the orthogonal transformation which is visually perceived as a large deterioration in image quality occurs. Then, F (0,0)
Is assigned a large number of bits (usually 8 bits or more) and is equally quantized.

Next, the conversion coefficient F (u, v) excluding the DC component
State the nature of The average value of F (u, v) is given by Equation 1,
It becomes "0" except for the DC component F (0,0).

When a fixed number of bits is assigned to a small block of an image in order to perform efficient encoding, a large number of encoded bits are allocated to transform coefficients of low-frequency components, and conversely, By performing coding by allocating a small number of coding bits to the transform coefficient of the high-frequency component, it is possible to reduce deterioration in image quality and perform coding at a high compression rate.

The image is converted into a small block of 8 × 8 = 64 pixels consisting of 8 pixels in both the horizontal and vertical directions,
When the CT is applied, the converted coefficients for each frequency component are 8 × 8 = 64 two-dimensional coefficients as shown in FIG. In FIG. 10, the upper left is the DC coefficient (DC component).
The other 63 are AC coefficients (AC components), and the spatial frequency increases toward the lower right. Since the AC component has a two-dimensional spread, it is converted to one-dimensional by zigzag scanning shown in the order of 0 to 63 upon encoding and transmission.

Here, the coefficients of the 64 DCTs are represented by DCT _i
It is represented by [i = 0 to 63].

The number of quantization bits for quantizing each pixel is often 8 bits in the case of an image signal.

A DCT coefficient of an output obtained by performing a DCT conversion on the 8-bit pixel may be represented by 12 bits. 8. Quantization Next, the quantization circuit (15 in FIG. 1) will be described.

The above-mentioned 64 DCT coefficients are linearly quantized with a different step size for each coefficient position, using a quantization table that defines a quantization step size for each coefficient.

There are two methods for setting the quantization step, but they are basically the same.

The first method is a method of transmitting a code indicating a quantization table using a quantization table in which a quantization step is determined for each of 64 DCT coefficients.

FIG. 11 shows an example of the quantization table. In the figure, q = 0 to q = 9 are quantization table codes representing a quantization table. By transmitting this code, the decoder can perform inverse quantization.

The 64 numbers arranged in a square indicate the number of quantization bits, and correspond to the 64 two-dimensional coefficients shown in FIG. For example, 7 in the upper left of the quantization table of q = 0 indicates that the DC component is quantized by 7 bits.

Hereinafter, each coefficient is similarly quantized with the number of bits indicated in the quantization table.

In the second method, first, each of the 64 DCT coefficients is weighted using a weighting matrix.

Thereafter, the quantization width data QS (Quantize-S
This is a method in which each coefficient is uniformly divided and then quantized using cale). At the time of transmission, a code corresponding to the quantization width data is sent. The weight matrix has a default value. Furthermore, a specific type of weighting matrix can be transmitted.

As an example, MPEG. In I, 5 bits are assigned to the code of the quantization width data QS, and 32 types can be designated. Therefore, this value is changed to QS _j [j =
0 to 31].

Here, the quantization width data QS _{j is} defined.

The case where the DCT coefficient value is quantized with the maximum number of quantization bits is represented by j = 0, and QS ₀ = 1.

When the coefficient value of the DCT is not transmitted, j = 31. At this time, the number of quantization bits described later is set to QL ₃₁ = 0.

Here, j is referred to as a quantization level.

FIG. 12 shows MPEG. The default value of the weighting matrix of the luminance signal used in I is shown.

In the figure, 64 numbers of 8 × 8 are:
There is a correspondence with the 64 two-dimensional coefficients shown in FIG. 10, and shows the weighting value for each DCT coefficient.

In the encoder, each coefficient of the DCT is divided by the corresponding weight value and quantization width data QS.

The coefficients of the 64 DCTs are given by DCT _i = [i =
0 to 63], and each value of the weighting matrix is represented by WEIGHT _i [i = 0 to 6].
3] When each value after quantization is represented by Q _i [i = 0 to 63],

[0096]

(Equation 3) Is represented by

The number of quantization bits at this time is

[0098]

(Equation 4) Is represented by

The following is an example.

MPEG. I in the vertical direction of the luminance signal of I
The AC component is represented by DCT ₁ in FIG. 10 described above.

The value corresponding to DCT ₁ in the weighting matrix is WEIGHT ₁ = 16. This is shown in FIG.
Corresponds to the part marked with a circle. When the quantization width data QS ₀ = 1,

[0102]

(Equation 5) Since the coefficient of DCT _i is represented by 12 bits, log ₂ D
The maximum value of CT _i is 12. The number of quantization bits at this time is

[0103]

(Equation 6) Becomes

FIG. 13 shows the required maximum number of quantization bits after passing through the weighting matrix when QS ₀ = 1. This figure is a matrix showing the number of 8 × 8 = 64 quantization bits, and each number indicates the number of quantization bits corresponding to each position of the DCT coefficient shown in FIG.

FIGS. 14 and 15 quantitatively show nine representative quantization tables among the quantization tables when 32 types of quantization width data QS _j are set. This table is based on the quantization width data QS in order to describe the case where the above-described second technique regarding the quantization table is used.

Here, j = 31 is an example in which no data is generated, and corresponds to quantizing all coefficients with 0 bits. Also, j = 0 is the quantization width data QS ₀ = 1
Therefore, it is equivalent to quantization with a weighting table. That is, in this case, the bit distribution is based on the weighting table shown in FIG.

In FIG. 14 and FIG. 15, the horizontal axis represents DCT.
These 64 coefficients correspond to the order of the zigzag scan shown in FIG. The vertical axis indicates the number of bits to be transmitted in each DCT coefficient.

When quantizing the DCT coefficients, M
From SB (Most Significant Bit) to LSB (Least Sign)
ificant Bit) is present. When limiting the number of bits to be transmitted, naturally, the MSB is transmitted with priority.

As described above, if the number of quantization bits for the DC component is reduced, block distortion or the like becomes conspicuous, so that the DC component is treated separately and a certain number of quantization bits are assigned. Here, it is assumed that 8 bits are allocated. MPEG. In the case of the example of the luminance signal of I, the maximum value of the AC component is 8 bits as described above.

Referring to FIGS. 14 and 15, the number of quantization bits and quantization width data will be quantitatively described.

The generated code amount becomes maximum when j = 0, and as j increases, the generated code amount decreases.
It becomes 0 at 31 and no sign is generated.

It is possible to control the amount of code generated by controlling the quantization width data. 9. Necessary conditions for high-speed reproduction Next, conditions required for high-speed reproduction will be described. 9.1 Refresh Block Code Swapping First, an embodiment in the simplest case will be described.

In the conventional example, one screen 264 is composed of 11 frames.
Since the intra-frame encoding process is performed on 0 areas, 1
The number of areas a in the screen is a = 2640, and the intra-frame encoding processing cycle f = 11 frames. Further, in order to explain a case where one track is divided into two and an average video code for one frame is recorded in one track, the number of divisions d of one track is described.
= 2, the number of tracks c for recording the average video code for one frame is c = 1. Therefore, the number of recording medium areas d × c ×
f = 2 × 1 × 11 = 22. The correspondence between the screen area of the refresh block and the recording medium area will be described with respect to a case where the correspondence is 1: 1. The number of screen areas that enter one recording medium area e = a / d × c × f = 2640/2 × 1 ×
11 = 120 pieces, and e = 120 pieces are converted into d × c × f
= 22 regions will be described.

FIG. 16 shows the operation timing of this system.

Referring to FIG. The input terminal 32 is supplied with a synchronization signal of the input video signal. This synchronization signal is input to the synchronization signal detection circuit 40 and detected.
The synchronizing signal detecting circuit 40 generates a synchronizing pulse synchronized with the synchronizing signal from an output terminal 41 and supplies it to a track forming signal generating circuit 42.

FIG. 16A shows an input video signal, Y represents a luminance signal, U and V represent chrominance signals, and the numbers written in the frames indicate frame numbers. FIG.
FIG. 16B shows a synchronizing pulse of the output terminal 41 obtained from the synchronizing signal detecting circuit 40, which is generated in synchronization with the frame switching point of the input video signal shown in FIG. FIG. 16C shows the track forming signal generation circuit 42.
5 shows a track forming signal obtained from the above. A and B attached to the track formation signal designate a period in which the A head and the B head of the rotary drum 43 alternately form tracks. As shown in FIG. 1, the A head and the B head are mounted at positions facing the rotary drum 43 by 180 °. In this embodiment, FIG.
The generation timing of the synchronization pulse shown in FIG.
The switching timing of the track forming signal shown in (c) is synchronized. FIG. 16D shows a track formed by the A head and the B head, and the numbers written in the frames indicate the track numbers.

The track forming signal output from the track forming signal generating circuit 42 is supplied to a track forming control circuit 44. This track formation control circuit 44
Controls the rotation phase of the rotating drum 43. Further, the synchronization pulse of the synchronization signal detection circuit 40 is replaced with a code replacement circuit 45.
To control the recording signal supply timing to the A head and the B head.

Next, a description will be given of a code permutation method used in this embodiment to enable high-speed reproduction of a VTR. First, a combination of the luminance signal Y and the chrominance signals U and V supplied to the input terminals 27, 28 and 29 by the blocking circuit 30 is input from the input terminal 11 as an input video signal to the subtraction circuit 12 and the motion evaluation circuit. 13 is supplied to
The variable length coding circuit 16 outputs a video code which has been subjected to band compression coding.

Here, in the conventional band compression system shown in FIG. 59, the video signal is variable-length coded, and
As shown in (i), the switching point of the frame of the video code differs depending on the frame. The NMP signal shown in FIG. 16H indicates a frame switching point of the video signal. Conventionally, 264
There are 0 superblocks and this 2640
The super blocks are included in one frame period indicated by the NMP signal in FIG.

[0120] Conventionally, four macroblocks exist in the horizontal direction on one screen, and these macroblocks are composed of 11 super blocks. In addition, one superblock in a macroblock per frame forcibly uses intra-frame processing. The sequence for forcibly using the intra-frame processing is included in the system control signal of FIG. Here, the super block for which the intra-frame processing is forcibly performed is referred to as a refresh block, and the super block for which the intra-frame processing is not forcibly performed is referred to as a non-refresh block. FIG. 2 shows the relationship between macro blocks, refresh blocks, and non-refresh blocks.

Here, the definition of the term is: refresh block: When a macroblock is forcibly performed in-frame processing one superblock at a time during one frame period, the superblock that has performed the in-frame processing is called a refresh block. . Since a macro block is composed of 11 super blocks, 1
Intra-frame processing is forcibly performed in one frame cycle.

Non-refresh block: A super block other than the above-described refresh block. In this super block, there are a block that has been subjected to intra-frame processing and a block that has been subjected to inter-frame processing, depending on the contents of an image. For example, when a scene change or the like occurs in an input video signal, in-frame processing may be used, but this is also a non-refresh block.

Here, there are 240 refresh blocks (= 2640 ＝ 11) in one frame period. Therefore, conventionally, there are 240 refresh blocks in one frame period shown in FIG. 16H, as shown in FIG. 16G. Then, the conventional signal is directly used as V
When recording is performed by TR, the position of the refresh block cannot be determined, and high-speed reproduction cannot be performed as described above.

FIGS. 17A and 17B show video signals of frame numbers F ₅ and F ₆ , respectively. In the figure, the portions indicated by G ₅ and G ₆ indicate refresh blocks, and the portions indicated by H ₅ and H ₆ indicate non-refresh blocks. Thereafter, between the frame number, the refresh block number, and the non-refresh block number, the refresh block number of the frame of frame number F _n (n is an integer) is G _n , and the non-refresh block number is H _n .

In the present invention, the arrangement of the refresh block and the non-refresh block on the track is made different.

This embodiment shows a case where one track is divided into two and recorded. When one track is divided into two, high-speed reproduction can be performed up to double speed. 3
At the time of high-speed reproduction at twice or more times, all the refresh blocks cannot be reproduced, so that an area where an image cannot be formed occurs as in the diagram shown in FIG.
If it is desired to realize high-speed reproduction of 20 times speed as a VTR specification, one track may be divided into 20. Furthermore, when it is desired to realize fast high-speed reproduction, refresh blocks may be arranged at equal intervals on a track.

FIG. 16 (e) shows a timing pulse for dividing one track into two, and divides one track period shown in FIGS. 16 (b) and (c) equally into two. The divided one period is called a sector.

That is, as a definition of a word, a sector: d is almost equally divided into one track period (in this case, 2)
It refers to the divided period. In this embodiment, FIG.
As shown in (f), 120 refresh blocks are put in one sector. In this case, since one track is composed of two sectors, 240 refresh blocks are inserted in one track, which is equal to the number of refresh blocks in one frame of the video signal.
That is, the number of refresh blocks e included in one sector is:
Assuming that the number of super blocks in which intra-frame processing is performed periodically is b, and b intra-frame processing signals are recorded on c tracks, e = b / c × d (in this case, 24
0/1 × 2 × 120).

By performing the above-described code replacement, the refresh block for one frame is arranged in one frame period indicated by the NMP signal in the related art, but the refresh block for one frame is arranged in one track period. It can be arranged to be present.

FIG. 18 shows a track pattern.
That is, the tracks T _{1 to} T on the magnetic tape 26
G ₁ ~G ₁₁ filled out in the frame of _11, corresponding to the refresh block number G _n described above. The relationship between the refresh blocks and the track T _n is made to the relationship of refresh block number G _n in the track T _n is recorded. Further, H ₁ to H ₁₁ filled out in the frame of the track T ₁ through T ₁₁ corresponds to the non-refresh block number H _n described above. The switching point of the non-refresh block is a thick line portion shown in the frame of the tracks T _{1 to} T ₁₁ .

The relationship between the sector and the track is shown in the track 46 of FIG. The track 46 is divided into two parts, d =
It is divided into two sectors. This one sector contains e
= 120 refresh blocks are arranged. The non-refresh block is inserted while the refresh block is arranged.

[0132] Here, if the track T _5, T ₆ will be described in detail as an example, to record the refresh block G ₅ of the frame F ₅ in the track T _5. Also, track T ₆
To record refresh blocks G ₆ of the frame F ₆ is in. A non-refresh block is recorded in the empty portion where the refresh block is arranged. The track T ₅ records non refresh block H _5, H _6, the track T
The ₆ records the non-refresh block H _6, H _7.

Therefore, in order to realize the recording form as described above, the band compression coded video code obtained from the variable length coding circuit 16 in FIG. 1 is supplied to the code replacement circuit 45 again. The refresh timing generation circuit 39 generates a code position signal of the above-described refresh block from the output terminal 35, and the code position signal is supplied to the code replacement circuit 45. The code replacement circuit 45 rearranges the variable length code between the refresh block and the non-refresh block based on the synchronization pulse and the code position signal of the refresh block. That is, a process of inserting 120 refresh blocks into each of two sectors provided in one track is performed. This processing is realized by temporarily storing codes in a memory (not shown) and reading the codes from the memory so that 120 refresh blocks are included in one sector.

The output of the transposition circuit 45 is
It is supplied to the index insertion circuit 47. The index insertion circuit 47 inserts an index signal into the control data section of each sector so that it is possible to detect at the time of reproduction that a non-refresh block is partially separated and recorded. The index signal is prepared by an index generation circuit 48 to which a code position signal from the refresh timing generation circuit 39 is supplied. The output of the multiplexer 49 including the index insertion circuit 47 is recorded on the magnetic tape 26 via the ECC circuit 50, the unit sink insertion circuit 51, and the modulation circuit 52.

FIGS. 19A and 19B show trace loci X _{1 to} X ₁₁ of the head during 2 × speed reproduction.
Note that within the framework of each track T ₁ through T _22, shows the same refresh blocks G _n and non-refresh block H _n and FIG 18. 20 (a) to (h) and FIG. 21 (a) show reproducible refresh blocks in the head trace at the time of double speed reproduction shown in FIG.
To (c). Frames 1 to 11 shown in FIGS. 20A to 20H and FIGS. 21A to 21C correspond to FIGS.
9 (b), the head trace locus X ₁ at the time of double speed reproduction
Shows a reproducible refresh blocks to X _11.

[0136] In example frame 1, by performing the head trace X _1, displays the refresh block G ₁ in the upper half of the screen, it is possible to display the refresh block G ₂ in the lower half of the screen. Similarly, in frames 2 to 11, the refresh block G ₃
It is possible to play up to ~G _22. Therefore, if reproducible refresh blocks are accumulated in frames 1 to 11, codes in all screen areas can be reproduced as shown in FIG.

The code subjected to the inter-frame processing and the code subjected to the intra-frame processing according to the content of the image are included between the codes subjected to the intra-frame encoding processing periodically. These codes have no correspondence between the image area and the recording medium area.

As a recording medium, a magnetic tape 26 was used.
However, the present invention can be applied to a video disk, and in this case, one round of the disk corresponds to one track of the tape. 9.2 Refresh Block Code Amount By inserting a refresh block in a predetermined area on the track of the VTR, high-speed reproduction is possible, but it is necessary to prevent the code amount from exceeding the code amount recordable in the predetermined area. .

When the code amount of a predetermined refresh block is
If the recordable code amount in a predetermined area of the recording medium is exceeded, refresh is not performed at a position on the image corresponding to the exceeded code.

Even if this is not avoided, refreshing is performed from a certain position on the image, so it is highly possible to determine the contents of the image. Requires control of the amount of code generated in the refresh block.

Therefore, the code amount of the refresh block will first be described in detail. 9.2 Refresh Block Code Amount First, if a DTR is not used as a VTR servo and a video signal is recorded by c = 1 head scan per frame to realize a special reproduction speed of i = 2 times speed, one frame is used. The case where the code amount of the refresh block is calculated for each 1 / c × i = の region of the video of FIG. If the maximum recording code amount that can be recorded on one track where P is the code amount of the refresh block formed in one scan is α, the code amount of the refresh block in a half area of one frame is α / c. × i = α / 2 or less. An example in which the head scan of the VTR is one scan and the average code amount of the video signal of one frame is recorded will be described in detail. Also, a case will be described in which the trick play speed is doubled. In the embodiment, since there are 240 refresh blocks per frame, 120 refresh blocks are recorded per sector.

FIGS. 22A and 22B show a refresh block in one screen and a dividing method when the refresh block is further divided. F _n shown in FIG. 22 in (a) shows the screen of the n-th frame. G _n indicates a refresh block in the n-th frame. This refresh block is 240
Exists. In addition, G shown on the left side of the screen
_n (0) and G _n (1) indicate refresh blocks obtained by equally dividing the 240 refresh blocks in the vertical direction. That is, G _n (0) indicates 120 refresh blocks existing above the screen among the G _n refresh blocks. G _n (1) is
It shows the refresh blocks in the lower area of the screen, and includes 120 refresh blocks.
FIG. 22B shows a refresh block of frame number F _{n + 1} , and the definitions of G _{n + 1} (0) to G _{n + 1} (1) are the same as those in FIG. .

Next, the track pattern of the VTR will be described. FIG. 23 shows a track pattern on the magnetic tape 26. T _{0 to} T ₁₁ indicate tracks recorded using the rotating drum 43. Here, a case where the average generated code amount of one frame is recorded on one track will be described. That is, a case where c = 1 described above will be described. This corresponds to the case where b = 240 refresh blocks are recorded on one track. In other words, the refresh block G of the frame number F _n
n it will be recorded in the track T _n.

In this configuration, when performing double speed reproduction, the reproducing head crosses two tracks. Therefore, one track is divided into two equal parts.
While reproducing the area No. 2, a reproduction signal is obtained over two tracks. Here, if one divided portion is referred to as a sector, one track is formed per frame, and therefore two sector numbers S ₀ and S ₁ are assigned as shown in FIG.

Generally, an area obtained by dividing a single track into substantially equal parts d is referred to as a sector.

In order to realize i-time high-speed reproduction, the head straddles i tracks, so that one track reproduces the area of 1 / i. Then, assuming that the highest high-speed reproduction speed is i _max , i _max ≦
Set to the relationship of d. Then, the sector names are S _{0 to} S _d-1.
Expressed by

Next, the relationship between the refresh block and the sector will be described. When recording the refresh block G _n of the frame number n in one track T _n, G _n (0)
.. S ₀ , G _n (1)... S ₁ are recorded.

Here, assuming that the number of refresh blocks included in one sector is equally arranged, the number of refresh blocks included in one sector is as follows. That is, 1
Assuming that the number of refresh blocks per frame is b, the number of tracks for recording the b refresh blocks is c, the number of track divisions is d, and the number of refresh blocks within one sector is e, e = b / c × d. Become. That is, e = 240/1 × 2 = 120.

In FIG. 23, the head traces of X _{0 to} X ₄ represent the head trajectory at double speed. That is, in the head trace of X ₀ , the sector S ₀ of the track T ₀ (refresh block G ₀ (0)) and the sector S ₁ of the track T ₁ (refresh block G _0
1 (1)), indicating that sector S ₀ (refresh block G ₂ (0)) of track T ₂ can be reproduced.

Since the recording capacity that can be recorded in the sectors S ₀ and S ₁ of the recording medium on the tape 26 is determined,
Within this recording capacity, the refresh block G _n (0),
The generated code amount of G _n (1) must be suppressed.

That is, when the DTF is not used and the high-speed reproduction speed is i, the area of 1 / i of the p tracks formed in one scan is traced.

As described above, the maximum code amount that can be recorded on p tracks formed in one scan is α, and when a video signal is recorded by c scans per frame, 1
It is necessary to reduce the maximum code amount in the 1 / c × i area of the refresh block of the frame to α / i or less. In this case, the case where an extremely wide head is not used as the special reproduction head is shown.

When the DTF is used as the VTR servo system, the maximum recording code amount that can be recorded on p tracks formed in one scan is α, and the video signal is recorded by c head scans per frame. In addition, it is necessary to keep the maximum code amount of the refresh block in the area of 1 / c of the video of one frame equal to or less than the above α. 10. Code amount control There are two types of code amount control methods. The first method is a method of controlling the quantization level as described above. In this case, the generated code amount of the refresh block is suppressed, so that the image quality of the refresh block itself is deteriorated. However, in the next frame, the difference between the in-frame processing signal of the refresh block and the video signal of the next frame is sent, so that the image quality only drops momentarily. This technique will be described later in detail.

In the second method, a code once quantized is divided into two parts, and the code amount of the MSB or low-frequency component is converted into a VTR.
This is a method of reducing the amount of codes that can be read out at the time of high-speed reproduction on a recording medium such as this. Regarding this, 11. Details are given in the chapter.

The control of the encoded information amount when the first method is used will be described below. 10.1 Macroblock Code Amount Control When a video signal is highly efficiently coded using variable length coding as in this embodiment, the amount of generated information is generally not constant. This is because the information amount of the video signal fluctuates with time.

On the other hand, when a fixed-rate transmission system is used, encoding control for keeping the encoded information amount constant is required.

A general method of the fixed rate conversion is to prepare a buffer memory at the output of the encoder, input the data to the buffer memory at a variable rate, and perform the output at a fixed rate to smooth the encoded information amount. It is. Since the amount of data in the buffer memory fluctuates according to the amount of input information, overflow or underflow may occur. In order to prevent this, when overflow or underflow is likely to occur, the encoding parameters are changed so as to decrease or increase the amount of encoded information, respectively. For example, the quantization characteristics may be made coarser or finer.

[0158] The larger the capacity of the buffer memory is, the higher the effect of smoothing is, but there are restrictions on encoding delay and cost.

In addition, a relatively small buffer memory can perform finer coding control depending on the local characteristics of an image, and a buffer memory of about one frame may be used.

The control of the macroblock code amount will be specifically described.

The capacity of the rate buffer is used for controlling the code amount of the macro block. In the method using the rate buffer, as shown in FIG. 24, a rate buffer (Rate Buffer) having an equal capacity is provided in the encoder and the decoder.

The code amount of input / output of these buffers and the occupancy of the buffers will be described with reference to FIG.
Reference symbol a in FIG. 24 indicates an input signal of the rate buffer b of the encoder. This signal is an output signal of the variable length encoding circuit 16 of the encoder. As a characteristic of this signal, each block is input at a fixed period, but the generated code of each block is a variable length code, so that it has a variable length rate. The output signal c of the rate buffer of the encoder is transmission data, and a code is output at a fixed rate. Further, the input signal d of the rate buffer e of the decoder is a fixed-rate code input, and the output signal f is a variable-rate code output.

The characteristics of the encoder and the decoder will be described in detail with reference to FIGS. 25 and 26, respectively. The horizontal axis in FIGS. 25A to 25C and FIGS. 26A to 26C indicates the frame number. Here, FIG.
(A) to (c) and FIGS. 26 (a) and (b) are the same as the input frame numbers, but the frame numbers in FIG. 26 (c) are shifted by 8 frames. This is necessary in order to absorb the fluctuation of the delay time of the transmission code of the encoder and the decoder due to the use of the variable length code.

FIGS. 25 (a)-(c) and 26 (a)-
The vertical axis of (c) indicates the code amount. In this example, an example in which the capacity of the rate buffer is 4 Mbits and the transmission code amount per frame is 0.5 Mbits / frame is shown. FIGS. 25A to 25C show the encoder side, and FIGS.
6 (a) to 6 (c) show the characteristics on the decoder side. FIG. 25A shows the generated code amount per frame. The broken line in the figure indicates the capacity of the rate buffer for reference. Since variable-length codes are used, the amount of code generated in each frame differs from frame to frame. F _{1 to} F ₉ , in which the frame numbers are represented by F _n , show examples of code generation when the buffer overflows and underflows occur. F
In _1, the code is generated in 4.5M bits, and the F ₂ to F ₉ until the generated code is 0.

The maximum value of the generated code amount of each frame is determined by the sum of the buffer capacity and the transmitted code amount. In this example, the buffer capacity is 4 M bits, and the transmitted code amount per frame is 0.5 [M bits]. / Frame], the maximum amount of codes that can be generated per frame is 4.5 Mbits.
Until F ₂₀ to F ₃₀ is an example of a case where the control generated code amounts of the respective frames by the buffer occupancy.

FIG. 25B shows the occupancy of the buffer of the encoder. In this example, the buffer capacity is 4M
And the capacity of the buffer is indicated by a broken line. F
_{Since a} large generated code amount occurs in _one frame, F
At time ₁ , buffer overflow has occurred. F
_{Since the} state where no code is generated at all from _{2 to} F ₉ continues, the buffer underflow occurs at the time of F ₉ .

FIG. 25 (c) shows the transmission code amount from the encoder. A real straight line A drawn diagonally in the figure indicates the accumulated transmission code amount. This slope indicates the amount of transmitted code per frame. In this example, 0.5 M bits are transmitted per frame time. Frame rate 30
In the case of [Hz], 30 × 0.5 [M / Frame] = 15
The transmission code amount is [Mbps]. The broken line indicates the maximum value determined by the maximum capacity of the buffer.

The polygonal line shown in FIG.
This shows the accumulated code amount generated. That is, FIG.
Is the integrated value of the generated code amount per frame.
When the accumulated code amount touches the broken line, the buffer overflows, and when it touches the solid line, the buffer underflows. A dotted line drawn horizontally between the accumulated code amount and the accumulated transmission code amount indicates a delay time in the encoder buffer when the generated code is transmitted. This is shown.

In FIG. 26A, a solid line B indicates the accumulated received code amount. This real straight line B is shown in FIG.
Is the same as the actual straight line A. The polygonal lines indicate the projected code amount of each frame when the image is output. This is shown in FIG.
This corresponds to a value obtained by integrating the projected code amount per frame in (c). The dotted line drawn horizontally represents the delay time when the received code is projected, and the sum of the delay time in the encoder and the delay time in the decoder are all equal, and the buffer delay shown in FIG. Time (Buffer D
elay).

FIG. 26 (b) shows the occupancy of the buffer of the decoder. Here, FIG. 25 (b) and FIG.
(B) is compared. Figure 2 shows the buffer delay time.
25 (b) and FIG. 26 (b) when 5 (b) is shifted.
Is a relationship inverted up and down. That is,
An encoder overflow results in a decoder underflow, and an encoder underflow results in a decoder overflow.

FIG. 26 (c) shows the amount of projected codes per frame of the projected codes. FIG. 25 (a) and FIG.
6 (c) is delayed by the buffer delay time of the encoder and the decoder.

When the subscriber changes the channel, it is possible to output the video after accumulating the necessary code amount in the buffer of the decoder. This accumulation amount
It is equal to the value for storing the received code amount for the time indicated by the dotted line in FIG. This value corresponds to the NMP signal of the conventional example. That is, the decoder only needs to store the code in the buffer for the time determined by the NMP signal, and then output the video.

[0173] Figure 25 As shown in F ₁ of (a), if the maximum code amount has occurred in the first frame, the maximum buffer delay is caused in the buffer of the decoder.
In this case, a normal video signal can be output after the received code is accumulated in the buffer for the time indicated as the buffer delay in FIG. In this case, a normal video signal is output after the buffer of the decoder is filled with the reception code.

That is, received codes are accumulated from F _{0 to} F ₈ , and a normal video signal is output after the initialization state that fills the buffer memory is completed. When outputting the Utsude code in FIG. 26 F ₁ of (c), the buffer of the decoder is in the underflow. Further, FIG.
When F ₁ to F state of not outputting Utsude code to ₉ (c) was followed, the decoder buffer at F ₉ has become overflow. This coincides with a state in which the buffer state of the encoder is delayed by eight frames and overflow and underflow are inverted.

When the subscriber changes the channel, it is necessary to accumulate the codes only for the time according to the NMP signal in the buffer of the decoder in order to output a normal video signal. It is possible to produce an incomplete image as shown by the dotted line in c).

FIG. 27 shows an example of the relationship between the buffer occupancy and the increase or decrease of the quantization level set for each macroblock. The quantization level is not changed while the buffer occupancy is at the predetermined value, and the quantization level is increased or decreased when the buffer occupancy exceeds the predetermined value. In FIG. 27, when the occupying rate of the buffer is 45 to 55%, the quantization level is not changed,
When this value is exceeded, the quantization level is changed. Thereby, the rate control of the buffer becomes possible.

The quantization level is coarsely quantized when the value of j is large, and the generated code amount is small. Therefore, when the buffer occupancy is small, the quantization level is reduced. When the buffer occupancy is large, the quantization level is increased. Operate in the up direction.

FIG. 28 shows a configuration for realizing the above operation.

To determine the macroblock quantization level, a quantization level setting circuit 53 and a superblock code amount calculation circuit 54 were used.

First, a method of calculating the code amount of the super block will be described in detail with reference to FIG.

First, the output of the quantization circuit 15 is input to the variable length coding circuit 16. Inside this circuit, first, the 8 × 8 DCT coefficients are read by the zigzag scanning circuit 16a by the scanning method shown in FIG. 10, the continuous number of 0 coefficients and the amplitude of non-zero coefficients are combined, and the Huffman encoding circuit 16b is used. input.

The number of consecutive 0 coefficients and the amplitude of the non-zero coefficient are input to the superblock code amount calculation circuit 54.
The super block code amount calculation circuit 54 calculates the generated code amount by using a ROM that stores the table shown in FIG.

FIG. 29, which is also used in the conventional example, shows the amplitude of the non-zero coefficient on the horizontal axis and the number of consecutive 0 coefficients on the vertical axis. The number in the frame indicates the number of bits of the code. By adding the number of bits of this code, the generated code amount is calculated in super block units.

Further, in order to determine the quantization level of the macro block, the macro block code amount calculation circuit 55
The code amount of the macro block is calculated by adding the code amounts of the eleven super blocks.

The transmission code amount stored in the transmission code amount ROM 56 is subtracted from this value, and the rate buffer code amount calculation circuit 57 calculates the occupancy of the rate buffer included in the code replacement circuit 45.

Based on the rate buffer occupancy and the graph of FIG. 27, the macroblock quantization level setting circuit 58
Sets the quantization level for each macroblock. 10.2 Superblock code amount control Code amount control per superblock can be controlled only in a direction to make it coarser than the quantization level determined by the macroblock.

This is because, for example, if there is a superblock processed in a frame, the code amount processed in the frame is larger than the code amount processed in the interframe.
This is because the code amount may be significantly increased in the super block processed in the frame.

[0188] On the other hand, the human visual characteristic is that when the content of the image changes, for example, when a scene change occurs or when a hidden part appears behind a moving object (this is called covered back). In addition, the eyes cannot react quickly to the definition and a certain time is required.

Therefore, in the in-frame processing portion caused by the change in the content of the image, it is difficult to determine the deterioration of the image quality even if the quantization level is made coarse. That is, the code amount can be reduced in a portion where the image adaptive intra-frame processing has occurred.

A configuration for realizing this operation will be described with reference to FIG.

Refresh block quantization level setting circuit 5 corresponding to super block quantization level setting circuit
9 and the non-refresh block quantization level setting circuit 60 receive from an input terminal 61 an image adaptive intra-frame / inter-frame determination signal output from the energy comparison circuit 36 in the intra-frame / inter-frame determination circuit 31. DCT circuit 1
4 is input from the input terminal 62 and input to the DCT coefficient energy calculation circuit 63, where the energy of the DCT coefficient is calculated, and the correction level of the quantization level is determined based on this energy. This value is input to the quantization circuit 15 through an adder 64 that adds the value to the macroblock quantization level. The relationship between this energy and the correction level is shown in FIG.
The relationship shown in FIG.

Further, even in a super block that has been subjected to inter-frame processing, if the energy is extremely large, it means that there are many high-frequency components. The roughening level may be roughened. In this case, the correction level is set as shown in FIG. 10.3 Refresh block code amount control As described in Chapter 9, section 9.2, the generated code amount of the refresh block needs to be controlled to a predetermined code amount determined from a recording medium such as a VCR.

In order to realize this, in this embodiment, the code amount of the refresh block is independently calculated, and the quantization level of the refresh block is set using this value.
As a configuration, the refresh block code amount calculation circuit 6
5. The refresh block quantization level setting circuit 59 was used.

The generated code amount of the refresh block is output from the super block code amount calculation circuit 54, and the refresh block code amount calculation circuit 65 sequentially adds the code amount of the refresh block. In this embodiment, the values are added during a period of 120 super blocks to be included in one sector on the tape 26.

By inputting the result to the refresh block quantization level setting circuit 59, a correction value from the macro block quantization level is determined.

The refresh block quantization level setting circuit 59 also has the super block code amount control method described in section 10.2 above.

The output of the refresh block quantization level setting circuit 59 is input to the quantization circuit 15 through the switch 66 and the adder 64 for adding a correction value to the quantization level of the macro block.

FIG. 31 shows an example of a method of setting a refresh block quantization level.

In FIG. 31, the horizontal axis indicates the refresh block number. In the present embodiment, the refresh block number of sector 0 and the refresh block number of sector 1 are shown in order to record a refresh block of one frame in two sectors. Further, in this example, the recording code amount α / 2 of one sector is not exceeded in 120 refresh blocks.

The vertical axis in FIG. 31 indicates the code amount of the refresh block. The maximum code amount is α / 2 as described above.
Set to. Here, it is assumed that α / 2 = 250K bits. In FIG. 31A, a solid line C is a target code amount of the refresh block, and the generated code amount is controlled so as not to exceed this line. Since the solid line C is an example for control, it does not need to be a straight line, and it is necessary to reduce the generated code amount per sector to α / 2. A polygonal line D is a line showing an example of a change in the refresh block accumulated code amount. This shows an output signal of the refresh block code amount calculation circuit 65. The quantization level is determined so as not to exceed the refresh block target code amount (solid line C).

FIG. 32 shows a macroblock quantization level,
An example of setting the quantization level of the refresh block will be described.

As shown in FIG. 28, first, the quantization level of the macro block is determined based on the occupancy from the buffer memory. For the quantization level of this macroblock,
By increasing the quantization level as needed, the quantization level of the refresh block is set only in the direction of decreasing the generated code amount. The quantization level correction level indicating the difference between the quantization level of the macro block and the quantization level of the refresh block can be transmitted as additional data.

In FIG. 32, the horizontal axis represents the quantization level j = 31 to 0 of the macroblock. When j = 31, no code is generated, and when j = 0, a maximum code amount is generated. Further, the numbers entered below indicate an example of the number of bits used to indicate the quantization level correction level.

The vertical axis indicates the quantization level j = 31 to 0 of the refresh block. The circles in the figure indicate quantization levels that can be taken as refresh blocks. In each case, a quantization level at which the code generation amount is smaller than the macroblock quantization level is assigned.

Since the output signal of the DCT circuit 14 is input to the refresh block quantization level setting circuit 59, the refresh block quantization level setting circuit 59 compares the output signal with the refresh block accumulated code amount so as not to exceed the refresh block target code amount. It is possible to choose a conversion table.

This will be described in detail with reference to FIG.

FIG. 31 (b) is an enlarged view of the horizontal axis of FIG. 31 (a). Refresh block number 80 to 8
The method of determining the quantization level to 1 will be described with reference to FIG. First, it is assumed that the code amount up to the refresh block number 80 has been calculated from the refresh block code amount calculation circuit 65, and the code amount indicated by E in FIG. It is also assumed that the target code amount is determined by the refresh block number, and the refresh block number 81 has the code amount indicated by F in FIG.

If the macroblock quantization level is set at j = 15, and if there is a quantization level relationship shown in FIG. 32, j = 15, 19, 23, and 27 are set as the refresh block quantization levels. It is possible.

The refresh block quantization level setting circuit 59 receives the coefficient signal obtained by DCT of the video signal as the output signal of the DCT circuit 14, so that the quantization level is set to j = 15, 19, 23, 27. The amount of generated code at the time of setting can be calculated. The results are G, H,
Suppose I and J decide. The generated code amounts G, H, I,
By comparing J with the target code amount F, a refresh block quantization level j = 23 which is the code amount of I can be selected.

In this way, by controlling the code amount of the refresh block and inputting it to the above-described code replacement circuit 45 and index insertion circuit 47 for recording, it is possible to reliably perform refreshing at the time of high-speed reproduction. Become. 13. Bit stream structure The bit stream structure of each block is shown below.

In FIG. 1, the overhead data of the output of the overhead data generation circuit 67 is added to the output of the variable length coding circuit 16 and output to the output terminal 68.

In package media such as VCRs and video discs, a code transposition circuit 45 is required to realize high-speed reproduction. However, when transmitting broadcast waves,
Changing the sign is not always necessary.

The code replacement method depends on the number of drum rotations of the VCR, the number of heads, the tape format, the recording code amount of one track, and the special reproduction speed.

The bit stream of the broadcast wave is transmitted using the macro block bit stream shown in FIGS.

The VCR bit stream output from the transposition circuit 45 is shown in FIGS. 37, 38 and 40.
43 is transmitted using the bit stream of the (non-) refresh block shown in FIG. 14． Block Layer Bit Stream Structure A block is composed of 64 DCT coefficients obtained by performing DCT on 8 × 8 pixels adjacent to each other for luminance or color difference. 6
The four DCT coefficients are subjected to a zigzag scan in the order shown in FIG. 10, and two-dimensional Huffman coding is performed using a combination of the run length of the zero coefficient and the amplitude of the non-zero coefficient to form a bit stream. At the end of the code of one block of DCT,
Add EOB Huffman code. 15. Superblock Layer Bitstream Structure A superblock is composed of eight luminance blocks next to each other in the horizontal direction 4 and the vertical direction 2 and a total of 10 blocks each of the U and V color difference blocks at the same position on the image. You. The order of inversion is Y ₀ , Y ₁ , Y ₂ , Y
₃ , Y ₄ , Y ₅ , Y ₆ , Y ₇ , U, V. As a DC component of the luminance signal, a value obtained by calculating a difference between adjacent blocks is sent. 16. Macro (non) refresh block address As described in Chapter 9, Section 9.1, realizing high-speed reproduction of the VCR requires rearrangement of refresh blocks. This will be described in detail below.

First, the relationship between the position of the macro block and the (non-) refresh block on the screen and the address is defined. 34 and 35 show examples of the address setting method.

As shown in FIG. 33, the macroblock is 1
It consists of one super block, one refresh block and ten non-refresh blocks. The address of the super block on one screen is set as shown in FIG. 16.1 Macro Block Address As shown in FIG. 34, the macro block address is assigned the same address value as that of the head super block of the macro block. 16.2 Refresh Block Address When set as in section 16.1, since the beginning of the macro block is a refresh block as shown in FIG. 33, the address value of the refresh block and the macro The block address values match. 16.3 Non-Refresh Block Address As the address of the non-refresh block, the immediately preceding address value of the non-refresh block is used.

That is, the macro block and (non-)
The addresses of the refresh blocks use the same address value. 16.4 Address Value As shown in FIG. 3, this address value is defined as follows: when the superblock position in the horizontal direction is x and the superblock position in the vertical direction is y. B. Address = 60x + y

Here, since DigiCipher uses four processors in the horizontal direction, I indicates this processor.
If D is the PID and the ID indicating the vertical position is the VID, the address value is MBA (Macro Block Address) = (60 · 11) · PID + 60 · x ₀ + VID RBA (Refresh Block Address) = (60 · 11) ) · PID + 60 · x ₀ + VID NRBA (Non Refresh Block Address) = (60 · 11) · PID + 60 · x ₀ + VID.

Here, x ₀ is the horizontal position of the macro / (non-) refresh block when PID = 0 and VID = 0.

Although FIGS. 34 and 35 show the case where x ₀ = 0, it goes without saying that x ₀ = _{0 to} 43 is used. Also this x ₀ corresponds to the frame count in the conventional example. 17． Macro (non-) refresh block bitstream structure 17.1 Macroblock bitstream structure The macroblock bitstream (FIG. 36) consists of macroblock overhead data, refresh block overhead data, non-refresh block overhead data, and refresh and non-refresh blocks. The variable length code of the block.

The following data is included in the macroblock overhead data.

Path ID (PSID _M ): ID indicating a path in a bit stream. When PSID = 1 and PID = 1, it passes through a path indicating a (macro) block ID and a (macro) block address. Also, PSID = 1, PID =
In the case of 2, it passes through the path of the Fill bits code length and the Fill bits code. Here, the Fill bits will be described. Since the code amount to be transmitted is constant, a predetermined code is forcibly inserted up to the transmission code amount when the band-compressed code amount is smaller than the transmission code amount. This code is called a Fill bits code, and this code length is called a Fill bits code length. PASSI
When D _M = 0, the signal passes through a path including a variable length code.

Processor ID (PID _M ): ID indicating four processors in one screen.

(Macro) block ID (BID): ID indicating the type of bit stream composed of a plurality of blocks and overhead data. Macro block ID, refresh block ID, non-refresh block ID
There are three types. Macro block I
D is used. When PSID and PID are set to predetermined values,
It passes through a path indicating a block ID.

(Macro) block address (MB
A): Indicates the position of the macro block on the screen. Chapter 13 1
Indicates the macroblock address described in section 3.1. Similarly to the block ID, when the PSID and the PID are set to predetermined values, this path is passed.

Macroblock quantization level: Chapter 10, 1
A quantization level set in macroblock units determined by the capacity of the rate buffer described in section 0.1. When no data is generated, setting this quantization level to a predetermined value allows the processing to proceed to the next macroblock without generating the (non-) refresh block overhead data and the variable length code of the (non-) refresh block. Can be. This is called skipping.

[0228] vertical ID (VID _M): Although not present in the bit stream, VID _M is defined in the following manner. 1
ID indicating the vertical position in the screen, 60 in the vertical direction
Since the number of macro-blocks are present, VID _M = 0 to 5
It becomes 9.

The overhead data and variable length code of the refresh block included in the macro block will be described in Chapter 17, section 17.2, Refresh block bit stream structure.

The overhead data and variable length code of the non-refresh block included in the macro block will be described in Chapter 17, Section 17.3, Non-Refresh Block Bit Stream Structure. 17.2 Refresh Block Bitstream Structure (FIG. 37) Refresh Block Bitstream Structure (FIG. 37)
Contains macroblock overhead data, refresh block overhead data, and one refresh block variable length code 0. This refresh block can be realized by selecting a high-speed playback mode in a macroblock bit stream structure. The macroblock overhead data is basically the same as in section 17.1, except that the block ID is the ID of the refresh block.
have. The address indicates the refresh block address.

The following data is included in the refresh block overhead data.

Refresh block code length: Indicates the total code length of the refresh block overhead data and the variable length code of the refresh block.

Refresh block correction quantization level:
A correction value between the macroblock quantization level and the refresh block quantization level. Output of the refresh block quantization level correction value circuit described in Chapter 10, section 10.3 Refresh block code amount control.

Field / frame discrimination: Discrimination whether the pixels of the refresh block are field-based or frame-based.

The variable length codes are as follows.

Refresh block variable length code (refresh block 0) Variable length code of a block to be refreshed among 11 super blocks in a macro block. 17.3 Non-Refresh Block Bit Stream Structure (FIG. 38) Non-Refresh Block Bit Stream Structure (FIG. 3)
8) includes macroblock overhead data, non-refresh block overhead data, and ten non-refresh block variable length codes 1 to 10.

The macroblock overhead data is
Same as 17.1, except that the block ID has the ID of the non-refresh block and the address indicates the non-refresh block address.

The non-refresh block overhead data includes the following data.

Non-refresh block code length: data length of non-refresh block overhead data, 1
Total code length of code lengths of 0 non-refresh blocks.

Non-Refresh Block Correction Quantization Level: The difference between the quantization level of the macro block and the quantization level of each of the ten non-refresh blocks.

Field / frame discrimination: Discrimination as to whether the pixels of each of the ten non-refresh blocks are field-based or frame-based.

PCM / DPCM discrimination: Each of the ten non-refresh blocks is processed in the frame (PC
M) or Inter-frame processing (DPCM).

Motion vector: The moving amount of the super block when predicting from the previous frame when the non-refresh block is in the DPCM mode.

The variable length codes are as follows.

Non-refresh block variable length code Non-refresh block 1 to non-refresh block 1
0 variable length code is included. 1 of the 11 super blocks in the macro block that is not refreshed
The variable length code of 0 super blocks is included. 18 slice layer, picture layer, O. P layer 18.1 Slice layer The slice layer is composed of one or a plurality of macro (non-) refresh blocks.

[0246] The head of the slice has an address value indicating the distinction between a macro slice, a refresh slice, and a non-refresh slice and a position in an image, so that data can be used even during high-speed reproduction or when an error occurs. .

The slice distinction and the address value are as follows.
In the macro and (non-) refresh block bit stream structures shown in FIGS. 36 to 38, by setting the PSID and PID to predetermined values, they can be set by passing through a path indicating a block ID and an address value. 18.2 Picture Layer A picture, that is, one picture, is composed of at least one or a plurality of slices. 18.3 G. O. P Layer (Group of Picture Layer) A GOP is composed of a plurality of picture layers. DigiCipher
, There are 44 superblocks in the horizontal direction, and the position of the macroblock in the horizontal direction is determined by the frame count value (FC).
O. Enter the P layer. 19. Macro slice layer, picture layer, O. P layer The macro slice layer indicates the order in which macroblocks are transmitted when a DigiCipher broadcast wave signal is transmitted.
(FIG. 39) This macro slice layer is the same as the macro picture layer because processing is performed on one screen. Then, one macroblock address is inserted into one screen. In FIG. 36, the macro block address is obtained by passing the path indicating the macro block address when the path ID and the processor ID are set to predetermined values. This also to set for each frame, the frame count value F · C _M and 1 macro blocks: are associated to one.

[0248] transmission order of macro-blocks of a macro-slice layer is a unit processor PID _M = 0 to 3, from the top to the bottom of the screen are sequentially sent to the VID _M = 0 to 59.

More specifically, using the example of the macro block address shown in FIG. 34, after transmitting the macro block address value first, the macro block is transmitted with the following macro block address. That is, the data is transmitted as 0, 660, 1320, 1980 1, 661, 1321, 1981 :::::.

In the next frame, the horizontal position x ₀ of the macro block is shifted by one, and after transmitting this macro block address value, the macro block is transmitted with the following macro block address. That is, 60, 720, 1380, 204061, 721, 1381, 2041 ::::: are sequentially transmitted in this order.

After the horizontal position x ₀ is sequentially shifted from ₀ to 43, it returns to x ₀ = 0 again. These 44 images are referred to as macro G. O. P layer. This is a cycle in which one processor handles the entire area of one screen, corresponds to the frame count F · C _M, and x ₀ = f (F · C
_CM ).

Further, since one screen is constituted by four processors, refresh is performed at a period of 11 frames.

Note that during normal reproduction of a recording medium such as a VCR, the macro slice layer, the picture layer, O.
Output from the recording medium using the bit stream structure of the P layer. 20. Refresh slice layer, picture layer, O.
As described in Section 9.1, “Refresh Block Code Swapping,” in Chapter 9, High-speed Playback Requirements, a predetermined number of refresh blocks must be added to the VCR to realize high-speed playback.
Must be recorded so as to be arranged in the sector on the tape pattern.

The refresh slice layer shows the configuration of the predetermined number of refresh blocks. That is,
The position of the refresh block on the screen, the number of refresh blocks to be put in the refresh slice, and their arrangement are shown.

With the configuration of this refresh slice,
The specifications for high-speed playback are determined. 40 and 41 show examples of the refresh slice layer.

The refresh picture layer indicates a refresh block for one screen. Refresh G. O. The P layer is composed of a refresh picture layer of 44 frames. Since refreshing of one screen is completed in a cycle of 11 frames, and each processor scans the entire area of one screen in a cycle of 44 frames, the frame count F · C
_R = 0 to 43 with 44 frames as the cycle. O. A P layer is formed.

The number of refresh blocks in one sector on the tape 26, that is, one refresh slice layer is one.
The average code amount per frame is determined by the number of tracks for recording, the number of drum rotations, the number of heads per scan, and the high-speed reproduction speed.

Hereinafter, the simplest case will be described.

When the tape format shown in FIGS. 18 and 23 is recorded, ie, one frame is recorded on one track and double speed reproduction is realized, one refresh picture layer has two refresh slice layers. Since the number of refresh blocks in one frame is 240,
Since 120 (= 240 （2) refresh blocks are inserted in one sector, one refresh block is inserted in the refresh slice layer.
Insert 20 refresh blocks. The method for inserting the refresh block is described in Sections 20.1 and 20.
There are two types of methods described in Section 2.

If the number of tracks per frame, the number of rotations of the drum, and the high-speed reproduction speed are determined to other specifications, one
What is necessary is just to set a predetermined number of refresh slices in the refresh picture layer.

When the VCR system is determined, the number of refresh blocks in a refresh slice is also uniquely determined. Also, the number of refresh slices in the refresh picture layer is uniquely determined. 20.1 Refresh Slice Layer Structure No. 1 A first method of arrangement of refresh blocks in the refresh slice layer is shown in FIG.

First, at the beginning of the refresh slice layer, the refresh block address of the first refresh block of the refresh slice is entered.

Since refresh slice 0 is the first refresh slice in the refresh picture layer, this refresh block address matches the macro block address in the macro slice layer described in Chapter 19.

Subsequently, a refresh block is arranged.

The arrangement of the refresh blocks in the refresh slice is such that the processors PID _R = 0, 1, 2, 3
Are sequentially transmitted to transmit vertical IDs VID _R = 0 to 29. This means that the four refresh blocks in the horizontal direction are sequentially transmitted on the screen and are transmitted vertically from top to bottom.

As a result, the 120 refresh blocks at the top of the screen are transmitted. Following the refresh block transmitted in refresh slice 0, refresh slice 1 sets PID _R = 0 to 3 and VID _R = 31 to 59.
To send out.

At the beginning of refresh slice 1, PI
A refresh block address determined by D _R = 0, VID _R = 30, and F · C _R is inserted.

In the decoder, the initial position can be known using the refresh block address. Also, PID _R
= 0, 1, 2, 3 to know the horizontal position, PID
By counting _R , the position in the vertical direction can be known.

[0269] It should be noted that, in FIG. 40, but is shown as there is a refresh slice delimiter to switched eyes of VID _R, may be set a break of the refresh slice even switched eyes of PID _R. 20.2 Refresh Slice Layer Structure No. FIG. 41 shows a second method of arrangement of the 2 refresh blocks. This method is a method of sequentially transmitting refresh blocks adjacent in the vertical direction per processor.

In this case, PID _R is fixed and VID _R
= 0 to 59 in order, then change the PID _R ,
Further transmitted in the order of VID _R = 0 to 59.

The second method is advantageous in terms of image quality when the high-speed reproduction speed is high because adjacent refresh blocks in the same frame can be transmitted. This is because, at the time of high-speed reproduction, adjacent regions of the same frame can be reproduced largely.

[0272] In the decoder knows the initial position using a refresh block address, by counting the period PID _R is fixed, it is possible to know the position in the vertical direction. Furthermore, when the PID _R value changes, the PI
It is possible to know the horizontal shift amount using the value of D _R = 0 to 3. 21. Non-refresh slice layer, picture layer,
O. P layer 21.1 Structure in the non-refresh slice layer The non-refresh slice layer indicates a transmission order and a transmission break when transmitting the non-refresh block shown in FIG.

The transmission order of the non-refresh blocks is always the same as the transmission order of the macro blocks, and the PID _NR
Repeats 0, 1, 2, 3 sequentially. VID _NR is 0
To 59 are sequentially transmitted.

That is, in the example of FIG. 42, non-refresh block addresses 0, 660, 1320, 1980,
, 661, 1321, 1981,..., And in the next frame, the horizontal position x ₀ is shifted by one superblock, and 60, 720, 1380, 2040,
61, 721, 1381, 2041,...

By making the sending order of the macro blocks and the sending order of the non-refresh blocks the same, the signal processing during normal reproduction is simplified. In order to satisfy this condition, the refresh slice layers are sequentially transmitted as refresh slices 0 to 2. 21.2 Break of Non-Refresh Slice Layer Next, the break of the non-refresh slice layer will be described.

A non-refresh picture including a non-refresh block for one screen contains one or more non-refresh slices. This non-refresh slice is divided into two types.

First, at the switching point of the frame, that is, at the break of the non-refresh picture layer, a break of the non-refresh slice is inserted.

The second method is a method of inserting a non-refresh slice break in order to realize high-speed reproduction of a VCR.

As described in Chapter 9, Requirements for High-Speed Playback, section 9.1, Refresh Block Code Swapping
It must be placed in a sector on the R tape pattern.

In order to realize this arrangement, it is necessary to insert a break in the non-refresh slice layer so that the refresh slice falls within the sector.

Note that the number of refresh blocks in the refresh slice layer is arbitrarily changed according to the code amount allocated to the non-refresh slice layer.

A non-refresh block address is placed at the head of the non-refresh slice layer. 22. VCR picture layer G. O. When recording on the P layer VCR, the above-mentioned refresh slice and non-refresh slice are combined and transmitted.

FIG. 43 shows this combination method, in which the code transmission indicated by the solid line is performed. As described in Chapter 21, non-refresh slices are transmitted in the order of non-refresh slices 0, 1, and 2.

Also, during this non-refresh slice,
Insert a refresh slice. That is, if the non-refresh slice is NRS (Non Refresh Slice) and the refresh slice is RS (Refresh Slice), NRS0, RS0, NRS1, RS1, and NRS2 are transmitted in this order.

Here, the sending order of the non-refresh slices is always sent in the order of 0, 1, and 2. However, the sending order of the refresh slices may be sent in the order of NRS0, RS1, NRS1, RS0, NRS2. good.

The refresh slice transmission order is VC
It is determined by the design method of the reproduced image for high-speed reproduction of R.

In FIG. 43, the part shown by the dotted line is the VC
R when the recording code is transmitted to the refresh slice and the non-refresh slice.
O. The relation of the P layer is shown.

The refresh slice is arranged in consideration of recording in the sector of the VCR, and the non-refresh slice is arranged between the refresh slices, but the switching of each picture layer can be set independently.
The transmission order of each picture layer is F · C _R = 0.
To 43, and it sends in the order of F · C _NR = 0~43. 23. Data multiplex format When the bit stream described in Chapters 13 to 22 is recorded by the A head and the B head through the output terminal 69 in FIG. 1, a signal necessary for the VCR is added and recorded.

FIG. 44 shows the VCR data multiplex format.

FIG. 29 is a diagram showing transmission data of track 0. The horizontal axis corresponds to the period of one unit described later,
The vertical axis corresponds to the number of units recorded on one track. Here, since the case where the average code amount of one frame is recorded on one track is described, the vertical axis also corresponds to the average code amount of one frame.

The right end shows an example of a switching point between a video signal and an audio signal and a switching point between sectors.

In the non-refresh block bit stream structure of FIG. 42, VID _NR = v ₁ and VID _NR =
the method of determining the v ₂ is, in the sector S ₀ of the refresh slice 0 is the track T _0, as refresh slice 1 is placed in a sector S ₁ of the track _{T 0 VID NR = v 1,} v
Decide ₂ .

As described above, after arranging the codes of the non-trick block and the trick block, as shown in FIG. 44, the sync signal, (non-) non-refresh block position, non-refresh block address, other additional information, and error correction A sign is added and recorded. 23.1 Unit Sync Since VCRs have jitter due to uneven rotation of cylinders, track jumps during special reproduction, etc., it is necessary to add a unit sync signal at a predetermined cycle. Here, one period of the sync signal is referred to as one unit.

Definition of words Unit: One period of sink in transmission data to VCR. During this period, the sync, additional information, non-refresh block position code, (N-) R. B. P, non-refresh block address code (N-) R. B. P,
And (non-) refresh slice codes, error correction codes, and the like.

Also, the VCR set in this unit period
Is called a unit sync.

Definition of words Unit sync: A VCR sync set for one unit, and additional information for the VCR is recorded after the unit sync.

As additional information, a unit sync number,
Examples include video / audio identification, track numbers, unit numbers, and the like.

Also, an error correction parity is added for VCR error correction. 23.2 (Non-) Refresh Block ID (Non-) Refresh Block ID is described in Sections 23.3 to 2
When the block indicating the (non-) refresh block frame address position described in section 3.5 is a non-refresh block, the (N-) R. B. When ID = 0 and refresh block, (N-) R. B. Indicates ID = 1. 23.3 (Non-) Refresh Block Frame The (non-) refresh block frame indicates the frame number of the block indicated by the (non-) refresh block position. 23.4 (Non-) refresh block address (N
-) R.I. B. A (non-) refresh block address (N-) R.
B. A indicates the projection position information of each block.

Since each block is composed of a variable length code, the switching point of the block is not fixed.
Thus, the address (N-) R. Of the first (non-) refresh block entering each unit. B. A is shown. 23.5 (Non-) Refresh Block Position (N-) R. B. Since the P variable length code and the inter-frame DPCM processing are used, the starting point of the block is not fixed. Therefore, this starting point is indicated by a (non-) refresh block position.

When arranging the refresh slice between the non-refresh slices, the refresh slice is inserted so as to necessarily indicate the position of the head block of the refresh block by the refresh block position code.

A unit may include a plurality of refresh blocks and non-refresh blocks. In this case, the position indicated by the refresh block position is
Indicates the position of the first (non) refresh block that appears.

Therefore, the head block of the refresh slice is arranged so as to appear first in the unit.

When the recordable code amount is larger than the transmission data code amount, an empty area may be set and the head block of the refresh slice may be arranged from the head position in the unit. At the time of high-speed reproduction, since the head traces while traversing the track, the envelope is maximized when the head completely matches the track, and otherwise the envelope is necessarily small. This indicates that the error rate increases, and that it may become impossible to reproduce.

On the other hand, in order to use the refresh slice as a reproduction signal, it is necessary to know the start position of the head code of the refresh slice.
-) R.I. B. The P signal must be reproduced.
This (N-) R. B. In order to detect the P signal, the unit sync signal must be detected.

Therefore, by arranging the refresh block from the head position in the unit, it is possible to minimize the influence of the smaller envelope.

Further, when a free area is set and the head block of the (non-) refresh slice is arranged at the head position in the unit, code replacement in the decoder uses only the (non-) refresh block ID to perform refresh. Since the blocks and the non-refresh blocks can be allocated to different FIFO memories, there is an advantage that the code re-interchange can be easily configured. 23.6 Specific Example FIG. 45 shows a specific example of the (non-) refresh block ID, frame, address, and position index signals.

FIG. 45 (a) is an enlarged view of a unit relating to the image of FIG. In the figure, the (non-) refresh block ID [(N-) R. B.
ID] (non-) refresh block frame [(N-) R.
B. Frame] (non-) refresh block address [(N-) R.
B. Address] (Non-) refresh block position [(N-)
R. B. Position] at which the index signal is inserted.

[0308] Also, the position where the variable length code is inserted is shown.
To indicate the switching position of the block in the unit,
The position of the code amount is shown from 0 to 150 above.

[0309] Figure 45 (b), the refresh block R. frame number F ₆ It shows the value of the index signal to be inserted when B ₀ is the first block in the unit.

R. B. ID = 1 R.I. B. F = 6 R.F. B. A = 0 R.S. B. P = 50.

[0311] Figure 45 (c) is a non-refresh block N. frame number F ₁₀ R. When B ₇₁₀ is the first block in the unit, it indicates the value of the index signal to be inserted.

R. B. ID = 0 R.I. B. F = 10 R.F. B. A = 710 R.A. B. P = 50.

In the VCR data multiplex format, only additional information such as an index is added.
There is no requirement for video source coding from this format.

Therefore, the content of the video information is not deteriorated by this format. 23.7 Additional Information The additional information in FIG. 44 includes a unit number, a track number, and the like. By inserting these pieces of information, the slow reproduction can be realized by rearranging the units according to the unit number during the slow reproduction.

Further, at the time of high-speed reproduction, this unit number is used to reproduce a specific position of a track. That is, servo is performed so that the envelope at the position where the refresh slice is arranged is maximized. 24. Code replacement circuit Regarding the configuration of the code replacement circuit 45 at the time of recording, FIG.
This will be described in detail with reference to FIG.

[0316] The case where a bit stream transmitted by a broadcast wave is input to the output terminal 68 will be described. If it becomes possible to process when a broadcast wave bit stream is input,
Necessary items for recording only in the VCR are included. Therefore, this case will be described.

First, since the bit stream input to the output terminal 68 has the macroblock format shown in FIG. 36, this macroblock is separated into refresh blocks and non-refresh blocks. The separated (non-) refresh block is stored in the (non-) refresh block memories 45a and 45b.

To perform this separation, a (non-) refresh block memory write control circuit 45c generates a necessary timing signal.

In order to generate this timing signal,
The NMP detection circuit 45d first determines the start position of the frame, and the overhead data detection circuit 45e detects the path ID.
(PSID), processor ID (PID), macroblock quantization level Q _M , refresh block code length L
_R detects overhead data of the non-refresh block code length _LNR .

[0320] Using these overhead data,
The (non-) refresh block memory write control circuit 45 c
a and 45b are supplied to terminal 45
f, generated from 45 g.

The write timing will be described with reference to FIG.

FIGS. 47 (a) and 47 (b) show bit streams when transmitted as broadcast waves. FIG.
(A) is overhead data, and PSID indicates a path in the bit stream. VID, P
The ID is the ID shown in FIG. Note that VID is not included in the bit stream. When the macro block quantization level Q _M is set to Q _M = 31, a skip operation is performed.

In FIG. 47B, black squares indicate macro (non-) refresh block addresses, and squares indicate macroblock overhead data. Also, L
_R is the overhead data of the refresh block and the code length of the variable length code.

Only the bit streams shown in FIGS. 47 (c) and 47 (d) are extracted from the macro block bit stream of FIG. 47 (b) and stored in the (non) refresh block memories 45a and 45b, respectively.

FIG. 47C shows a signal to be written into the refresh block memory 45a. That is, the macro block address, macro block overhead data, refresh block overhead data, and variable length code are written.

Since an address is inserted at the head of the slice layer, a refresh block address is inserted at the head of the refresh slice layer as shown in refresh slice 1. This operation is shown in FIG.
(Non-) refresh block address generation circuit 70
4A, an address is generated and output from a terminal 45h.
6 is inserted by the address insertion circuit 45i.

FIG. 47D shows a signal to be written to the (non-) refresh block memory 45b. That is,
The macro block address, macro block overhead data, (non-) refresh block overhead data and variable length code are written.

Further, as shown in the (non-) refresh slice 1, a (non-) refresh block address is inserted at the head of the non-refresh slice. This (non-) refresh block address is inserted using the (non-) refresh block address generation circuit 70a and the address insertion circuit 45i in FIG.

Next, the memory read (non-) refresh slice coupling control circuit 70 will be described.

First, the points in combining (non-) refresh slices will be described. FIG. 49 shows an envelope at the time of high-speed reproduction of the VCR.

FIG. 49A is a diagram showing a part of the tape and the track shown in FIG. 23 and a part of the head trace at 2 × speed. The corresponding envelope is shown in FIG.
(B).

In FIG. 49 (b), the portion shown by the solid line shows the envelope shape that can be reproduced by the head, and where the envelope is large, the error rate is small.

Therefore, the point when arranging refresh slices between non-refresh slices is to arrange refresh slices around the point where the envelope becomes maximum.

Therefore, a process of arranging refresh slices is performed at the time of recording, centering on a predetermined position on the track. At the time of high-speed reproduction, servo is performed so that the head traces the center value of the refresh slice.

[0335] Memory read (non -) in the refresh slice coupling control circuit 70, first, by using the refresh block length L _R input from the terminal 45j, in the refresh slice code amount calculator 70b, calculates a refresh slice code amount.

In the refresh slice arrangement position designation ROM 70c, the recording code amount of one sector and the position where the head traces each track during high-speed reproduction are stored.

Using the refresh slice code amount and the refresh slice arrangement position, the (non-) refresh slice / refresh slice connection point determination circuit 70d determines the switching point between the refresh slice and the non-refresh slice. In order to make this determination, the non-refresh block code amount calculation circuit 70e calculates the sum of the code amounts of each non-refresh block. Using this, the (non-) refresh slice connection points v ₁ and v ₂ shown in FIG. 42 are determined so that the center point of the refresh slice is located at a predetermined position on the track.

The (non-) refresh block memory read control circuits 70f and 70g read the respective codes from the (non-) refresh block memories 45a and 45b using the (non-) refresh slice connection points.

The switch 45j is switched accordingly.

The (non-) refresh block address generation circuit 70a generates a (non-) refresh block address using a (non-) refresh slice connection point. This address is inserted into the bit stream by the address insertion circuit 45i. 25. Basic Structure of Decoder The basic structure of the decoder will be described in detail with reference to FIG.

First, a VCR mode signal such as normal reproduction / high-speed reproduction from a user is input to a reproduction speed setting circuit 72 through a terminal 71.

The tape feed control circuit 73 and the track reproduction control circuit 74 control the rotation phase of the drum and the phase of the tape feed speed by applying the servo of the VCR. Particularly at the time of high-speed reproduction, servo is performed so as to read the area where the refresh slice is recorded.

As a result, the signals recorded on the tape 26 are read out using the A head and the B head. The read signal passes through a switch 75 for switching between the A head and the B head, and after being subjected to reproduction waveform equalization and the like, is input to an error correction circuit 76 and a unit sync detection circuit 77.

The unit sync detection circuit 77 detects a sync signal inserted in each unit. This eliminates the effects of VTR jitter and the like. Each unit is grasped by detecting this sync signal, and the index detection circuit 78 detects the index signal shown in FIG. In the figure, the upper part of the bold line is the index signal. From the (non-) refresh block position signal detected by the index detection circuit 78, the start point of the (non-) refresh block is grasped. Also,
Using the (non-) refresh block ID, a distinction is made between non-refresh and refresh of the (non-) refresh block starting at this start point.

Also, by detecting the (non-) refresh block frame and the address, the projection position of the (non-) refresh block and the order of the projected frames can be known.

Next, the code length detection circuit 79 receives the (non-) refresh block position [(N-) R. B. P], the head position of the (non-) refresh block is detected, and the (non-) refresh block code length included in the overhead data of the (non-) refresh block is detected.

By using the (non-) refresh block code length, it is possible to clarify the delimiter of the (non-) refresh block, to sequentially detect overhead data and grasp the position of the variable length code.

In FIG. 50, code length detection circuit 79
Although the overhead data detection circuit 81 is shown as another configuration, the code length detection circuit 79 is included in the overhead data detection circuit 81.

FIG. 51 shows the relationship between an index used in each circuit and overhead data. In each circuit, signal processing is performed using the index marked with a circle and overhead data.

The code reordering circuit 82 separates the (non-) refresh slice and the refresh slice from the VCR picture layer bit stream shown in FIGS. 40 to 43 using the (non-) refresh block ID.

Also, the separated (non-) refresh slice is stored in the refresh memory and the non-refresh memory in the code reordering circuit 82, respectively.

At the time of normal reproduction, reading is performed while switching between the refresh memory and the non-refresh memory having the same (non-) refresh block address in the code reordering circuit 82, the non-refresh block and the refresh block are combined, and the macro block is read. The signal is output from the code re-interchange circuit 82 through the terminal 83.

A VCR normal reproduction bit stream and a broadcast wave bit stream have the same macroblock configuration. When a broadcast wave bit stream is input, it is input from a terminal 83.

In the case of a bit stream of a broadcast wave, overhead data is detected and decoded using an overhead data detection circuit 81. Since the operation at the time of normal reproduction is the same as the operation of decoding the broadcast wave, this operation will be described first.

First, in the bit stream of the macroblock shown in FIG. 36 at the terminal 83, the variable length code of the (non-) refresh block is input to the variable length code decoding circuit 84. When extracting the variable length code, the variable length code is extracted from the bit stream by decoding the (non-) refresh block code length in the overhead data and the overhead data. The variable length code decoding circuit 84 sequentially detects the Huffman code by comparing the code with the Huffman table from the head position of the variable length code. Using the detected Huffman code, the subsequent number of zero coefficients (run length) and non-zero coefficient (amplitude) of the quantized DCT coefficients are obtained. Since these coefficients are arranged in the order in which the zigzag scan was performed,
The order of the coefficients is rearranged as required by the inverse DCT circuit 85.

The signal obtained by decoding the variable length code is input to the inverse quantization circuit 86. In the inverse quantization circuit 86, the macroblock quantization level is corrected by the (non-) refresh block correction quantization level, and the quantization level is obtained for each superblock.

Next, each of the 64 coefficients per block is first multiplied by a weight value according to the weight table.

Then, inverse quantization is performed by multiplying each of the 64 coefficients by a quantization scale value in accordance with the quantization level in units of super blocks, thereby obtaining DCT coefficients. (Here, the case of the second quantization method described in Chapter 8 has been described.) The 64 DCT coefficients are passed through the inverse DCT circuit 85, and the coefficients in the frequency domain are transformed into the time domain. Then, a signal of 64 pixels of 8 pixels in the horizontal direction and 8 pixels in the vertical direction is obtained.

The output of the inverse DCT circuit 85 is added to the adder 87
To enter.

The signal of the switch 88 is input to the adder 87 and added to the output signal of the inverse DCT circuit 85. The switch 88 is controlled by an intra-frame / inter-frame switching circuit 89. The output signal of the adder 87 is input to the deblocking circuit 90 and also to the frame delay circuit 91.

The frame delay circuit 91 is composed of a frame memory. The output signal of this frame memory is input to the motion compensation circuit 92 and the deblocking circuit 90.

The output signal of the motion compensation circuit 92 is input to the switch 88.

The non-blocking circuit 90 uses the signals of the adder 87 and the frame delay circuit 91 to perform the band compression signal processing and the processing for matching the projection order of the TV scanning lines, and the luminance signal and the color difference signals U, V is output from the output terminals 93 to 95.

The operation of the decoder includes intra-frame processing and inter-frame processing. In the switch 88, the switch 8
When the switch 8 is off, the process is performed within a frame, and when the switch 88 is turned on, the process is performed between frames. The on / off switching circuit 89 controls the on / off of the switch 88.

PCM / DPC in overhead data
The M discrimination signal is input to the intra / frame switching circuit 89 through the terminal 96. Here, PCM is in the frame, D
PCM indicates inter-frame processing. The switch 88 is turned off by PCM, and the switch 88 is turned on by DPCM. As described in Chapter 3, the intra-frame / inter-frame processing includes image adaptive intra-frame processing and refresh (forced intra-frame processing).

First, the operation of the intra-frame processing will be described.

At the time of processing within a frame, the output signal of the inverse DCT circuit 85 is input to the frame delay circuit 91 and the deblocking circuit 90, and the luminance signal Y and the color difference signals U and V are output. Next, the operation of the inter-frame processing will be described.

In this case, the prediction signal of the previous frame stored in the frame delay circuit 91 is read out and input to the motion compensation circuit 92.

Also, the motion vector of the overhead data is input from the terminal 96 to the motion compensation circuit 92, and the position of the prediction signal on the screen is shifted. A predicted signal corresponding to a position corresponding to the position on the screen of the output signal of the inverse DCT circuit 85 is
The signal is output from the motion compensation circuit 92, passed through the switch 88, and input to the adder 87. In the adder 87, the inverse DCT circuit 8
5 is added to the prediction signal, and input to the frame delay circuit 91 and the deblocking circuit 90. Then, the luminance signal Y and the color difference signals U and V are separated and output from terminals 93 to 95.

The above-described write processing to the variable-length code decoding circuit 84, the inverse quantization circuit 86, the inverse DCT circuit 85, and the frame delay circuit 91 in the normal reproduction of broadcast waves and recording media is always performed on the basis of macroblocks. I will do it.

That is, the processing of these circuits per processor is based on the sequential processing of 11 super blocks in a macro block, and the macro blocks are sequentially processed from top to bottom on the screen. 26. High-speed playback Next, the operation at the time of high-speed playback will be described in detail.

First, the code reordering circuit 82 reads only the refresh memory that stores the refresh slice from the bit stream.

Since the refresh slice contains the refresh block address, frame ID, and processor ID, the overhead data can be detected by the overhead data detection circuit 81 to determine the projection position.

Thus, the write memory address corresponding to the video position when writing to the frame memory in the frame delay circuit 91 can be determined.

At the time of high-speed reproduction, only refresh blocks are valid as projection data, and data of non-refresh blocks are not valid. Therefore, based on only the refresh block, write processing to the variable length code decoding circuit 84, the inverse quantization circuit 86, the inverse DCT circuit 85, and the frame delay circuit 91 is performed.

Since the refresh block is always an intra-frame process, the intra-frame / inter-frame switching circuit 89 designates an intra-frame process. That is, the switch 88 is always off.

There is only one refresh block in a macroblock. Therefore, in one screen, there is only a method of transmitting refresh blocks in 11 super blocks in the horizontal direction or transmitting refresh blocks continuously in the vertical direction. This is different from the sending order of the pixels according to the scanning line. Therefore, during high-speed reproduction, the data of the refresh block is sequentially written into the frame memory of the frame delay circuit 91. Thereafter, the data in the frame memory of the frame delay circuit 91 is read out in the order of sending out the pixels according to the scanning lines, and a high-speed reproduced image is obtained. 27. FIG. 52 is a diagram showing a configuration of the code re-shuffling circuit 82. As shown in FIG. A terminal 97 receives a signal obtained by correcting an error in the reproduced bit stream from the VCR.

The bit stream structure has the bit stream structure shown in FIGS. 37, 38, and 40 to 43. Therefore, first, a refresh slice and a non-refresh slice are separated by the switch 82a. This switch 82a is switched by inputting (non-) refresh block ID and (non-) refresh block position signal, which are indexes of the VCR data multiplex format shown in FIG.

Thus, the refresh slice is stored in the refresh block memory 82b and the non-refresh slice is stored in the non-refresh block memory 82c.

Next, at the time of normal reproduction, signals from the refresh block memory 82b and the non-refresh block memory 82c are read using the switch 82d using the refresh block memory read circuit 82e and the non-refresh block memory read circuit 82f.

At this time, reading is performed so that the refresh block address shown in FIG. 35 and the non-refresh block address match.

Thus, during normal playback, the terminal 83
As shown in the example in FIG. 34, a signal is output in the configuration of the variable length code of the macro block.

The non-refresh block memory read circuit 82f calculates the address of each non-refresh block from the non-refresh block address of the refresh slice layer and the processor ID. A macro block is configured using this address. The code is read from the non-refresh block memory 82c using each non-refresh block code length.

The refresh block memory read circuit 82e calculates the address of the refresh block from the refresh block address of the refresh slice layer and the processor ID. There are two types of refresh slice configuration methods shown in FIGS. In either case, the refresh block memory read circuit 82e generates an address so that the output of the refresh block memory 82b can form a bit stream of a macroblock. That is, the refresh block memory read circuit 82e
Can also exchange refresh blocks.

When performing this read, the refresh block memory read circuit 82e performs processing using the refresh block code length.

At the time of high-speed reproduction, the switches 82a and 82d
Only b is selected, and only the refresh block is transmitted from the terminal 83. In the above-described configuration, separation into four processors is performed using the switch 99.

FIG. 53 shows another embodiment of the code reordering circuit 82. This configuration is a circuit configuration suitable for the refresh slice layer shown in FIG.

In FIG. 41, refresh blocks in the refresh slice layer are arranged such that refresh blocks adjacent in the vertical direction are consecutively arranged. Therefore, the refresh block memory 82b in the code reordering circuit 82
Each processor has refresh block memories 82b1 to 82b4. Each memory stores a refresh block corresponding to each processor. At the time of reading for normal reproduction, the non-refresh block and the switches 82g to 82j are combined to form a macro block.

At the time of high-speed reproduction, the switch 82a selects only the refresh block and writes the refresh block in the refresh block memory 82b. Also, switches 82g to 82
j reads only the refresh block memory 82b. 28. Frame Delay Circuit As shown in FIG. 54, the frame delay circuit 91 has two memory write address generation circuits 91a and 91b. The output of the two address generation circuits 91a and 91b is switched by the switch 91c based on the normal / high-speed reproduction setting signal input from the terminal 71.

In the case of DigiCipher, processing is performed by four processors, and four macroblocks exist in the horizontal direction. Therefore, one macroblock is processed in the horizontal direction per processor.

Therefore, per processor, the macro blocks are processed from top to bottom in units of 11 super blocks in the macro block.

The circuits for performing the processing by the four processors include a variable length code decoding circuit 84, an inverse quantization circuit 86, an inverse D
A CT circuit 85, an adder 87, a motion compensation circuit 92, an intra-frame / inter-frame switching circuit 89 and a switch 88, and write address generation circuits 91 a and 91 b in a frame delay circuit 91.

The distribution of codes to the four processors is performed using the processor ID (PID) included in the macroblock overhead data.

Since the operations of the four processors are the same, the operation of one processor will be described.

At the time of normal reproduction, the switch 91c selects the normal reproduction write address generation circuit 91a. Since the bit stream at the time of normal reproduction is the bit stream of the macro block shown in FIG. 36 and FIG. 39, the projection start is performed using the macro block address at the head of the macro picture layer, that is, the macro slice layer. The position is determined, and then the address for normal reproduction is sequentially generated using the processor ID.

FIG. 55 shows the operation of the normal reproduction / write address generation circuit 91a.

First, the macro block address at the head of the macro slice layer is stored in the overhead data detection circuit 8.
1, and is input from a terminal 96 to a normal reproduction / write address generation circuit 91a.

FIG. 55 shows an example in the case of the processor 1.

First, the M.D. B. A =
Read 0. This M. B. A = 0 indicates the projection position of the head super block of the macro block of the processor 0.

The projection position of the super block at the head of the macro block of the processor PID is represented by the following equation. When the processor PID = 1, the head super block address of the macro block is 660 as shown in the following equation.
Becomes S. B. A = M. B. A + 660 × PID = 0 + 660 × 1 = 660 During normal reproduction, as shown by the arrow in FIG. 55, first, one macroblock in the horizontal direction, that is, S.D. B. A = 66
.., 1260, 11 superblocks are processed, and one macroblock is processed in the vertical direction. That is, S.I. B. After A = 1260, S.P. B. A = 6
, 1261 are processed.

At the time of high-speed reproduction, the high-speed reproduction mode is input to the terminal 71, and the switch 91c selects the high-speed reproduction write address generation circuit 91b. The high-speed reproduction write address generation circuit 91b is used for high-speed reproduction of package media such as a VCR. At the time of high-speed reproduction, only the blocks processed within the frame are valid, so only the data of the refresh block is written.

At the time of high-speed reproduction, the code re-interchange circuit 82 outputs only the refresh block from the terminal 83. Variable length code decoding circuit 84, inverse quantization circuit 8
6. The inverse DCT circuit 85 processes only this refresh block, and inputs only the refresh block from the terminal 100 to the frame memories 91d to 91f.

In the case of DigiCipher, only data of one refresh block in one macroblock is written.
That is, since the refresh blocks are adjacent to each other in the vertical direction, during high-speed reproduction, the position of the super block in only the vertical direction is generated by the high-speed reproduction address generation circuit 91b. Note that non-refresh blocks are not processed at all. When processing a refresh slice composed of refresh blocks, DigiCipher performs processing with four processors, so that one refresh block per processor is provided in the horizontal direction.

Therefore, the operation of the high-speed reproduction write address generation circuit 91b is the same for both the bit streams of the refresh slice layers No. 1 and No. 2 shown in FIGS.

At the time of high-speed reproduction, only the bit stream of the refresh slice layer shown in FIGS. 40 and 41 is used. Since the bit stream of the refresh slice layer contains a refresh block address (RBA) at the head of the refresh slice,
This R. B. Using A and processor ID (PID),
Know the initial position of the high-speed reproduction signal processing of each processor.

Description is made with reference to the example of FIG.

A terminal 96 outputs a refresh block address R.R. B. A is input to the high-speed reproduction write address generation circuit 91b. The correspondence between refresh block G _n of the track pattern of the refresh slice and 23 in FIG. 40 is set as follows, describes the case of performing tracing x ₀ of double-speed playback. Refresh slice 0: G _n (0) Refresh slice 1: G _n (1) In this case, the refresh block address is R.R. B. A = 0 and R.A. of refresh slice 1 B. A = 90 is reproduced. This R. B.
A = 0, R.A. B. A = 90 indicates the projection position of the first refresh block of the processor 0.

The projection position of the head super block of the refresh block of the processor PID is represented by the following equation. Therefore, when the processor PID = 1, the head super block address of the refresh block is S.P. B. A = 660, in the case of refresh slice 1, S.A. B. A = 750. S. B. A ₀ = R. B. A + 660 × PID = 0 + 660 × 1 = 660 B. A ₁ = R. B. A + 660 × PID = 90 + 660 × 1 = 750 In the case of DigiCipher, since refresh blocks are arranged in the vertical direction, not necessarily per processor, the high-speed reproduction address generation circuit 91b is superimposed in the vertical direction. Generate block addresses. That is, B. A ₀ : 660,661,..., 687,68
8,689 S.M. B. A ₁ : 750, 751, ..., 777, 77
The super block address is generated in the order of 8,779.

Next, the read address generation circuit 91 g
The luminance signal Y and the color signals U and V are read out according to the scanning line order of the TV.

The frame delay circuit 91 and the memory write / read address generation circuits 91a, 91b, 91g also function as the non-blocking circuit 90. 29. Track reproduction control circuit During recording, the refresh slice is recorded around a predetermined position of the track, so that during high-speed reproduction, the tape feed and drum rotation phase are controlled so as to reproduce this predetermined position. There are various methods for performing this control as follows.

[0411] 1. The position to be traced by the head during high-speed reproduction is recorded on a linear track. 2. The signal identifying the track is recorded on the helical track. The identification signal includes a pilot signal and the like.

[0412] 3. The track number and unit number are recorded on the helical track, and servo is applied so that the envelope of the unit number to be read during high-speed reproduction is maximized.

[0413] The third method will be described in detail.

First, the unit number and the track number are read as additional information arranged after the unit sync of the VCR transmission data in FIG. 44, and read from the terminal 101 in FIG. Refresh slice arrangement position designation R in FIG.
In the OM 70c, a predetermined position on the track is
Refresh slice is recorded. This predetermined position is determined by the track number and the unit number. On the other hand, at the time of high-speed reproduction, the RF signal reproduced from the head is input to the envelope detection circuit 103 from the terminal 102.

In the envelope detection circuit 103, FIG.
The envelope shape at the time of high-speed reproduction shown in FIG. The track reproduction control circuit 74 controls the rotation phase of the drum and the tape feed so that the envelope of the track number and the unit number where the center position of the refresh slice exists is maximized. 30. Other Embodiment 1 of Macroblock Bitstream Structure The macroblock bitstream structure described in Chapter 17, Section 17.1 (FIG. 36) shows a configuration in which the format converter of the VCR is the simplest.

In the bit stream structure shown in FIG.
The R format converter does not need a variable length code decoding circuit. Also, the detection of overhead data may be performed only by detecting macroblock overhead data.
The overhead data detection circuit may have a minimum configuration.

[0417] The bit stream of the broadcast wave may be configured by incorporating only the necessary items for the broadcast wave, and therefore various bit streams are conceivable. In this case, the format converter of the VCR only needs to have a circuit necessary to generate a bit stream (FIGS. 37, 38, and 40 to 43) required for the VCR.

FIG. 57 shows another embodiment 1 of the macroblock bit stream structure. In this bit stream structure, it is necessary to detect all overhead data. On the other hand, at the time of recording, since the bit stream structure contains the refresh block code length, there is no need to decode the variable length code.

[0419] With respect to the bit stream of Fig. 57, items that have been used conventionally will be described first. This content is based on the following two documents, and indicates an exhibit document number. (a) “DigiCipher Description” Aug. 22 1991 (b) “Channel compatible DigiCipher HDTV System”
April 3. 1992 Each item of the bitstream is described in detail.

In FIG. 57, the bit stream structure in the macro block is composed of overhead data and variable length codes.

Processor ID: Since DigiCipher uses 4 processors, the number of this processor is indicated by 2 bits (b).

Macro block quantization level (MQL):
The quantization level QL is represented by 5 bits. The larger the value, the coarser the quantization, and the macroblock quantization level MQ
L = 31 indicates a state where no code is generated.
When QML = 31, overhead data and variable length codes are skipped after QML as shown in FIG. 57, and the process proceeds to the next macroblock.

[0423] 2-bit correction quantization level: A correction quantization level is set in a direction in which quantization is coarser than the macroblock quantization level MQL (a). The correction quantization level is 2 bits per super block.
(b). Also, the setting is made for 11 super blocks (a).

Corrected quantization level path PQL: If the quantization levels of all superblocks are the same as the macroblock quantization levels, the 2-bit correction quantization levels are all 0, and in this case, the 2-bit correction No quantization level is set. That is, when PQL = 1, the path does not pass to the 2-bit correction quantization level, and when PQL = 0, the path passes to indicate the 2-bit correction quantization level (b).

Field / frame discrimination: DCT 8 ×
The pixel configuration of eight pixels specifies whether to use field pixels or frame pixels, and is set for each superblock (a).

[0426] PCM / DPCM discrimination: A super block is processed in a frame (PCM) or processed between frames (DPC
M) Distinguishing (a).

Motion vector: A motion vector of each super block is shown (a).

Next, a new bit stream configuration will be described.

[0429] Path ID (PSID): When PSID = 0, the path passes through the path where the macroblock quantization level exists. When PSID = 1, the processor ID (P
ID)).

[0430] When PID = 0, it passes through the path where the high-speed reproduction mode (TRK) exists.

When PID = 1, it passes through a path where a block ID and a block address exist.

When PID = 2, it passes through the path where the Fill Bits code length and the Fill Bits code exist.

Trick quantization level TQL: At the time of high-speed reproduction of a VCR, only refresh blocks can be used. Also, a plurality of refresh blocks may exist in one macro block. If the plurality of refresh blocks exist, the following 2
You need points.

First, when a plurality of refresh blocks having different frames exist in one macro block, 5 refresh blocks are assigned to each refresh block.
A bit quantization level is required.

Second, the position of the refresh block in the macro block must be specified.

To specify this position, it is necessary to skip in units of super blocks. Therefore, at the time of high-speed reproduction of the VCR, the setting is made so as to pass through the path of the trick quantization level TQL.

The trick quantization level TQL has a 5-bit absolute quantization level for each superblock. Therefore, 11 super blocks contain a quantization level of 55 bits.

By setting TQL = 31, it is possible to skip variable-length codes in superblock units.

Thus, it is possible to arrange the variable length code of the refresh block at an arbitrary position in the macro block.

As shown in FIG. 57, there is a correspondence between the trick quantization level TQL and the variable length code of each super block. TQL ₀ is a super block 0 TQL ₁ is a super block 1: TQL ₁₀ is a super block 10 2 shows the trick quantization level TQL of the first embodiment.

At the time of high-speed reproduction, super blocks 0 to 1
Of the 0s, the variable length code of the refresh block is arranged only at the super block position where the refresh block is arranged, and the trick block quantization level TQL = 31 is set for the other super block parts, and skipping in super block units is performed. Do.

Note that the variable-length code of the bit stream of recording or normal reproduction and of the broadcast wave bit stream is
Are in refresh block 0, super blocks 1-1
0 corresponds to the non-refresh blocks 1 to 10.

[0443] High-speed reproduction mode (TRK): When transmitting a bit stream of a broadcast wave or transmitting a bit stream at the time of normal reproduction, set TRK = 0 and set a 2-bit correction quantization level (PQL = 0) or A 2-bit correction quantization level is not used (PQL = 1).

In the high-speed reproduction mode of the VCR, TR
K is set to 1 and passes through a path indicating the above-described trick quantization level.

Block ID: ID indicating the distinction between a macroblock (non-) refresh block.

Block address: Indicates the address which is the absolute position of the macro (non-) refresh block on the screen.

Fill Bits code: When the generated code amount of the variable length code is small, a predetermined code is forcibly inserted. The code to be forcibly inserted is called Fill Bits. In particular, VCR
During high-speed reproduction, since only refresh blocks are used and non-refresh blocks are not used, the amount of generated codes is likely to decrease. Since the transmission code amount is constant, Fill Bits to be forcibly inserted are required.

Fill Bits code amount: By inserting the code length of the above Fill Bits before Fill Bits, Fill Bis
The end point of the sign of ts can be clarified. Thereby, the boundary with the macroblock can be clarified.

[0449] By using the above bit stream as a bit stream of a broadcast wave, a decoder that receives the broadcast wave can receive a signal that has been specially reproduced by a VCR.

By using the above-mentioned bit stream, the VCR format converter can realize special reproduction by a simple process of only detecting overhead data of a macroblock and replacing the code of a refresh block. 31. Another Embodiment 2 of Macro Bit Stream Structure In FIG. 57, a case where the refresh block code length and the non-refresh block code length are combined and only the macro block code length is inserted will be described below.

FIG. 58 shows a bit stream in this case. In this case, a variable length code decoding circuit is used to separate the refresh blocks during recording. This circuit is similar to the variable length code decoding circuit 84 in FIG.

By performing variable-length decoding, refresh blocks can be separated. This separation is performed, and the refresh block is recorded at a predetermined position on the tape.

The bit stream forming method during normal reproduction and high-speed reproduction is the same as the method described in Chapter 30.

The present invention is not limited to the above embodiment, but can be implemented with various modifications without departing from the spirit and scope of the present invention.

[0455]

As described in detail above, according to the present invention,
It is possible to provide an extremely good band compression signal processing device that can easily obtain a good reproduced image at the time of high-speed reproduction.

[Brief description of the drawings]

FIG. 1 is a block diagram showing an embodiment of a band compression signal processing apparatus according to the present invention.

FIG. 2 is a diagram showing a pixel configuration of the embodiment.

FIG. 3 is an exemplary view for explaining a super block address according to the embodiment;

FIG. 4 is an exemplary view for explaining refresh of the embodiment.

FIG. 5 is an exemplary view for explaining refresh of the embodiment;

FIG. 6 is a block diagram showing an intra-frame / inter-frame determination circuit according to the embodiment;

FIG. 7 is a view showing characteristics at the time of intra-frame / inter-frame determination in the embodiment.

FIG. 8 is an exemplary view for explaining forced refresh in the embodiment.

FIG. 9 is an exemplary view for explaining forced refresh per processor in the embodiment.

FIG. 10 is a diagram showing a scanning order when zigzag scanning DCT coefficients.

FIG. 11 is a diagram showing an example of a quantization table.

FIG. 12 is a diagram showing an example of a weighting table.

FIG. 13 is a diagram showing an example in which the weighting table is converted into the number of bits.

FIG. 14 is a diagram showing the number of bits generated by a quantization table.

FIG. 15 is a diagram showing the number of bits generated by a quantization table.

FIG. 16 is a timing chart shown for explaining the operation of the embodiment.

FIG. 17 is a view showing a relationship between refresh blocks and non-refresh blocks of frame numbers F ₅ and F _{6 in} the embodiment.

FIG. 18 is a view showing a track pattern in the embodiment.

FIG. 19 is a diagram showing a head trace locus at the time of 2 × speed reproduction in the embodiment.

FIG. 20 is an exemplary view showing reproducible refresh blocks of frames 1 to 8 in the embodiment.

FIG. 21 is a diagram showing refreshable refresh blocks of frames 9 to 11 and refresh blocks in which 11 frames are accumulated in the embodiment.

FIG. 22 shows frame numbers F _n and F _{n + 1} in the embodiment.
FIG. 4 is a diagram showing a relationship between a refresh block and a non-refresh block.

FIG. 23 is a diagram showing a head trace locus at the time of 2 × speed reproduction in the embodiment.

FIG. 24 is a diagram showing a configuration of a rate buffer.

FIG. 25 is a diagram showing the operation of the rate buffer on the encoder side.

FIG. 26 is a diagram showing the operation of the rate buffer on the decoder side.

FIG. 27 is a diagram showing an occupancy of a buffer and an increase / decrease of a quantization level.

FIG. 28 is a block diagram showing details of a quantization level setting circuit of the embodiment.

FIG. 29 is a diagram showing a generated code amount when performing variable length coding.

FIG. 30 is a diagram showing a relationship between DCT coefficient energy and a corrected quantization level.

FIG. 31 is a diagram illustrating an operation of controlling the code amount of a refresh block.

FIG. 32 is a diagram illustrating an example of quantization levels of a macro block and a refresh block.

FIG. 33 is a diagram showing a macro block and a (non-) refresh block.

FIG. 34 is a view for explaining a macroblock address;

FIG. 35 is a view for explaining a (non-) refresh block address;

FIG. 36 is a view for explaining a bit stream structure of a macroblock.

FIG. 37 is a view for explaining a bit stream structure of a refresh block;

FIG. 38 is a view for explaining a bit stream structure of a non-refresh block.

FIG. 39 shows a macro slice layer, a picture layer, O. P
The figure which shows the structure of a layer.

40 illustrates a refresh slice layer, a picture layer,
O. The figure which shows the structure of P layer No1.

41 illustrates a refresh slice layer, a picture layer,
O. The figure which shows the structure of P layer No2.

FIG. 42 shows a non-refresh slice layer, a picture layer,
G. FIG. O. The figure which shows the structure of a P layer.

FIG. 43 is a view showing the structure of a picture layer of a VCR.

FIG. 44 is a view showing the structure of VCR transmission data.

FIG. 45 is a view showing an example of the structure of transmission data of a VCR.

FIG. 46 is a block diagram showing details of a code transposition circuit.

FIG. 47 is a diagram showing (non-) refresh block memory write control timing.

FIG. 48 is a block diagram showing a memory read (non-) refresh slice coupling control circuit.

FIG. 49 is a view for explaining an envelope at the time of high-speed reproduction of a VCR.

FIG. 50 is a block diagram showing one embodiment of the decoder side of the present invention.

FIG. 51 is a diagram showing a relationship between an index, overhead data, and each circuit.

FIG. 52 is a block diagram showing details of a code re-interchange circuit.

FIG. 53 is a block diagram showing another example of the code reordering circuit.

FIG. 54 is a block diagram showing details of a frame delay circuit.

FIG. 55 is a view illustrating the operation of the frame delay circuit during normal reproduction.

FIG. 56 is a view illustrating the operation of the frame delay circuit during high-speed reproduction.

FIG. 57 is a view showing another example of a macroblock bit stream structure.

FIG. 58 is a view showing still another example of a macroblock bit stream structure.

FIG. 59 is a block diagram showing a conventional band compression system.

FIG. 60 is a view showing a format of a signal transmitted from the conventional system.

FIG. 61 is a view showing refresh blocks that can be reproduced from frames 1 to 8 during normal reproduction in the conventional system.

FIG. 62 is a diagram showing reproducible refresh blocks of frames 9 to 11 and refresh blocks in which 11 frames are accumulated during normal reproduction in the same conventional system.

FIG. 63 is a view showing a track pattern in the conventional system.

FIG. 64 is a diagram showing a head trace locus at the time of 2 × speed reproduction in the conventional system.

FIG. 65 is a diagram showing reproducible refresh blocks of frames 1 to 8 during double-speed reproduction in the conventional system.

FIG. 66 is a diagram showing reproducible refresh blocks of frames 9 to 11 and refresh blocks in which 11 frames are accumulated in double speed reproduction in the conventional system.

[Explanation of symbols]

11 input terminal, 12 subtraction circuit, 13 motion estimation circuit, 14 DCT circuit, 15 quantization circuit, 16 variable length coding circuit, 17 FIFO circuit, 18 output terminal,
19: inverse quantization circuit, 20: inverse DCT circuit, 21: addition circuit, 22: frame delay circuit, 23: motion compensation circuit,
24, 25: switch, 26: magnetic tape, 27-29
... Video input terminal, 30 ... Blocking circuit, 31 ... Intra / interframe decision circuit, 32,33 ... Input terminal, 34,35
... output terminal, 36 ... energy comparison circuit, 37 ... subtraction circuit, 38 ... addition circuit, 39 ... periodic refresh timing generation circuit, 40 ... synchronization signal detection circuit, 41 ... output terminal, 42 ... track formation signal generation circuit, 43 ... Rotary drum, 44 ... Track formation control circuit, 45 ... Sign change circuit, 46 ... Track, 47 ... Index insertion circuit,
48 ... index generation circuit, 49 ... multiplexer,
50: ECC circuit, 51: Unit sink insertion circuit, 5
2. Modulation circuit, 53: Quantization level setting circuit, 54: Super block code amount calculation circuit, 55: Macro block code amount calculation circuit, 56: Transmission code amount ROM, 57: Rate buffer code amount calculation circuit, 58: Macro Block quantization level setting circuit, 59: refresh block quantization level setting circuit, 60: non-refresh block quantization level setting circuit, 61, 62: input terminals, 63: DCT
Coefficient energy calculation circuit, 64 adder, 65 refresh block code amount calculation circuit, 66 switch, 67
... Overhead data generation circuit, 68, 69 ... Output terminal, 70 ... Memory read (non-) refresh slice combination control circuit, 71 ... Terminal, 72 ... Reproduction speed setting circuit, 73 ... Tape feed control circuit, 74 ... Track reproduction control Circuit, 75 switch, 76 error correction circuit, 77
... Unit sync detection circuit, 78 ... Index detection circuit, 79 ... Code length detection circuit, 80 ... Terminal, 81 ... Overhead data detection circuit, 82 ... Code reordering circuit,
83 terminal, 84 variable-length code decoding circuit, 85 reverse DC
T circuit, 86: inverse quantization circuit, 87: adder, 88: switch, 89: intra-frame / inter-frame switching circuit, 90: non-blocking circuit, 91: frame delay circuit, 92: motion compensation circuit, 93 to 95 ... output terminals, 96-98 ... terminals,
99 ... switch, 100-102 ... terminal, 103 ... envelope detection circuit.

──────────────────────────────────────────────────続 き Continuing on the front page (72) Inventor Michael Chinberg Carnegie Center Suite, Princeton 08450, New Jersey, USA 102 202 Advanced T-Vee Technology Center Toshiba America Consumer Products, Inc. (56) References JP-A-4-318783 (JP, A) JP-A-5-137110 (JP, A) (58) Fields investigated (Int. Cl. ⁷ , DB name) H04N 5/76-5 / 956 H04N 7/24-7/68 G11B 20/10-20/12

Claims (4)

(57) [Claims] 1. A method for forming one frame (where a is
Means for constructing an image area of (positive integer) and a video signal set by a continuous image,
The frame is calculated using the difference between the video signal and the video signal of the predicted image.
Interframe code composed by interframe coding
The video signal using the encoded signal and the information in the frame.
Intraframe code constructed by intraframe encoding
And f frames (where f is an integer of f ≧ 2)
Intra-frame encoding of the video signal at periodic intervals
Means for generating a refresh signal Te, the normal transmission period, scheduled transmission order, bandwidth compression et
The refresh signal of one image area from the encoder.
Signal, the inter-frame coded signal and the intra-frame code
Means for outputting and transmitting a coded signal, the refresh signal output after transmission,
The inter-system coded signal and the intra-frame coded signal are
Means for inputting to a compression decoder, means for obtaining a decoded image, and means for recording the decoded signal by a recording means.
C (c is an integer of a ≧ c ≧ 0) set for each frame
Each of the refresh signals in the
Address signal indicating the position of each of the c areas above
Means for adding a signal, the refresh signal of one image area, the frame
The inter-coded signal and the intra-coded signal are
Fast retransmission that allows transmission regardless of the transmission order
Be in special playback mode using the flag during raw processing
Means for instructing the refresh according to the address signal in a predetermined order.
The band compression decoder for displaying the flash signal.
Indicate the position on the frame with the fresh signal
Means for inputting the address signal, wherein the flag indicates the decoded signal on a recording medium.
When recording / reproducing, the decoded signal is transmitted.
Include fast playback mode and fast reverse playback mode
By the signal processing for indicating the special playback mode
A band compression signal processing device characterized by being generated . 2. The decoded signal on the recording medium.
When recording the number, the c
Add an address signal to the refresh signal
In each of the c image areas on the frame,
A refresh signal, the interframe coded signal and the
In the intra-frame coded signal, the c image regions
Means for adding overhead data, and recording the address signal and the overhead data
2. The belt according to claim 1, further comprising:
Range compression signal processing device. 3. The method according to claim 1, wherein one frame is generated at a period of said f frame.
Set for each frame from one image area to configure
B (b is an integer of a ≧ b ≧ 0) image areas
B-refle
Means for generating a refresh signal, and positions of b refresh signals set for each frame.
Means for adding and recording an address signal instructing the
2. The band compression signal processing according to claim 1, wherein
apparatus. 4. When recording the decoded image.
In addition, regardless of the transmission order, b refresh signals
The feature is that at least two of them are related and recorded.
The band compression signal processing device according to claim 3, wherein