JPH08237599A - Inter-frame band compression signal switching circuit - Google Patents

Abstract

PURPOSE: To attain a switched image of high quality by outputting only the valid signal for which an intra-frame coding processing is performed once without outputting the image by a difference signal when plural inter-frame band compression signals are switched. CONSTITUTION: When an inter-frame coding processing is executed, both of switches 24 and 25 are turned on. Therefore, the signal corresponding to the difference of an input video signal and the video signal before the one frame is obtained from a subtraction circuit 12. This difference signal is inputted in a DCT circuit 14, the signal is converted from a time base area to a frequency axis area and the signal is quantized in a quantization circuit 15. Because the difference signal and the video signal are added in an addition circuit 21 and are inputted in a frame delay circuit 22, the predictive video signal predicting the input video signal to be the base for preparing the difference signal is prepared and is inputted. By continuously outputting the valid block of the signal for which the intra-frame processing is performed once as a matter of practice the excellent image quality is obtained at the time of switching signals.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention is a band in which a video signal or the like is converted into a digital signal, and an intra-frame (including intra-picture) encoding process and an inter-frame (including inter-picture) encoding process are combined. The present invention relates to a device that performs compression, and relates to a device that synthesizes output signals of a plurality of band compression devices. Examples of the band compression signal synthesizer include a switcher or an editing device of a recording / reproducing device. The present invention also provides a device capable of switching or editing a wideband signal such as a high-definition TV (television) without deterioration of image quality.

[0002]

2. Description of the Related Art As is well known, when digitally transmitting a video signal, band compression is performed by combining a transmission method using a variable length coding method and a combination of intraframe coding processing and interframe coding processing. Transmission methods are being studied. Among them, a technique for performing band compression by combining intraframe coding processing and interframe coding processing and transmitting the data is described in, for example, the document IEEE Trans, on Broadcasting.
Vol, 36 No.4 DEC 1990 Woo Paik: “Digit
It is a band compression technology as shown in "al compatible HD-TV Broadcast system", and its characteristic part is explained below.

In FIG. 32, the video signal input to the input terminal 11 is supplied to the subtraction circuit 12 and the motion evaluation circuit 13, respectively. In the subtraction circuit 12, a subtraction process described later is performed, and its output is input to a DCT (discrete cosine transform) circuit 14. The DCT circuit 14 takes in 8 pixels in the horizontal direction and 8 images in the vertical direction as a unit block (8 × 8 pixels = 64 images), and outputs a coefficient obtained by converting the pixel array from the time domain to the frequency domain. Then, each coefficient is quantized by the quantization circuit 15. In this case, the quantization circuit 15 has 32 types of quantization tables, and each coefficient is quantized based on the selected quantization table. The quantizing circuit 15 is provided with a quantizing table so that the amount of information generated and the amount of information sent are within a certain range.

The coefficient data output from the quantization circuit 15 is zigzag-scanned from the low frequency band to the high frequency band for each unit block, and is extracted.
It is inputted to 6 and variable-length coded by combining the number of zero coefficients (run length) and the non-zero coefficient as one set. The encoder is a variable-length encoder having a different code length depending on the frequency of occurrence of Huffman code or the like. Then, the variable-length coded data is input to a FIFO (first-in-first-out) circuit 17 and read out at a prescribed speed, and then, via an output terminal 18, a multiplexer in the next stage (not shown). [Control signal, voice data, sync data (SYN
C), NMP and the like described later are multiplexed] and sent to the transmission path. Since the output of the variable length coding circuit 16 has a variable rate and the rate of the transmission path is a fixed rate, the FIFO circuit 17 serves as a buffer that absorbs the difference between the generated code amount and the transmitted code amount. .

The output of the quantization circuit 15 is input to the inverse quantization circuit 19 and inversely quantized. Further, the output of the inverse quantization circuit 19 is input to the inverse DCT circuit 20 and returned to the original signal. This signal is input to the frame delay circuit 22 via the adder circuit 21. The output of the frame delay circuit 22 is supplied to the motion compensation circuit 23 and the motion evaluation circuit 13, respectively. Motion evaluation circuit 13
Is the input signal from the input terminal 11 and the frame delay circuit 2
The output signal of 2 is compared to detect the overall motion of the image, and the phase position of the signal output from the motion compensation circuit 23 is controlled. In the case of a still image, the original image and the image one frame before are compensated so as to match each other. The output of the motion compensation circuit 23 can be supplied to the subtraction circuit 12 via the switch 24, and can also be fed back from the addition circuit 21 to the frame delay circuit 22 via the switch 25.

Next, the basic operation of the above system will be described. The basic operation of this system includes intraframe coding processing and interframe coding processing. The intraframe coding process is performed as follows. When this process is performed, both switches 24 and 25 are off. The video signal of the input terminal 11 is converted from the time domain to the frequency domain by the DCT circuit 14 and quantized by the quantization circuit 15. This quantized signal is subjected to variable length coding processing and then output to the transmission line via the FIFO circuit 17. The quantized signal is the inverse quantization circuit 1
9 and the inverse DCT circuit 20 restores the original signal, and the frame delay circuit 22 delays it. Therefore, in the intra-frame coding process, it is equivalent to that the information of the input video signal is variable length coded as it is. This intra-frame coding process is performed in a proper cycle in units of predetermined blocks and scene changes of the input video signal. This periodic intra-frame encoding process will be described later.

Next, the interframe coding process will be described. When the interframe coding process is executed, both switches 24 and 25 are turned on. Therefore, the subtraction circuit 12 obtains a signal corresponding to the difference between the input video signal and the video signal one frame before. This difference signal is
It is input to the DCT circuit 14, converted from the time domain to the frequency domain, and then quantized by the quantization circuit 15. In addition, since the differential signal and the video signal are added to the frame delay circuit 22 by the adder circuit 21 and input, a predicted video signal that predicts the input video signal from which the differential signal was created is created. Will be entered.

FIG. 33 shows a line signal in a state in which a video signal of a high-definition television signal is subjected to the intra-frame coding process and the inter-frame coding process as described above, and is sent out on the transmission path. ing. This signal is a signal of a transmission line, and includes a control signal, a voice signal, and a synchronization signal (S
YNC), system control signals, NMP, etc. are shown in a multiplexed state. FIG. 33A shows signals on the first line, and FIG. 33B shows signals on the second and subsequent lines. If this video signal has been subjected to intra-frame coding processing, a normal video signal can be obtained by inverse conversion.
However, in the case of a video signal that has been subjected to interframe coding processing, the difference signal is only reproduced even if this signal is inversely converted. Therefore, a normal video signal can be reproduced by adding the video signal (or the predicted video signal) reproduced one frame before to the difference signal.

According to the above system, all the information in the signal subjected to the intra-frame coding processing is variable length coded,
A signal that has been subjected to inter-frame coding processing in the next frame and thereafter will transmit difference information, which means that band compression is realized.

Next, the definition of the set of pixels processed by the band compression system will be described. That is, a block: an area of 64 pixels composed of 8 pixels in the horizontal direction and 8 pixels in the vertical direction.

Super block: 4 in the horizontal direction of the luminance signal
A block is an area composed of two blocks in the vertical direction. This area includes one block as the color signals U and V. The image motion vector obtained from the motion evaluation circuit 13 is included in units of super blocks.

Macroblock: 11 superblocks in the horizontal direction. In addition, when the code is transmitted, the DCT coefficient of the block is converted into a code determined by the number of consecutive zero coefficients and the amplitude of the non-zero coefficient, and these are transmitted as a set to transmit the code of the block. Finally, an end of block signal is added. Then, the motion vector of the motion correction performed in units of super blocks is
It is added and transmitted in macroblock units.

Regarding the transmission signal shown in FIG. 33,
Further explanations will be given on particularly relevant matters. First
The line synchronization (SYNC) signal indicates a frame synchronization signal in the decoder, and one timing synchronization signal is used for one frame to generate all timing signals of the decoder. The NMP signal on the first line indicates the number of video data from the end of this signal to the beginning of the macroblock of the next frame. This is because the code is configured by adaptively switching between the intra-frame coding process and the inter-frame coding process, so that the code amount of one frame differs for each frame, and the code position differs. This is because of Therefore, the position of the code corresponding to one frame is indicated by the NMP signal.

As a countermeasure when the user changes the channel, periodical intraframe coding processing is performed. That is, in this band compression system, as described above, 11 super blocks in the horizontal direction are called macro blocks, and 44 super blocks exist in the horizontal direction of one screen. That is, in one frame,
There are a total of 240 macroblocks, which is 4 macroblocks in the horizontal direction and 60 macroblocks in the vertical direction.

In this band compression system, FIG.
4 (a) to (h) and FIGS. 35 (a) to (c), refresh is performed in units of four macroblocks in each vertical column of superblocks, and all superframes are refreshed in 11 frame cycles. The block is refreshed. That is, as shown in FIG. 35 (d), the refreshed super block is accumulated for 11 frames, so that the intra-frame encoding process is performed in all the regions. Therefore, during normal reproduction of a VTR (video tape recorder) or the like, the above-described intra-frame encoding processing is performed at a cycle of 11 frames, so that a reproduced image can be viewed without any problem.

Head data is inserted at the beginning of the macroblock. This head data contains
The motion vector, field / frame determination, PCM / DPCM determination, quantization level, etc. of each super block are inserted together.

By the way, the band compression system described above is
It is used as an encoder for band compression of television signals, and the decoder is used on the receiving side.

Now, let us consider recording the above transmission signal in a VTR. A general VTR is a system in which a video signal of one field is converted into a fixed length code, a certain amount of information is generated, and recorded on X (X is a positive integer) tracks.

On the other hand, if the transmission signal obtained by the band compression system is used as it is for recording and reproduction on the VTR, the variable length code is used as it is for the intra-frame coding process and the inter-frame coding process. For,
The position where the code that has been subjected to the intraframe coding process is periodically recorded is not fixed, and a block that is not refreshed occurs during editing, switching of recording signals and reproduction signals, high-speed reproduction, and the like.

More specifically, FIG. 36 shows a track pattern when the variable-length coded signal as described above is helically recorded on the magnetic tape 26. In track patterns T ₁ through T _11, a portion indicated by a thick line indicates the switching position of the frame F ₁ to F _11. The switching positions of the frames F _{1 to} F ₁₁ are not aligned because the record data is created by the variable length code.

When the magnetic tape 26 is normally reproduced by a VTR, all the track patterns T _1- .
Since T ₁₁ is sequentially scanned by the magnetic head, a normal video signal can be reproduced without any problem by passing the reproduction output through the decoder. That is, at the time of normal reproduction, it is possible to reproduce all of the code that has been subjected to the intra-frame coding process and the code that has been subjected to the inter-frame coding process recorded on the magnetic tape 26, so that an image can be constructed using all the codes. Is.

However, in the VTR, there are cases where reproduction is performed from a limited number of tracks such as editing. In this case, there is no problem if the tracks of the signal subjected to the intra-frame coding process are reproduced one after another, but if reproduced from the tracks subjected to the inter-frame coding process, only the image by the difference signal is obtained.

[0023]

As described above, the conventional switcher and recording / reproducing apparatus having the band compression system have a problem that only an image based on a differential signal can be obtained at the time of signal switching or editing. There is. Further, in a switcher equipped with a conventional band compression system, when a signal is switched, a signal that has undergone intra-frame coding once becomes a valid signal, but there is a problem in that there is no means for extracting this. ing.

Therefore, the present invention has been made in view of the above circumstances, and provides an extremely good inter-frame band compression signal switching circuit which can easily obtain a good reproduced image at the time of signal switching or editing. With the goal.
Another object of the present invention is to provide a circuit capable of switching and editing a wideband signal such as that of a high-definition TV while maintaining high image quality. Furthermore, when switching the input signal of the decoder by inter-frame band compression with progressive refresh,
It is an object of the present invention to provide a circuit that can output an effective signal that has been subjected to intra-frame coding processing once and output an image quickly.

[0025]

An inter-frame band compression signal switching circuit according to the present invention converts two inter-frame band compression signals A and B having refresh processing for periodically performing intra-frame coding processing to signal A In the circuit for switching from the signal to the signal B, the continuous output of the effective block of the B signal, which has been subjected to the intraframe coding processing once, is generated.

Further, the inter-frame band compression signal switching circuit according to the present invention is a circuit for switching the two inter-frame band compression signals A and B having the progressive refresh processing from the signal A to the signal B once. Circuit for continuously outputting the effective block of the B signal subjected to the conversion process, the total code amount of the effective block in the refresh period at the time of switching the B signal, the rate buffer occupancy at the start of the normal B signal, and the A signal The rate buffer occupancy in each frame and the transmission rate of the A signal are used to determine the code amount at the time of switching, and signal switching is performed.

Furthermore, the inter-frame band compression signal switching circuit according to the present invention outputs two inter-frame band compression signals A and B having progressive refresh processing,
In the circuit for switching from the signal A to the signal B, a circuit for continuously outputting the effective block of the B signal once subjected to the intra-frame encoding processing, and the effective code amount ΔRB _j of each frame of the B signal at the time of refreshing Transmission rate r per frame, refresh period 1 at switching, periodic refresh period f, rate buffer occupancy RA _(nl) at switching of A signal, rate buffer occupancy PB _n at start of normal B signal As opposed to

(Equation 6) Is prescribed.

Further, the inter-frame band compression signal switching circuit according to the present invention is a circuit for switching the two inter-frame band compression signals A and B having progressive refresh processing from the signal A to the signal B once. Circuit for continuously outputting the effective block of the B signal subjected to the conversion processing, the effective code amount ΔRB _j of each frame of the B signal at the time of refreshing, the transmission rate r per frame, the refresh period 1 at the time of switching, With respect to the periodic refresh period f, the rate buffer occupancy RA _(nl) at the time of switching the A signal, and the rate buffer occupancy PB _n at the start of the normal B signal,

(Equation 7) When ΔR> 0,

(Equation 8) Is determined, and the extension code for the minimum frame is output.

Further, the inter-frame band compression signal switching circuit according to the present invention outputs two inter-frame band compression signals A and B having progressive refresh processing,
In the circuit for switching from the signal A to the signal B, a circuit for continuously outputting the effective block of the B signal once subjected to the intra-frame encoding processing, and the effective code amount ΔRB _j of each frame of the B signal at the time of refreshing Transmission rate r per frame, refresh period 1 at switching, periodic refresh period f, rate buffer occupancy RA _(nl) at switching of A signal, rate buffer occupancy PB _n at start of normal B signal As opposed to

[Equation 9] When ΔR <0,

[Equation 10] I is determined and the skip code for the minimum frame is output.

[0030]

According to the above construction, a good reproduced image can be easily obtained at the time of signal switching or editing, and switching or editing can be performed with a wide band signal of a high-definition TV or the like in high image quality. Further, it is possible to output only the effective signal which has been subjected to the intra-frame coding process once when switching the inter-frame band compression signal having the progressive refresh.

[0031]

An embodiment of the present invention will be described below in detail with reference to the drawings. The new configuration is shown by a double frame in the block diagram.

1. Basic Configuration of Band Compressor FIG. 1 is a diagram showing the basic configuration of the present invention. The luminance signal Y and the color signals U and V of a high definition TV or the like are input to the video input terminals 27, 28 and 29. After subjecting these signals to the necessary pre-processing, the blocking circuit 30 forms a block having a pixel configuration described later in Chapter 2, and the input terminal 11
To enter. The video signal input to the input terminal 11 is supplied to the subtraction circuit 12 and the motion evaluation circuit 13, respectively. The subtraction circuit 12 performs a subtraction process described later, and the output thereof is input to the DCT circuit 14.

The DCT circuit 14 takes in 8 pixels in the horizontal direction and 8 pixels in the vertical direction as a unit block (8 × 8 pixels = 64 pixels), and outputs a coefficient obtained by converting the pixel array from the time domain to the frequency domain. Then, each coefficient is quantized by the quantization circuit 15. In this case, the quantization circuit 15
Has 10 or 32 types of quantization tables, and each coefficient is quantized based on the selected quantization table. The quantizing circuit 15 is provided with a quantizing table so that the amount of information generated and the amount of information sent are within a certain range.

The coefficient data output from the quantizing circuit 15 is zigzag-scanned from the low frequency band to the high frequency band for each unit block and taken out, and then the variable length coding circuit 1
It is inputted to 6 and variable-length coded by combining the number of zero coefficients (run length) and the non-zero coefficient as one set. The encoder is a variable-length encoder having a different code length depending on the frequency of occurrence of Huffman code or the like.

The variable-length coded data is input to the FIFO circuit 17 and read out at a prescribed speed, and then, via the output terminal 18, the multiplexer 31 of the next stage [control signal, voice data, synchronous data (SYNC), N described later
MP, etc.] is supplied to the transmission line from the output terminal 32. Since the output of the variable length coding circuit 16 has a variable rate and the rate of the transmission path is a fixed rate, the FIFO circuit 17 serves as a buffer that absorbs the difference between the generated code amount and the transmitted code amount. .

The output of the quantization circuit 15 is input to the inverse quantization circuit 19 and inversely quantized. Further, the output of the inverse quantization circuit 19 is input to the inverse DCT circuit 20 and returned to the original signal. This signal is input to the frame delay circuit 22 via the adder circuit 21. The output of the frame delay circuit 22 is supplied to the motion compensation circuit 23 and the motion evaluation circuit 13, respectively.

The motion evaluation circuit 13 compares the input signal from the input terminal 11 with the output signal of the frame delay circuit 22, detects the overall motion of the image, and the motion compensation circuit 23.
Controls the phase position of the signal output from. In the case of a still image, the original image and the image one frame before are compensated so as to match each other. The output of the motion compensation circuit 23 is the switch 24.
It is also possible to feed the signal to the subtraction circuit 12 via the switch and feed it back to the frame delay circuit 22 from the adder circuit 21 via the switch 25.

Next, the basic operation of the above system will be described.

2. The signal input to the pixel configuration input terminal 11 forms a block, a super block, and a macro block by collecting a plurality of effective pixels in one screen. In addition, this configuration is a Digicipher
The example is based on MPEG, DSC-HDTV: Zenith + AT
It goes without saying that the block configuration used in the T method or the like may be used.

The definition of the block configuration will be described with reference to FIG.

Block: A 64 pixel area composed of 8 horizontal pixels and 8 vertical pixels [FIG.
See (d)].

Super block: 4 in the horizontal direction of the luminance signal
A block is an area composed of two blocks in the vertical direction. This area includes one block as the color signals U and V. Further, the image motion vector obtained from the motion evaluation circuit 13 can be set in units of super blocks [see FIG. 2 (c)].

Macroblock: 11 superblocks in the horizontal direction. In addition, when the code is transmitted, the DCT coefficient of the block is converted into a code determined by the number of consecutive zero coefficients and the amplitude of the non-zero coefficient, and these are transmitted as a set to transmit the code of the block. Finally, an end of block signal is added. Then, the motion vector of the motion correction performed in units of super blocks is
It is added as overhead data in units of macroblocks and transmitted [see FIG. 2 (b)].

That is, in this band compression system, as described above, the 11 super blocks in the horizontal direction are called macro blocks, and 44 in the horizontal direction of one screen.
Super block exists. That is, in one frame, there are a total of 240 macroblocks of 4 macroblocks in the horizontal direction and 60 macroblocks in the vertical direction.

Then, in this band compression system, FIG.
As shown in (a) to (h) and FIGS. 4 (a) to (c),
Refreshing is performed in units of four macroblocks in each vertical column of superblocks, and all superblocks are refreshed in a cycle of 11 frames.
That is, as shown in FIG. 4D, the refreshed super block is accumulated for 11 frames, so that the intra-frame coding process is performed in all the regions.

One screen: 1050 scanning lines, which are interlaced. The effective pixel is horizontal 14
It is composed of 08 pixels and 960 pixels in the vertical direction. Video signals for one screen are processed by four processors [Fig. 2
(See (a)].

FIG. 5 shows the relationship between one screen and a super block address (hereinafter referred to as SBA = Super Block Address). There are 44 super blocks in the horizontal direction and 60 super blocks in the vertical direction. Therefore, there are 2640 super blocks in one screen. The address S. B. Assign A. If the horizontal superblock address is x and the vertical superblock address is y, S.S. B. A = 60
There is a relationship of x + y.

3. Intra-frame / inter-frame coding First, the basic operations of this system are intra-frame coding processing and inter-frame coding processing. The intraframe coding process is performed as follows. When this process is performed, both switches 24 and 25 are off.
The video signal of the input terminal 11 is converted from the time domain to the frequency domain by the DCT circuit 14 and quantized by the quantization circuit 15. This quantized signal is subjected to variable length coding processing and then output to the transmission line via the FIFO circuit 17.

The quantized signal is returned to the original signal by the inverse quantization circuit 19 and the inverse DCT circuit 20, and delayed by the frame delay circuit 22. Therefore, in the intra-frame coding process, it is equivalent to that the information of the input video signal is variable length coded as it is. This intra-frame coding process is performed in a proper cycle in units of predetermined blocks and scene changes of the input video signal. The periodic intra-frame encoding process will be described later.

Next, the interframe coding process will be described. When the interframe coding process is executed, both switches 24 and 25 are turned on. Therefore, the subtraction circuit 12 obtains a signal corresponding to the difference between the input video signal and the video signal one frame before. This difference signal is
It is input to the DCT circuit 14, converted from the time domain to the frequency domain, and then quantized by the quantization circuit 15.

Further, since the differential signal and the video signal are added to the frame delay circuit 22 by the adder circuit 21 and input, the predicted video signal that predicts the input video signal from which the differential signal is created is generated. It will be created and entered. Generally, the generated code amount of an image subjected to intra-frame coding processing is larger than the generated code amount of an image subjected to inter-frame coding processing.

4. Intra-frame / inter-frame switching process 4.1 Image adaptive intra-frame coding process Switching between the intra-frame coding process and the inter-frame coding process is controlled by the intra-frame / inter-frame determination circuit 33. There are two types of this control method. First, according to the content of the input video signal, the first method performs interframe coding processing on a signal having a correlation between frames and intraframe coding processing on a signal having no correlation between frames. This is the method of applying. When a scene change or the like occurs, the intraframe coding process is performed. In-frame / inter-frame determination circuit 3
In 3, the prediction error energy between the current frame signal from the input terminal 11 and the prediction signal output from the motion compensation circuit 23 is compared with the current signal energy.

In FIG. 6, input terminals 11, 34, 35
And the output terminals 36 and 37 are the input terminals 11 and 3 of FIG.
4, 35 and output terminals 36, 37 are the same. The current signal is input to the input terminal 11. This current signal is input to the energy comparison circuit 38 and the subtraction circuit 39. The prediction signal output from the motion compensation circuit 23 is input to the input terminal 35, and the subtraction circuit 39 obtains a prediction error which is the difference between the current signal and the prediction signal. The current signal is calculated by the current signal energy calculation circuit 38a, the prediction error is calculated by the prediction error energy calculation circuit 38b, and both energies are compared. Examples of energy calculation formulas for the current signal and the prediction error are as follows.

[0054]

[Equation 11] FIG. 7 shows the inside / of the frame in the energy comparison circuit 38.
An example of the method for determining the interval is shown. In the figure, the horizontal axis represents the energy of the current signal and the vertical axis represents the energy of the prediction error. Further, a solid line drawn diagonally from the origin 0 indicates a case where the energy of the prediction error and the energy of the current signal are equal. In the area below this solid line, the energy of the prediction error is smaller, so interframe coding processing is performed. Further, in the area above the solid line, the energy of the current signal is smaller, so that intraframe coding processing is performed. In this way, the energy comparison circuit 38 outputs the intra-frame / inter-frame discrimination signal adapted to the input signal, and outputs it from the output terminal 36 via the addition circuit 40.

4.2 Forced Intra-frame Encoding Processing (Refresh) The second method is a method of forcibly performing the intra-frame encoding processing regardless of the correlation of the video signals. In this case, the intraframe coding process is periodically performed on a predetermined area of the screen. There are two purposes for performing this compulsory intra-frame coding process. It is necessary for the user to be able to recognize the image within a certain time when the channel is changed. This is so that special reproduction can be realized in a recording medium such as a VTR or a disc.

This forcible intraframe coding process is called refresh. Further, the time required for refreshing a predetermined area is named refresh time. As shown in FIG. 6, the periodic refresh timing generation circuit 41 inputs a sync signal from the input terminal 34 and generates an intra-frame selection signal at a predetermined cycle in synchronization with the sync signal. This signal and the intra-frame / inter-frame discrimination signal of the energy comparison circuit 38 are added by the adder circuit 40, and the intra-frame / inter-frame switching signal is output from the terminal 36.

5. Refresh Refresh of each of the following methods will be described in detail.

5.1 DigiCipher Refresh In the DigiCipher, as described above, 11 super blocks in the horizontal direction are called macro blocks, and 44 super blocks exist in the horizontal direction of one screen. That is, in one frame, there are a total of 240 macroblocks of 4 macroblocks in the horizontal direction and 60 macroblocks in the vertical direction. Then, in the band compression system described in the present invention, as shown in FIGS. 3A to 3H and FIGS. Refresh is performed, and all the super blocks are refreshed every 11 frames.

That is, as shown in FIG. 4 (d), the refreshed super block is accumulated for 11 frames, so that the intra-frame coding process is performed in all the regions. The merit of this refresh is that the refresh is performed evenly for each frame, so that the capacity of the FIFO circuit 17 serving as a rate buffer may be small.

This DigiCipher refresh is shown in FIG. 8 using the super block address shown in FIG. In the figure, the vertical axis represents the super block address, the horizontal axis represents the frame number, and the part surrounded by a square r represents the part subjected to the intra-frame coding process. In the figure, only the refresh block is shown. In the figure, refresh is applied to all the super blocks on one screen in 11 frames of frame numbers F _{0 to} F ₁₀ . Since the same processing is performed by the four processors, the refresh operation of one processor shown in FIG. 8 will be used to explain DigiCipher refresh with reference to FIG.

That is, S. B. Address = 0 to 659
Will be described. In FIG. 9A, the portion r subjected to the refreshing and the image adaptive intra-frame coding processing is shown surrounded by a square. For example, in F ₀ the scene
Assuming that a change has occurred, S. B. Intra-frame coding processing is performed on all the areas of addresses 0 to 659. Further, in F ₁₄ , S. B. Address 0-59
Intra-frame coding processing has been performed in the area.

FIG. 9B shows the DigiCipher refresh time. A part of the area is refreshed per frame, and the refresh is completed in the 11-frame period, so that 11 frames become the refresh time. In addition, this refresh completes the refresh of one screen no matter what 11-frame period. That is, 1 of F _{0 to} F ₁₀
Refresh is completed in one frame period or 11 frame periods of F _{1 to} F ₁₁ .

As shown in FIG. 9C, the minimum acquisition time is one frame period and is obtained when a scene change occurs and initialization is started.
Further, the maximum acquisition time in FIG. 9D is a case where the image adaptive intra-frame coding process does not occur at all, and is 11 frame periods. When the signal switching and the editing of the recording / reproducing apparatus are realized by using the refresh block as a starting point, at each refresh block address, as shown in FIG.
The frame period becomes the refresh interval.

5.2 MPEG (Moving Picture Image)
Refresh of Coding Experts Group) First, refresh used in MPEG will be described with reference to FIG. In MPEG, refresh is performed in frame units. The frame that has been refreshed is called an I picture. The cycle of the I picture, that is, the refresh cycle is set in frame units, and 12, 15, ... Frames are selected.
This situation will be described with reference to FIG. Note that only the case where the scanning line is 1050 will be described for simplification of description, but it goes without saying that other block configurations may be used.

In FIG. 10A, the vertical axis represents the super block address. This super block address corresponds to the super block address defined in FIG. The horizontal axis represents the frame number. Further, the blackened portions indicate the portions that have been subjected to the intraframe coding process. Here, frame numbers 0, 12, 24, 36, ... Show the periodically inserted intra-frame coded images, and frame numbers 13, 15,
The black-colored portions shown in 17, 19, 21, 23 indicate the portions to which the image adaptive intra-frame coding processing has been performed.

In this example, the refresh time is as shown in FIG.
It is 12 frames as shown in (b). In order to obtain an image on one screen when the user initializes by changing the channel, the intra-frame coding process must be performed on the entire area of one screen. Therefore, this time is defined as follows.

Acquisition time: Time required for intra-frame coding processing to be performed on all areas of one screen.

This acquisition time also depends on the timing at which the user changes the channel. Figure 10
(C) shows the minimum acquisition time. The minimum acquisition time is when the start of initialization and refresh or scene change occur at the same time,
One screen image can be obtained in one frame period. Figure 10
The maximum acquisition time is shown in (d). The maximum acquisition time is when the initialization starts immediately after the refresh is completed. In this case, 1
One screen image can be obtained in two frame periods.

Consider a case where signal switching and editing of the recording / reproducing apparatus are to be realized with a refresh block, which is a periodical intra-frame encoding process, as a starting point. 1
Since it is based on the refresh of 2 frame cycles,
The refresh interval is 12 frames as shown in FIG.

10. Code amount control There are two types of code amount control methods. The first method is a method of controlling the quantization level as described above. In this case, the amount of code generated in the refresh block is suppressed, so that the image quality of the refresh block itself deteriorates. However, in the next frame, the difference between the intra-frame coded signal of the refresh block and the video signal of the next frame is sent, so the image quality is only momentarily degraded. This method will be described in detail later.

The second method is to divide the code, which has been quantized once, into two, and calculate the code amount of the MSB or low frequency component by VTR.
It is a method that keeps the code amount that can be read out at the time of high-speed reproduction on a recording medium such as. Regarding this, 11. More on this in the chapter.

The control of the amount of coded information when the first method is used will be described below.

10.1 Macroblock Code Amount Control When the video signal is high-efficiency coded using variable length coding as in the present embodiment, the generated information amount is generally not constant. This is because the amount of information contained in the video signal varies with time. On the other hand, when a fixed rate transmission system is used, encoding control is required to keep the amount of encoded information constant.

A general method of fixed rate conversion is to prepare a buffer memory at the output of the encoder, input the variable rate to this buffer memory, and output at a fixed rate to smooth the encoded information amount. Is. Since the amount of data in the buffer memory changes according to the amount of input information, there is a possibility that overflow or underflow will occur. In order to prevent this, when overflow or underflow is likely, the encoding parameter is changed so as to reduce or increase the encoded information amount, respectively. For example, the quantization characteristic may be made coarser or finer.

The larger the capacity of the buffer memory is, the higher the smoothing effect is, but the coding delay and the cost are limited. In addition, a relatively small buffer memory may allow finer control of encoding according to the local characteristics of the image, and thus a buffer memory of about 1 frame may be used.

The control of the macroblock code amount will be specifically described.

The capacity of the rate buffer is used for controlling the code amount of the macroblock. In the method using the rate buffer, as shown in FIG. 11, the encoder and the decoder are provided with equal-rate rate buffers.

The input / output code amount of these buffers and the buffer occupancy will be described with reference to FIG. Reference numeral a in FIG. 11 indicates an input signal of the rate buffer b of the encoder. This signal is the output signal of the variable length coding circuit 16 of the encoder. The characteristic of this signal is that each block is input at a constant cycle, but the generated code of each block is a variable length code, so that it has a variable length rate. The output signal c of the rate buffer of the encoder is transmission data, and the code is output at a fixed rate. Further, the input signal d of the rate buffer e of the decoder is a code input of a fixed rate, and the output signal f is a code output of a variable rate.

The characteristics on the encoder side and the decoder side will be described in detail with reference to FIGS. 12 and 13. The horizontal axes in FIGS. 12A to 12C and FIGS. 13A to 13C indicate frame numbers. Here, FIG.
13 (a) to 13 (c) and FIGS. 13 (a) and 13 (b) are the same as the input frame numbers, the frame numbers in FIG. 13 (c) are shifted by 8 frames. This is necessary in order to absorb the variation in the delay time of the transmission code of the encoder and the decoder due to the use of the variable length code.

12A to 12C and 13A to 13C.
The vertical axis of (c) shows the code amount. In this example, the capacity of the rate buffer is 4 Mbits, and the transmission code amount per frame is 0.5 Mbits / frame. 12A to 12C show encoder side,
13A to 13C show the characteristics on the decoder side.

FIG. 12A shows the generated code amount per frame. The broken line in the figure is shown with reference to the capacity of the rate buffer. Since the variable length code is used, the generated code amount of each frame differs depending on the frame. In F _{1 to} F ₉ in which the frame number is represented by F _n , examples of code generation when the buffer overflows and underflows are shown. At F ₁ , a 4.5 Mbit code is generated,
F ₂ ~F occur until ₉ code is set to 0.

The maximum value of the generated code amount of each frame is determined by the sum of the buffer capacity and the transmitted code amount. In this example, the buffer capacity is 4 Mbits, and the transmitted code amount per frame is 0.5 [M [Bits / frame], the maximum possible code amount per frame is 4.5 Mbits. F _{20 to} F ₃₀ are examples in which the generated code amount of each frame is controlled by the occupancy of the buffer.

FIG. 12B shows the occupancy of the encoder buffer. In this example, the buffer capacity is 4M
The capacity of the buffer is indicated by a broken line. F
_{Since a} large amount of generated code is generated in ₁ frame, F
_At the time of ₁ , a buffer overflow has occurred. F
_{Since the} code is not generated at all from _{2 to} F ₉ , the buffer underflow occurs at the time of F ₉ .

FIG. 12C shows the transmission code amount from the encoder. A solid straight line A drawn diagonally in the figure shows the cumulative transmission code amount. This inclination indicates the amount of transmitted code per frame. In this example, 0.5M bits are transmitted per frame time. Frame rate is 30
In the case of [Hz], 30 × 0.5 [M / Frame] = 15
The transmission code amount is [Mbps]. Also, the maximum value determined by the maximum capacity of the broken line buffer is shown.

The polygonal line shown in FIG. 12 (c) is
The cumulative generated code amount is shown. That is, FIG. 12 (a)
Is the integrated value of the generated code amount per one frame.
When the accumulated generated code amount contacts the broken line, the buffer overflows, and when it contacts the solid line, the buffer underflows. The dotted line drawn horizontally between the cumulative generated code amount and the cumulative transmitted code amount indicates the delay time in the encoder buffer when transmitting the generated code, and the longer one indicates the longer time until transmission. This shows that.

In FIG. 13 (a), the solid line B shows the cumulative received code amount. This solid line B is shown in FIG.
Is the same as the real straight line A. The polygonal line indicates the video code amount of each frame when the image is output. This is
This corresponds to a value obtained by integrating the projection code amount per frame in (c). Further, the dotted line drawn horizontally represents the delay time when the received code is displayed, and the sum of the delay time in the encoder and the delay time in the decoder is all equal, and the buffer delay shown in FIG. Time (Buffer D
elay).

FIG. 13B shows the occupation rate of the buffer of the decoder. Here, FIG. 12B and FIG.
Compare with (b). Figure 1 shows only the buffer delay time.
When shifting 2 (b), FIG. 12 (b) and FIG. 13 (b)
And are in a vertically inverted relationship. That is,
An encoder overflow results in a decoder underflow, and an encoder underflow results in a decoder overflow.

FIG. 13C shows the projected code amount per frame of the projected code. FIG. 12A and FIG.
3 (c) is delayed by the buffer delay time of the encoder and the decoder. When the subscriber changes the channel, it is possible to output the video after accumulating the code of the required code amount in the buffer of the decoder. This accumulated amount is equal to the value that accumulates the received code amount for the time shown by the dotted line in FIG. This value has a corresponding relationship with the NMP signal of the conventional example (vbv delay in MPEG). That is, the decoder may store the code in the buffer for the time determined by the NMP signal and then output the video.

As shown in F ₁ of FIG. 12A, when the maximum code amount occurs in the first frame, the maximum buffer delay time occurs in the decoder buffer. In this case, it is possible to output a normal video signal after accumulating the received code in the buffer for the time indicated as buffer delay in FIG. In this case, a normal video signal is output after the buffer of the decoder is filled with the reception code.

That is, the received codes are accumulated from F _{0 to} F ₈ and a normal video signal is output after the initialization state filling the buffer memory is completed. When the projection code is output at F ₁ in FIG. 13C, the buffer of the decoder is underflowed. Moreover, FIG.
When the state in which the projection code is not output from F _{1 to} F _{9 in} (c) continues, the buffer of the decoder overflows at F ₉ . This corresponds to the state in which the buffer state of the encoder is delayed by 8 frames and the overflow and underflow are inverted. When the subscriber changes the channel, in order to output a normal video signal, it is necessary for the buffer of the decoder to store the code for the time according to the NMP signal. It is possible to produce an incomplete image as shown by the dotted line.

FIG. 14 shows an example of the relationship between the buffer occupancy rate and the increase / decrease in the quantization level set for each macroblock. The quantization level is not changed while the occupancy of the buffer is at a predetermined value, and the quantization level is increased or decreased when the buffer occupancy exceeds the predetermined value. In FIG. 14, the quantization level is not changed when the buffer occupation rate is 45% to 55%, and is changed when the buffer occupation rate exceeds 45%. This makes it possible to control the rate of the buffer.

The quantization level is roughly quantized when the value of j is large and the generated code amount is small. Therefore, when the buffer occupation rate is small, the quantization level is lowered.
When the buffer occupancy is large, the quantization level is increased.

FIG. 15 shows a configuration for realizing the above operation. In order to determine the macroblock quantization level, the quantization level setting circuit 42 and the super block code amount calculating circuit 43 are used. Here, a method of calculating the code amount of the super block will be described in detail with reference to FIG. That is, the output of the quantization circuit 15 is input to the variable length coding circuit 16. In this circuit, first, the zigzag scan circuit 16a reads the DCT coefficient of the 8 × 8 pixel block, combines the continuous number of zero coefficients and the amplitude of the nonzero coefficient, and inputs them to the Huffman coding circuit 16b.

The number of consecutive zero coefficients and the amplitude of non-zero coefficients are input to the super block code amount calculating circuit 43. This super block code amount calculation circuit 43 is shown in FIG.
The generated code amount is calculated using a ROM (read only memory) (not shown) that stores the table shown in FIG. 16 is also used in the conventional example,
The horizontal axis shows the amplitude of the non-zero coefficient, and the vertical axis shows the number of consecutive zero coefficients. The numbers in the frame indicate the number of bits of the code. The number of bits of this code is added to calculate the generated code amount in units of super blocks.

Further, in order to determine the quantization level of the macroblock, the macroblock code amount calculation circuit 44
Then, the code amounts of the 11 super blocks are added to calculate the code amount of the macro block. Further, the transmission code amount stored in the transmission code amount ROM 45 is subtracted from this value, and the rate buffer occupancy rate is calculated by the rate buffer code amount calculation circuit 46. This rate buffer occupancy rate and FIG.
The macroblock quantization level setting circuit 47 sets the quantization level for each macroblock on the basis of the graph.

10.2 Super block code amount control The code amount control per super block can be controlled only in the direction in which the quantization level is made coarser than the quantization level determined by the macro block. This is because, for example, if there is a superblock that has undergone intraframe coding processing, the amount of code that has undergone intraframe coding processing is greater than the amount of code that has undergone interframe coding processing. This is because the code amount may be significantly increased.

On the other hand, the human visual characteristic is that when the contents of the image change, for example, when a scene change occurs or when a part hidden behind a moving object appears (this is called a covered back). Does not allow the eyes to react quickly and precisely and requires a certain amount of time. Therefore, it is difficult to determine the deterioration of the image quality in the intra-frame coding processing part caused by the change in the content of the image even if the quantization level is roughened. That is, the code amount can be reduced in the portion where the image adaptive intra-frame encoding processing has occurred.

A configuration for realizing this operation will be described with reference to FIG. Super block quantization level setting circuit 48
The image adaptive intra-frame / interval determination signal output from the energy comparison circuit 38 in the intra-frame / interval determining circuit 33 is input to the connection terminal 49. Further, the output signal of the DCT circuit 14 is input from the connection terminal 50 to the DCT coefficient energy calculation circuit 51 to calculate the DCT coefficient energy,
This energy determines the correction level of the quantization level. This value is input to the quantization circuit 15 through the addition circuit 52 that adds the macro block quantization level. The relationship between this energy and the correction level has the relationship shown in FIG.

Furthermore, even in a super block subjected to interframe coding processing, if the energy is extremely large, it means that there are many high frequency components,
Also in this case, since it is difficult to determine the deterioration of the image quality, the quantization level may be coarse. In this case, the correction level is set as shown in FIG.

25. Decoder Basic Configuration The basic configuration of the decoder will be described in detail with reference to FIG.
FIG. 19 shows a circuit using overhead data.
In FIG. 19, the circuit name is shown on the horizontal axis and the data name is shown on the vertical axis, and the circuit marked with a circle is the circuit used. The normal bit stream in which signals are not switched and the broadcast wave bit stream have the same macroblock configuration.

In the case of a broadcast wave bit stream, the overhead data detection circuit 53 is used to detect the overhead data and decode it. Since the normal operation is the same as the operation of decoding a broadcast wave, this operation will be described first. The variable-length code of the bitstream of the macroblock shown in FIG. 20 supplied to the input terminal 54 is input to the variable-length code decoding circuit 57 via the rate buffer (FIFO) circuit 55 and the connection terminal 56.

When the variable length code is extracted, the variable length code of each block is extracted from the bit stream by detecting the end of block (EOB). The variable length code decoding circuit 57 sequentially detects the Huffman code by comparing the Huffman table and the code from the head position of the variable length code. Using the detected Huffman code, the number of consecutive zero coefficients (run length) and the non-zero coefficient (amplitude) of the quantized DCT coefficient are obtained. Since the coefficients are arranged in the order in which the zigzag scan is performed, the order of the coefficients can be rearranged according to the need of the inverse DCT circuit 60 described later.

The signal obtained by decoding the variable length code is connected to the connection terminal 5
It is input to the inverse quantization circuit 59 via 8. The inverse quantization circuit 59 performs inverse quantization based on the quantization level in the bitstream. Next, each of the 64 coefficients per block is first multiplied by a weighting value according to a weighting table. Next, each of the 64 coefficients is multiplied by a quantization scale value according to the quantization level in units of superblocks to perform inverse quantization and obtain DCT coefficients.

The inverse DCT circuit 6 outputs the 64 DCT coefficients.
The coefficient in the frequency domain is converted to the time domain by passing 0 to obtain a signal of 64 pixels of 8 pixels in the horizontal direction and 8 pixels in the vertical direction. The output of the inverse DCT circuit 60 is added to the adder circuit 61.
To enter. In addition, the signal from the switch 62 is input to the adder circuit 61 and added to the output signal of the inverse DCT circuit 60. The switch 62 is an intra-frame / inter-frame switching circuit 6
Controlled by 3. The output signal of the adder circuit 61 is the switch 6
Then, the signal is input to the deblocking circuit 65 and then to the frame delay circuit 67 via the connection terminal 66.

The frame delay circuit 67 is composed of a frame memory, and the output signal of this frame memory is input to the motion compensation circuit 68 and the deblocking circuit 65.
The output signal of the motion compensation circuit 68 is input to the switch 62. The deblocking circuit 65 includes a frame delay circuit 67 that is supplied from the output of the adder circuit 61 and the switch 69.
Output of the luminance signal Y and the color difference signals U and V are output from the output terminals 70 to 72, respectively.

The operation of the decoder includes intraframe decoding processing and interframe decoding processing. In the switch 62, when the switch 62 is off, the intraframe decoding process is performed, and when the switch 62 is on, the interframe decoding process is performed. The on / off control of the switch 62 is performed by the intra-frame / inter-frame switching circuit 63.

The PCM / DPCM discrimination signal in the overhead data obtained from the overhead data detection circuit 53 is input to the intra-frame / inter-frame switching circuit 63 through the connection terminal 73. Here, PCM is in the frame, D
PCM indicates interframe decoding processing. PCM
The switch 62 is turned off by and the switch 62 is turned on by DPCM. As described in Chapter 3, the intraframe / interframe decoding process is the image adaptive intraframe decoding process.
There is a refresh (forced intraframe decoding process).

First, the operation of the intraframe decoding process will be described. During the intraframe decoding process, the inverse DCT circuit 60
Is input to the frame delay circuit 67 and the deblocking circuit 65, and the luminance signal Y and the color difference signals U and V are output.

Next, the operation of the interframe decoding process will be described. In this case, the prediction signal of one frame before stored in the frame delay circuit 67 is read out, and the motion compensation circuit 6 is read.
Enter in 8. Also, the motion vector of the overhead data is input to the motion compensation circuit 68 from the connection terminal 73, and the position of the prediction signal on the screen is shifted. A motion compensation circuit 68 outputs a prediction signal corresponding to the position on the screen of the output signal of the inverse DCT circuit 60, and inputs it to the addition circuit 61 through the switch 62. In addition circuit 61, the inverse D
The output of the CT circuit 60 and the prediction signal are added and input to the frame delay circuit 67 and the deblocking circuit 65. Then, the luminance signal Y and the color difference signals U and V are separated and output from the output terminals 70 to 72.

The writing process to the variable length code decoding circuit 57, the inverse quantization circuit 59, the inverse DCT circuit 60, and the frame delay circuit 67 in the broadcast wave and the normal time described above is always performed based on the macro block. . That is,
The processing of these circuits per processor is based on the sequential processing of 11 super blocks in the macro block, and the macro blocks are sequentially processed from the top to the bottom of the screen.

28. Frame Delay Circuit The frame delay circuit 67 has a write address generation circuit 67a as shown in FIG. Here, DigiCiph
The operation of the frame delay circuit 67 will be described by taking the case of er as an example. However, the basic items are the same in other systems (MPEG, etc.). In the case of DigiCipher, since it is processed by 4 processors and there are 4 macroblocks in the horizontal direction, one macroblock is processed in the horizontal direction for each processor. Therefore, per processor, macro blocks are processed from the top to the bottom in units of 11 super blocks in the macro block.

The circuit for performing processing by these four processors is a variable length code decoding circuit 57, an inverse quantization circuit 59, an inverse D.
The CT circuit 60, the adder circuit 61, the motion compensation circuit 68, the intra-frame / inter-frame switching circuit 63 and the switch 62, and the write address generation circuit 67 a in the frame delay circuit 67. Codes are distributed to the four processors by using the processor ID (PID) included in the macroblock overhead data. This 4
Since the operations of the processors are the same, the operation of one processor will be described. The operation of one processor is the same when the number of processors is small in other methods.

Since the bit stream in the normal state is the bit stream of the macro blocks shown in FIGS. 20 and 22, the macro block address at the head of the macro picture layer, that is, the macro slice layer is used.
By setting the projection start position, and then using the processor ID,
Addresses for normal reproduction are sequentially generated.

FIG. 23 is a diagram showing the operation of the write address generating circuit 67a during normal reproduction. First, the head macro block address of the macro slice layer is detected by the overhead data detection circuit 53 and input to the write address generation circuit 67a from the connection terminal 73. FIG. 23
An example of the case of the processor 1 is shown in FIG. First, the M.D. B. Read A = 0. This M. B. A =
0 indicates the projection position of the super block at the head of the macro block of the processor 0.

Since the projection position of the super block at the head of the macro block of the processor PID is expressed by the following equation, when the processor PID = 1, the head super block address of the macro block is 66 as shown in the following equation.
It becomes 0.

S. B. A = M. B. A + 660 × PID = 0 + 660 × 1 = 660 During normal reproduction, first, as indicated by an arrow in FIG. B. A = 6
Up to 60, 720, ..., 1260, 11 super blocks are processed, and one macro block is processed in the vertical direction.
That is, S. B. After A = 1260, S. B. A =
, 1261 are processed.

Next, the read address generation circuit 67b.
Reads the luminance signal Y and the color signals U and V according to the scanning line order of the TV. The frame delay circuit 67 and the write / read address generation circuits 67a and 67b also function as the deblocking circuit 65.

Chapter 29 Skip When a coded superblock is exactly the same as a predicted superblock, it is said that no data of this coded superblock layer is sent and this is skipped. The bit stream structure at this time is set to the trick quantization level TQL _n = 31 (n is a super block number) as described in the macro block bit stream structure of FIG. 20, and the corresponding variable length code is skipped. Go to the next super block. That is, no valid data is generated in the corresponding super block. Where TQL =
31 will be called a skip code. As another method of constructing a bit stream for expressing skip, EOB (End of Block) may be inserted at the position of the variable length code of the corresponding super block.

29.1 Circuit Operation During Skip The circuit operation during skip will be described with reference to FIGS. 18 and 21. The overhead data detection circuit 53 detects the skip code in the bitstream structure (FIG. 20) and inputs the skip signal to the skip control circuit 74 from the connection terminal 73. The skip control circuit 74 generates a skip control signal necessary for the frame delay circuit 67, the deblocking circuit 65, the switch 64, and the switch 69, and the connection terminal 75.
Is output via.

The switch 64 and the switch 69 shown in FIG.
Shows the operation concept at the time of skip. At the time of skip, since there is no valid data in the bit stream, the output signal of the adder circuit 61 is not used. That is, the switch 64 is in the open state, and writing to the frame delay circuit 67 is not performed. Further, at the time of skip, since it is the same as the image data of the predicted super block, the image data stored in the frame delay circuit 67 is read to output the video signal from the output terminals 70 to 70.
Output to 72. That is, the switch 69 is in the on state.

At the time of non-skip, similar to the operations explained in Chapter 25 Decoder Basic Configuration and Chapter 28 Frame Delay Circuit,
Performs a write operation to the frame delay circuit.

29.2 Operation Example During Skipping A specific example of the operation of the frame delay circuit 67 during skipping will be described with reference to FIGS. 24 and 25. In the bit stream (FIG. 20), the variable length code of the refresh block exists in super block 0, and the super block 1
-An example will be described in which the variable length code does not exist in the super block 10.

The trick quantization level TQL ₀ represents the variable length code of the refresh block, and the trick quantization levels TQL _{1 to} TQL ₁₀ represent skip 3.
It is 1.

The operation of the write address generating circuit 67a at the time of skip will be described with reference to FIG. A write address generation circuit 67a in the frame delay circuit 67 of the decoder
First confirms that all the trick quantization levels TQL _{1 to} TQL ₁₀ are in the skip state in the macroblock bitstream of FIG. As a result, as shown in FIG. 25, the super block 1 in the macro block is
~ Super block 10 confirms that it is a skip. Skip means frame memories 67c, 67d,
Since writing to 67e is not performed, no address is generated in the skip portion. That is, as a result, the address is generated only in the portion where the refresh block exists, so that the address is generated in the vertical direction. FIG. 24 shows the case of DigiCipher.

In the case of the DigiCipher, as shown in FIG. 3A, the refresh block is arranged in the vertical direction, not necessarily for one processor. The super block address is generated in the direction. That is, S. B. Super block addresses are generated in the order of A: 600, 601, ..., 658, 659.

Next, the read address generation circuit 67b.
Reads the luminance signal Y and the color signals U and V according to the scanning line order of the TV. The frame delay circuit 67 and the write / read address generation circuits 67a and 67b also function as the deblocking circuit 65. When the above frame memory writing and reading are performed, the read address is set in the scanning line order in the horizontal direction, and in the writing, it is written in the vertical direction.

35. Partial area refresh signal switching basic operation As described with reference to Chapter 5 and FIGS. 3 and 4, when a partial area of one screen is refreshed in one frame period (for example, DigiCipher) The inter-frame band compression signal switching circuit will be described. FIG. 26 is a diagram showing an output signal obtained by switching between two inter-frame band compression signals in which a partial area of one screen is refreshed. This figure is similar to FIG. 9 described in Chapter 5, Section 5.1.

FIG. 26 (a) shows the inter-frame band compression signal A, and the portion surrounded by a square and having a r in it indicates a block in which the A signal is refreshed. Figure 2
6 (b) shows the inter-frame band compression signal B,
The portion surrounded by a square and having R written therein indicates a block in which the B signal is refreshed. The point of switching between these two signals is that when switching from the A signal to the B signal, the block in which the B signal is refreshed is output as an effective signal.

That is, as shown in FIG.
_When there is a user switching request 310 at ₁₀ , first, as the FB ₁₀ signal, only signals of super block addresses 600 to 659 obtained by refreshing the B signal are sent.
That is, as shown in FIG. 25, within one macroblock, only the refresh block is sent and the remaining superblocks output the skip signal. In the next frame FB ₁₁ , super block addresses 540 to 659
Is output.

That is, signals of super block addresses 540 to 599 refreshed by FB ₁₁ and F
The signals of the super block addresses 600 to 659 refreshed in B ₁₀ are output. That is, FIG.
As shown in, when viewed in macroblock units, the refresh block and the superblock refreshed in the previous frame are transmitted, and the remaining superblocks are left in the skipped state. Here, regarding the skip, the operation described in Chapter 29 Skip is performed.

Refresh valid blocks at switching corresponding to the super block addresses 540 to 599 and 600 to 659 of the FB ₁₁ described here are defined.

Refresh effective block at the time of switching: A block in which a new signal after switching is refreshed once. The variable length code data of the super block to be skipped is not used in producing a projected image. The variable length code of this invalid superblock can be deleted, and it is preferable to delete it for efficiency.

36. Bitstream at the time of switching partial region refresh band compressed signal As described in Chapter 35, it is preferable to delete the variable length code of the invalid block. In this method, the variable length code of unnecessary super block is deleted in the inter-frame band compression signal switching circuit, and in the overhead data,
This is a method of inserting a code indicating a skip of TQL = 31.

This is the switch switching control circuit 7 in the inter-frame band compression signal switching circuit (FIG. 27) described later.
6, when reading from the A and B memories 79 and 80 using the A and B write / read control circuits 77 and 78, only the refresh valid block at the time of switching is read. Here, the refresh valid block at switching refers to a block that has been refreshed once after switching, and is the same as the block defined in the description of FIGS. 24 and 25 in Chapters 35 and 36.

37. Partial area refresh inter-frame compression signal switching circuit FIG. 27 shows a circuit configuration of a partial area refresh inter-frame compression signal switching circuit. As mentioned in Chapter 35, variable length codes of invalid superblocks that have not been refreshed in the previous frame are preferably deleted. Therefore, the partial region refresh inter-frame band compression signal switching circuit requires the A and B variable length code detection circuits 81 and 82. Therefore, the configuration shown in FIG. 28 is obtained. In FIG. 28, blocks having the same function are assigned the same numbers. Note that, here, the A and B write / read control circuits 77 and 78, the switch switching control circuit 76, and the switching overhead data generation circuit 83.
The operation of is shown in FIG.

Operation of Partial Area Refresh Signal Switching Circuit The partial area refresh signal switching circuit of FIG. 27 operates in the steps shown in FIG. FIG. 28 is a diagram illustrating in detail the inside of each block of FIG. 27. In the figure, blocks to which the same number is assigned are blocks having the same function. The inside of the B refresh effective area detection circuit 84 includes a B super block delimiter detection circuit 84a, a B overhead data detection circuit 84b, and a B variable length code detection circuit 82. In addition, inside the switch switching control circuit 76, a super block delimiter position storage circuit 76a and a switching generated code amount calculation circuit 76 are provided.
It consists of b.

Further, the inside of the B write / read control circuit 78 includes all super block write control circuits 78a,
The refresh effective read control circuit 78b is used. Inside the switching overhead data generation circuit 83, a trick quantization level setting circuit 83a, a switching Macroblock code length setting circuit 83b, a rate buffer occupancy setting circuit 83c, a decoder projection frame setting circuit 8
3d, a rate buffer capacity setting circuit 83e, and a transmission rate setting circuit 83f. The inside of the B memory 80 is a memory M- ₁₀ to store the code of each macroblock.
It is composed of a macroblock memory 80a composed of M ₀ and a multiplexer 80b.

The macroblock memory 80a temporarily stores all codes of each macroblock during storage. At the time of reading, the super block that has been refreshed once is set as an effective block, and at the time of switching, only the effective block is read. Further, the multiplexer 80b
Then, the codes of the effective blocks are combined and output.

Step 1 As described with reference to FIG. 26, when switching from the A signal to the B signal, the refresh block of the signal B is switched as the start block. Therefore, the A and B refresh effective area detection circuits 85 and 84 and the A and B variable length code detection circuits 81 and 82 detect refresh blocks,
As described in Chapters 35 to 37, the superblock that has been refreshed once is set as the effective block. Furthermore, variable length codes of invalid blocks other than valid blocks are deleted. In addition, the switching period l [see FIG.
Corresponding to B'switching mode of 0 (c)] is determined.

Step 2 When the effective block is determined, the generated code amount RBT (Rate B channel) of the effective block at the time of switching represented by the following equation
Transition Value) is calculated.

[0141]

(Equation 12) Here, n is a frame in which output of all data of the frame of the signal B is started, and (n−f) is a frame in which switching from the A signal to the B signal is started. In FIG. 26, since the refresh is started from FB _{10 of} the B signal, (n
-F) = 10. Further, f indicates a refresh period. In the example of DigiCipher refresh in Chapter 5, Section 5.1, since 11 frames are in the refresh period, f = 11. Further, ΔRB _j indicates the generated code amount of the effective block of one frame of the frame FB _j of the B signal. Therefore, RBT represents the total generated code amount of valid blocks in the refresh period. In step 2, the buffer occupancy RA _(nl) , ..., R of the signal A is further added.
A _(nl-imax) and the buffer occupancy RB _n of the signal B are detected.

Step 3 The output timing of the start frame at the time of switching and the switching start point are determined from the total code amount of the effective blocks in the refresh period at the time of switching, and the output end determines the end frame of the A signal. Therefore, the frame FB that starts outputting all the data of the frame of the signal B
total code amount of the effective blocks in the rate buffer occupancy RB _n and the refresh period during the switching of the _n

(Equation 13) And the transmission code amount r per refresh period at the time of switching
Rate buffer occupancy RA when switching between l and signal A
_{by (nl)}

[Equation 14] To calculate.

Here, the operation of the inter-frame band compression signal switching circuit of FIG. 27 differs from the case of ΔR> 0, ΔR = 0, and ΔR <0. When ΔR> 0, the following operation is performed.

Step 4.1 In this case, the initial value of the effective block buffer occupancy

(Equation 15) Since RA _(nl) is smaller, the sending timing of FB _(nf) is later than the sending timing of FA _(nl) . Then, the extended frame amount k is generated such that the transmission timing of the end frame of the A signal is after the transmission timing of the start frame of the B signal. It satisfies the following formula.

[0145]

[Equation 16] Step 5.1 Next, the switch switching operation of the switch switching control circuit 76 will be described with reference to FIG. The solid line 270 is shown in FIG.
Output terminal 86 of the inter-frame band compression signal switching circuit of
Corresponding to the signal. Since the transmission rates of the input and output signals are the same, they are linear. The solid line 270 shows the switching timing of the signal A and the signal B. FA
The timing of the A signal ending the output at ₁₃ is the intersection point 402 of the dotted line drawn from the point 401 in the horizontal direction and the solid line 270.
Then, the timing of starting the output of the start frame FB ₉ at the time of switching is the intersection 404 of the dotted line horizontally drawn from the point 403 and the solid line 270, and the transmission end timing of FB ₉ is later than the transmission timing of FA ₁₃ . Therefore, the end frame FA _{(n-l + k)} of the A signal described above is

[Equation 17] It becomes FA ₁₉ that satisfies the requirement. FA ₁₉ is an intersection 405 of the extension of the accumulated code amount 272 of the A signal and a dotted line drawn horizontally from the points 403 and 404. Since the transmission timing is the point 404, the A signal is transmitted up to the point 404. Is output. The output timing of the FB ₂₀ at which the normal B signal is started is the dotted line drawn from the point 406 in the horizontal direction and the solid line 27.
It becomes the intersection 407 with 0. During the period from point 404 to point 407, the generated code amount of the effective block at the time of switching the B signal is output.

FIG. 30B shows the state of the rate buffer circuit 55 inside the decoder when the signal shown in FIG. 30A is input to the inter-frame band compression decoder shown in FIG. A is up to the point 404 on the solid line 270 in FIG.
Since only the signal is input, the point 41 on the solid line 410
Up to 1, only the A signal is present. Solid line 270, point 4
From 04 to point 407, since the generated code amount of the effective block at the time of switching is input, point 4 is stored in the rate buffer.
After twelve, the B signal exists, the A signal disappears at the point 413, and only the B signal exists.

FIG. 30C shows the output signal of the decoder. Only the A signal is output up to frame number F ₁₃ , the switching signal is output from F ₁₄ to F _19, and only the F ₂₀ to B signal is output. When outputting a skip code and ΔR <0, the following operation is performed.

Step 4.2 In this case, the initial value of the effective block buffer occupancy

(Equation 18) Since RA _(nl) is larger, the end frame of the A signal must be set before RA _(nl) . Signal A
The buffer occupancy RA _(nl), ..., with RA _{(nl-ima x),} generating a skip code by the skip frame quantity i which satisfies the formula shown below.

[0149]

[Formula 19] Step 5.2 The switch switching operation of the switch switching control circuit 76 is shown in FIG.
This will be described using 1 (a). The timing of ending the output of the A signal in FA ₁₃ is the intersection 422 of the dotted line drawn from the point 421 in the horizontal direction and the solid line 270, and the timing of starting the output of the start frame FB ₉ at the time of switching is horizontal from the point 423. An intersection point 424 between the dotted line drawn with the line and the solid line 270 is obtained, and the sending timing of FB ₉ is earlier than the sending timing of FA ₁₃ . Therefore, the end frame F of the A signal described above
A _(nli) is

(Equation 20) FA ₁₂ that satisfies the above conditions. FA ₁₂ points 423 and 424
Is a frame of an intersection 425 between a dotted line drawn horizontally from the above and the accumulated code amount 272 of the A signal. The output timing of the FB ₂₀ at which the normal B signal is started is a dotted line horizontally drawn from the point 426, a solid line 270, and an intersection 427. Point 424
During the period from to point 427, the generated code amount of the effective block when the B signal is switched is output.

FIG. 31 (b) shows the state of the rate buffer circuit 55 when the signal of FIG. 31 (a) is input to the decoder. A solid line 430 shows the occupancy of the rate buffer. Since only the A signal is input up to the point 423 on the solid line 270, only the A signal exists up to the point 431 in FIG. 31B, and the B signal exists in the rate buffer after the point 423. The A signal disappears and only the B signal exists.

FIG. 31 (c) shows the output signal of the decoder 221, which is the A signal up to frame number F ₁₃ , F ₁₄ is an image holding F ₁₃ , a switching signal from F ₁₄ to F ₁₉ , and F _20. Output only the B signal. When ΔR = 0 Step 5.3 When ΔR = 0, the A signal is transmitted as the frame number FA _(nl-1)
After outputting up to FB, only the effective block of B signal is FB
_(n-1) , and outputs all B signals from FB _n .

[0152]

As described above, according to the present invention, when switching a plurality of inter-frame band compression signals,
It is possible to obtain a high-quality switching image by outputting only the effective signal that has been subjected to the intra-frame coding processing once without outputting the image based on the differential signal.

[Brief description of drawings]

FIG. 1 is a block diagram showing an embodiment of an inter-frame band compression signal switching circuit according to the present invention.

FIG. 2 is a diagram shown for explaining a pixel region in the embodiment.

FIG. 3 is a diagram shown for explaining refreshing of the embodiment.

FIG. 4 is a diagram shown for explaining refreshing of the embodiment.

FIG. 5 is a diagram shown for explaining a super block address in the embodiment.

FIG. 6 is a block configuration diagram showing details of an intra-frame / inter-frame determination circuit in the embodiment.

FIG. 7 is a diagram for explaining intra-frame / inter-frame determination characteristics according to the embodiment.

FIG. 8 is a diagram shown for explaining forced refresh in the embodiment.

FIG. 9 is a diagram for explaining forced refresh per processor in the embodiment.

FIG. 10 is a diagram for explaining MPEG refresh in the embodiment.

FIG. 11 is a diagram showing a configuration of a rate buffer.

FIG. 12 is a diagram showing the operation of a rate buffer on the encoder side.

FIG. 13 is a diagram showing the operation of the rate buffer on the decoder side.

FIG. 14 is a diagram showing increase / decrease in buffer occupancy and quantization level.

FIG. 15 is a block configuration diagram showing details of a quantization level setting circuit of the same embodiment.

FIG. 16 is a diagram showing a generated code amount when variable length coding is performed.

FIG. 17 is a diagram showing the relationship between DCT coefficient energy and corrected quantization level.

FIG. 18 is a block diagram showing an embodiment of the decoder side of the present invention.

FIG. 19 is a diagram showing a relationship between an index, overhead data, and each circuit.

FIG. 20 is a diagram shown for explaining a bitstream structure of a macroblock.

FIG. 21 is a block diagram showing details of a frame delay circuit.

[Fig. 22] A macro slice layer, a picture layer, G. O. P
The figure which shows the structure of a layer.

FIG. 23 is a diagram shown for explaining the normal operation of the frame delay circuit.

FIG. 24 is a diagram for explaining the operation of the frame delay circuit when skipping.

FIG. 25 is a diagram showing a display operation of the switching operation of the inter-frame band compression signal switching circuit.

FIG. 26 is a diagram showing a switching operation of an inter-frame band compression signal switching circuit.

FIG. 27 is a diagram showing a block configuration of an inter-frame band compression signal switching circuit.

FIG. 28 is a diagram showing a detailed block configuration of an inter-frame band compression signal switching circuit.

FIG. 29 is a flowchart shown to explain the switching operation of the inter-frame band compression signal switching circuit.

FIG. 30 is a diagram showing the operation of the rate buffer of the inter-frame band compression signal switching circuit.

FIG. 31 is a diagram showing an operation of a rate buffer of another embodiment of the inter-frame band compression signal switching circuit.

FIG. 32 is a block diagram showing a conventional band compression system.

FIG. 33 is a diagram showing a format of a signal transmitted from the conventional system.

FIG. 34 is a diagram showing refreshable refresh blocks of frames 1 to 8 during normal reproduction in the conventional system.

FIG. 35 is a diagram showing refreshable blocks that can be played back from frames 9 to 11 and refresh blocks that have accumulated 11 frames during normal playback in the conventional system.

FIG. 36 is a diagram showing a track pattern in the conventional system.

[Explanation of symbols]

11 ... Input terminal, 12 ... Subtraction circuit, 13 ... Motion evaluation circuit, 14 ... DCT circuit, 15 ... Quantization circuit, 16 ... Variable length coding circuit, 17 ... FIFO circuit, 18 ... Output terminal,
19 ... Inverse quantization circuit, 20 ... Inverse DCT circuit, 21 ... Addition circuit, 22 ... Frame delay circuit, 23 ... Motion compensation circuit,
24, 25 ... Switch, 26 ... Magnetic tape, 27-29
... Video input terminal, 30 ... Blocking circuit, 31 ... Multiplexer, 32 ... Output terminal, 33 ... In-frame / interval determining circuit, 34, 35 ... Input terminal, 36, 37 ... Output terminal,
38 ... Energy comparison circuit, 39 ... Subtraction circuit, 40 ... Addition circuit, 41 ... Periodic refresh timing generation circuit, 42 ... Quantization level setting circuit, 43 ... Super block code amount calculation circuit, 44 ... Macro block code amount calculation circuit , 45 ... Transmission code amount ROM, 46 ... Rate buffer code amount calculation circuit, 47 ... Macro block quantization level setting circuit, 48 ... Super block quantization level setting circuit, 49, 50 ... Connection terminal, 51 ... DCT coefficient energy calculation Circuits, 52 ... Addition circuit, 53 ... Overhead data detection circuit, 54 ... Input terminal, 55 ... Rate buffer circuit, 56 ... Connection terminal, 57 ... Variable length code decoding circuit, 5
8 ... Connection terminal, 59 ... Inverse amount only circuit, 60 ... Inverse DCT circuit, 61 ... Addition circuit, 62 ... Switch, 63 ... In-frame / between switching circuit, 64 ... Switch, 65 ... Deblocking circuit, 66 ... Connection Terminal, 67 ... frame delay circuit,
68 ... Motion compensation circuit, 69 ... Switch, 70-72 ... Output terminal, 73 ... Connection terminal, 74 ... Skip control circuit, 7
5 ... Connection terminal, 76 ... Switch switching control circuit, 77 ... A
Write / read control circuit, 78 ... B Write / read control circuit, 79 ... A memory, 80 ... B memory, 81 ... A
Variable-length code detection circuit, 82 ... B variable-length code detection circuit, 8
3 ... Overhead data generation circuit at switching, 84 ...
B refresh effective area detection circuit, 85 ... A refresh effective area detection circuit, 86 ... Output terminal.

Continuation of front page (51) Int.Cl. ⁶ Identification number Office reference number FI Technical display location H04N 9/808 H04N 9/80 B 11/04

Claims (5)

[Claims] 1. An intraframe coding process is performed once in a circuit for switching two interframe band compression signals A and B having a refresh process for periodically performing the intraframe coding process from a signal A to a signal B. An inter-frame band compression signal switching circuit which continuously outputs an effective block of a B signal. 2. In a circuit for switching two inter-frame band compression signals A and B having progressive refresh processing from signal A to signal B, an effective block of B signal which has undergone intra-frame coding processing is made continuous. Output circuit, total code amount of effective block in refresh period when switching B signal, rate buffer occupancy at the start of normal B signal, rate buffer occupancy in each frame of A signal, transmission of A signal 2. The inter-frame band compression signal switching circuit according to claim 1, wherein the rate is used to determine the code amount at the time of switching and switching is performed. 3. A circuit for switching two inter-frame band compression signals A and B having progressive refresh processing from signal A to signal B, in which an effective block of B signal which has been subjected to intra-frame coding processing is made continuous. Output circuit, effective code amount ΔRB _j per frame of B signal at the time of refresh, transmission rate r per frame, refresh period 1 at switching, periodic refresh period f, and switching of A signal at switching For the rate buffer occupancy RA _(nl) and the rate buffer occupancy PB _n at the start of the normal B signal, The inter-frame band compression signal switching circuit according to claim 1, wherein 4. In a circuit for switching two inter-frame band compression signals A and B having progressive refresh processing from signal A to signal B, an effective block of B signal which has been once subjected to intra-frame coding processing is made continuous. Output circuit, the effective code amount ΔRB _j per frame of the B signal at the time of refreshing, the transmission rate r per frame, the refresh period 1 at the time of switching, the periodic refresh period f, and the A signal at the time of switching the A signal. For the rate buffer occupancy RA _(nl) and the rate buffer occupancy PB _n at the start of the normal B signal, Is defined, and when ΔR> 0, 4. The inter-frame band compression signal switching circuit according to claim 3, wherein k is determined so that the extension code for the minimum frame is output. 5. In a circuit for switching two inter-frame band compression signals A and B having progressive refresh processing from signal A to signal B, an effective block of B signal which has been once subjected to intra-frame coding processing is made continuous. Output circuit, the effective code amount ΔRB _j per frame of the B signal at the time of refreshing, the transmission rate r per frame, the refresh period 1 at the time of switching, the periodic refresh period f, and the A signal at the time of switching the A signal. With respect to the rate buffer occupancy RA _(nl) and the rate buffer occupancy PB _n at the start of the normal B signal, Is defined, and when ΔR <0, 4. The inter-frame band compression signal switching circuit according to claim 3, wherein i is determined so that the skip code for the minimum frame is output.