JPH0767113A - Inter-frame band compressing signal switching circuit - Google Patents

Abstract

PURPOSE:To easily obtain a satisfactory regenerative image in the case of signal switching or editing by generating a switching output while matching the phases of cyclical synchronizing signals at two band compressing signals at the circuit for switching the two band compressing signals provided with cyclical synchronizing signals inserted to the inter-frame band compressing signals independently of the border of a code for each frame. CONSTITUTION:Data, to which inter-frame encoding processing and variable length encoding is performed, are inputted to a rate buffer 17, read out at specified speed and supplied later through an output terminal 18 to a multiplexer 10 on the next stage, and a control signal, voice data and cycle data or the like are multiplexed. Afterwards, the data are sent from the output terminal 8 to a transmission line. In this case, the rate buffer 17 plays the role of a buffer for absorbing difference between each generated code amount and a sent code amount. Therefore, since the cyclical synchronizing signals can be easily synchronized when switching the two inter-frame band compressing signals, at the time of switching, no image distortion is generated.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention is a band in which a video signal or the like is converted into a digital signal, and an intraframe (including picture) encoding process and an interframe (including picture) encoding process are combined. The present invention relates to a device that performs compression, and relates to a device that synthesizes output signals of a plurality of band compression devices. Examples of the band compression signal synthesizing device include a switcher or an editing device of a recording / reproducing device. The present invention also provides an apparatus capable of switching or editing a wideband signal such as a high-definition TV (television) without deterioration in image quality.

[0002]

2. Description of the Related Art As is well known, when digitally transmitting a video signal, a transmission method using a variable length coding method or a band compression is performed by combining an intraframe coding process and an interframe coding process. Methods to do so are being studied. Among them, a technique of performing band compression by combining intraframe coding processing and interframe coding processing and transmitting the data is disclosed in, for example, the document IEEE Trans.on Broadcasting Vo.
Woo Paik: “Digital described in l.36 No.4 DEC 1990
It is a band compression technology as shown in "compatible HD-TV Broadcast system", and its characteristic part is explained below.

In FIG. 41, the video signal input to the input terminal 11 is supplied to the subtraction circuit 12 and the motion evaluation circuit 13, respectively. The subtraction circuit 12 performs a subtraction process, which will be described later, and the output thereof is input to a DCT (discrete cosine transform) circuit 14. The DCT circuit 14 takes in 8 pixels in the horizontal direction and 8 images in the vertical direction as a unit block (8 × 8 pixels = 64 images), and outputs a coefficient obtained by converting the pixel array from the time axis domain to the frequency domain. Then, each coefficient is quantized by the quantization circuit 15. In this case, the quantization circuit 15 has 32 types of quantization tables, and each coefficient is quantized based on the selected quantization table. The quantizing circuit 15 is provided with a quantizing table so that the amount of information generated and the amount of information sent are within a certain range.

The coefficient data output from the quantization circuit 15 is zigzag-scanned from the low frequency band to the high frequency band for each unit block, and is extracted.
It is inputted to 6 and variable-length coded by combining the number of zero coefficients (run length) and the non-zero coefficient as one set. The encoder is a variable-length encoder having a different code length depending on the frequency of occurrence of Huffman code or the like. Then, the variable-length coded data is input to a FIFO (first-in-first-out) circuit 17 and read out at a prescribed speed, and then, via an output terminal 18, a multiplexer in the next stage (not shown). [Control signal, voice data, sync data (SYN
C), NMP and the like described later are multiplexed] and sent to the transmission path. Since the output of the variable length coding circuit 16 has a variable rate and the rate of the transmission path is a fixed rate, the FIFO circuit 17 serves as a buffer that absorbs the difference between the generated code amount and the transmitted code amount. .

The output of the quantization circuit 15 is input to the inverse quantization circuit 19 and inversely quantized. Further, the output of the inverse quantization circuit 19 is input to the inverse DCT circuit 20 and returned to the original signal. This signal is input to the frame delay circuit 22 via the adder circuit 21. The output of the frame delay circuit 22 is supplied to the motion compensation circuit 23 and the motion evaluation circuit 13, respectively. Motion evaluation circuit 13
Is the input signal from the input terminal 11 and the frame delay circuit 2
The output signal of 2 is compared to detect the overall motion of the image, and the phase position of the signal output from the motion compensation circuit 23 is controlled. In the case of a still image, the original image and the image one frame before are compensated so as to match each other. The output of the motion compensation circuit 23 can be supplied to the subtraction circuit 12 via the switch 24, and can also be fed back from the addition circuit 21 to the frame delay circuit 22 via the switch 25.

Next, the basic operation of the above system will be described. The basic operation of this system includes intraframe coding processing and interframe coding processing. The intraframe coding process is performed as follows. When this process is performed, both switches 24 and 25 are off. The video signal of the input terminal 11 is converted from the time domain to the frequency domain by the DCT circuit 14 and quantized by the quantization circuit 15. This quantized signal is subjected to variable length coding processing and then output to the transmission line via the FIFO circuit 17. The quantized signal is the inverse quantization circuit 19
The signal is returned to the original signal by the inverse DCT circuit 20, and delayed by the frame delay circuit 22. Therefore, in the intra-frame coding process, it is equivalent to that the information of the input video signal is variable length coded as it is. This intra-frame processing is performed in a proper cycle in units of predetermined blocks and scene changes of the input video signal. The periodic in-frame processing will be described later.

Next, the interframe coding process will be described. When the interframe coding process is executed, both switches 24 and 25 are turned on. Therefore, the subtraction circuit 12 obtains a signal corresponding to the difference between the input video signal and the video signal one frame before. This difference signal is
It is input to the DCT circuit 14, converted from the time domain to the frequency domain, and then quantized by the quantization circuit 15. Further, since the differential signal and the video signal are added by the adding circuit 21 and input to the frame delay circuit 22,
A predicted video signal that predicts the input video signal from which the differential signal was created is created and input.

FIG. 42 shows a line signal in a state in which a video signal of a high-definition television signal has been subjected to the intraframe processing and the interframe processing as described above and then sent out on the transmission path. This signal is a signal of a transmission line, and is shown in a state in which a control signal, a voice signal, a synchronization signal (SYNC), a system control signal, NMP and the like are multiplexed. 42A shows the signal of the first line, and FIG. 42B shows the signal of the second and subsequent lines. If this video signal has undergone intraframe processing, a normal video signal can be obtained by inverse conversion. However, in the case of a video signal that has been subjected to interframe coding processing, the difference signal is only reproduced even if this signal is inversely converted. Therefore, a normal video signal can be reproduced by adding the video signal (or the predicted video signal) reproduced one frame before to the difference signal.

According to the above system, all the information in the signal processed in the frame is variable-length coded, and the signal processed in the inter-frame after the next frame transmits differential information. It means that the compression is realized.

Next, the definition of the set of pixels to be processed by the band compression system will be described. That is, a block: an area of 64 pixels composed of 8 pixels in the horizontal direction and 8 pixels in the vertical direction.

Super block: 4 in the horizontal direction of the luminance signal
A block is an area composed of two blocks in the vertical direction. This area includes one block as the color signals U and V. The image motion vector obtained from the motion evaluation circuit 13 is included in units of super blocks.

Macroblock: 11 superblocks in the horizontal direction. In addition, when the code is transmitted, the DCT coefficient of the block is converted into a code determined by the number of consecutive zero coefficients and the amplitude of the non-zero coefficient, and these are transmitted as a set to transmit the code of the block. Finally, an end of block signal is added. Then, the motion vector of the motion correction performed in units of super blocks is
It is added and transmitted in macroblock units.

For the transmission signal shown in FIG. 42,
A further description will be made on particularly related matters. First
The line synchronization (SYNC) signal indicates a frame synchronization signal in the decoder, and one timing synchronization signal is used for one frame to generate all timing signals of the decoder. The NMP signal on the first line indicates the number of video data from the end of this signal to the beginning of the macroblock of the next frame. This is because the code is configured by adaptively switching between the intra-frame coding process and the inter-frame coding process, so that the code amount of one frame differs for each frame, and the code position differs. This is because of Therefore, the position of the code corresponding to one frame is indicated by the NMP signal.

As a countermeasure when the user changes the channel, periodical intraframe processing is performed. That is, in this band compression system, as described above, 11 super blocks in the horizontal direction are called macro blocks, and 44 super blocks exist in the horizontal direction of one screen. That is, in one frame, there are a total of 240 macroblocks of 4 macroblocks in the horizontal direction and 60 macroblocks in the vertical direction. And in this band compression system, FIG. 43 (a)-(h)
As shown in FIGS. 44 (a) to 44 (c), refresh is performed in units of four macroblocks in each vertical column of superblocks, and all superblocks are refreshed in 11 frame cycles. That is,
The refreshed super block is shown in FIG.
As shown in FIG. 5, by accumulating 11 frames, the intra-frame processing is performed in all areas. Therefore, during normal playback of a VTR (video tape recorder) or the like, the above-mentioned intraframe processing is 1
Since it is performed in one frame cycle, the reproduced image can be viewed without any problem.

Head data is inserted at the beginning of the macroblock. This head data contains
The motion vector, field / frame determination, PCM / DPCM determination, quantization level, etc. of each superblock are inserted together. By the way, the band compression system described above is used as an encoder for band compression of a television signal, and the decoder is used on the receiving side.

Now, let us consider recording the above transmission signal in a VTR. A general VTR is a system in which a video signal of one field is converted into a fixed length code, a certain amount of information is generated, and recorded on X (X is a positive integer) tracks.

On the other hand, if the transmission signal obtained by the band compression system is used as it is for recording / reproducing in the VTR, the variable length code is used as it is for the code processed in the frame and the code processed between the frames, so that it is periodically used. The position where the code processed in the frame is recorded is not fixed,
Blocks that are not refreshed may occur during editing, switching of recording signals and reproduction signals, and high-speed reproduction.

More specifically, FIG. 45 shows a track pattern when the variable-length coded signal as described above is helically recorded on the magnetic tape 26. In track patterns T ₁ through T _11, a portion indicated by a thick line indicates the switching position of the frame F ₁ to F _11. The switching positions of the frames F _{1 to} F ₁₁ are not aligned because the record data is created by the variable length code. In the magnetic tape 26, when normally reproduced by a VTR, all track patterns T _{1 to} T ₁₁ are sequentially scanned by the magnetic head. Therefore, by passing the reproduction output to the decoder, no problem occurs. It is possible to reproduce various video signals. That is, at the time of normal reproduction, it is possible to reproduce all the intra-frame processed codes and the inter-frame processed codes recorded on the magnetic tape 26, so that an image can be constructed using all the codes.

However, in the VTR, there are cases where reproduction is performed from a limited number of tracks such as editing. In this case, there is no problem if the tracks of the signal subjected to the intra-frame coding process are reproduced one after another, but if reproduced from the tracks subjected to the inter-frame coding process, only the image by the difference signal is obtained.

[0020]

As described above, in the editing of the switcher or the recording / reproducing apparatus having the conventional band compression system, there is a problem that only the image by the differential signal can be obtained.

Therefore, the present invention has been made in consideration of the above circumstances, and provides an extremely good inter-frame band compression signal switching circuit which can easily obtain a good reproduced image at the time of signal switching or editing. With the goal.
It is another object of the present invention to provide a device capable of switching and editing a wideband signal such as a high-definition TV while maintaining high image quality.

[0022]

An interframe band compression signal switching circuit according to the present invention inserts an interframe band compression signal whose generated code amount changes for each frame, independently of a code boundary for each frame. A circuit for switching between two band compression signals having a periodic synchronization signal is configured to generate a switching output by matching the phases of the periodic synchronization signals of the two band compression signals.

Further, the inter-frame band compression signal switching circuit according to the present invention is a circuit for switching the two inter-frame band compression signals A and B having the refresh processing for periodically performing the intra-frame processing from the signal A to the signal B. In the above, a memory for storing the maximum generated code amount in the refresh processing period is provided, and when the switching request signal is generated, the signal B
The signal B is read out using the refresh signal of 1.

Further, the inter-frame band compression signal switching circuit according to the present invention is a circuit for switching the two inter-frame band compression signals A and B having the refresh processing for periodically performing the intra-frame processing from the signal A to the signal B. In the above, a memory for storing the maximum generated code amount in the refresh processing period is provided, and when the switching request signal is generated, the signal B
The circuit for reading the signal B from the refresh signal and the circuit for generating the signal switching overhead data at the time of switching are provided.

Further, the inter-frame band compression signal switching circuit according to the present invention outputs two inter-frame band compression signals A and B having a refresh process for periodically performing the intra-frame process to all the areas of one screen. A circuit for switching from A to signal B has a memory for storing the maximum generated code amount in the refresh processing period, reads the signal B from the refresh signal of the signal B when the switching request signal is generated, and The rate buffer occupancy RBn of the signal B (n is a frame number in which the signal B is refreshed) and the buffer occupancy RAn of the signal A in the frame in which the signal B is refreshed are defined as ΔR = RAn−RBn. However, when ΔR> 0, a maximum ΔR dummy signal is generated when switching from signal A to signal B. It is configured to.

Further, the inter-frame band compression signal switching circuit according to the present invention outputs two inter-frame band compression signals A and B having a refresh process for periodically performing the intra-frame process to all areas of one screen. A circuit for switching from A to signal B has a memory for storing the maximum generated code amount in the refresh processing period, reads the signal B from the refresh signal of the signal B when the switching request signal is generated, and The rate buffer occupancy RBn of the signal B (n is a frame number in which the signal B is refreshed) and the buffer occupancy RAn of the signal A in the frame in which the signal B is refreshed are defined as ΔR = RAn−RBn. And RAn <RB
RA (n−i) ≧ RBn− when n, that is, ΔR <0
r · i (r is the output rate per frame, RA (n−
i) n-i is a frame number of the signal A and is a real number n
-I is detected, and the signal A is output as the output signal of the switching circuit from the frame number n-i, the signal B is output from the frame number n, and the skip signal is output during the period from the frame number n-i to n. There is.

[0027]

According to the above-mentioned structure, first, when the two inter-frame band compression signals are switched, it is possible to easily synchronize the synchronization signals periodically, so that the image disturbance does not occur at the time of switching. Further, when switching between the two inter-frame band compression signals, it is possible to output only the correct image by starting from the image processed in the frame. Furthermore, it becomes possible to output a bit stream by switching between two inter-frame band compression signals, and by inputting this bit stream to the band compression decoder, a correct switching image can be obtained. Further, it becomes possible to output the bit streams of the two inter-frame band compression signals to the transmission path of the fixed transmission rate, and by inputting these bit streams to the band compression decoder, the correct switching image can be obtained. .

[0028]

Embodiments of the present invention will be described in detail below with reference to the drawings (note that the novel construction is shown by a double frame in the block diagram).

1. Band Compressor Basic Configuration FIG. 1 is a diagram showing the basic configuration of the present invention. The luminance signal Y and the color signals U and V of a high definition TV or the like are input to the video input terminals 27, 28 and 29. After subjecting these signals to necessary pre-processing, the blocking circuit 30 configures a block having a pixel configuration, which will be described later in Chapter 2, and inputs the block to the input terminal 11. The video signal input to the input terminal 11 is supplied to the subtraction circuit 12 and the motion evaluation circuit 13, respectively.
In the subtraction circuit 12, a subtraction process described later is performed,
The output is input to the DCT (discrete cosine transform) circuit 14.

The DCT circuit 14 takes in 8 pixels in the horizontal direction and 8 pixels in the vertical direction as a unit block (8 × 8 pixels = 64 pixels), and outputs a coefficient obtained by converting the pixel array from the time domain to the frequency domain. Then, each coefficient is quantized by the quantization circuit 15. In this case, the quantization circuit 15
It has 10 or 32 types of quantization tables, and each coefficient is quantized based on the selected quantization table. The quantizing circuit 15 is provided with a quantizing table so that the amount of information generated and the amount of information sent are within a certain range.

The coefficient data output from the quantization circuit 15 is zigzag-scanned from the low frequency band to the high frequency band for each unit block, and is extracted.
It is inputted to 6 and variable-length coded by combining the number of zero coefficients (run length) and the non-zero coefficient as one set. The encoder is a variable-length encoder having a different code length depending on the frequency of occurrence of Huffman code or the like.

The variable-length coded data is input to a rate buffer (FIFO: first-in-first-out) 17 and read at a prescribed speed, and then the next stage via an output terminal 18. Multiplexer 10
It is supplied to the control signal, audio data, synchronization data (SYNC), NMP, etc., which will be described later, and is sent from the output terminal 8 to the transmission line. Rate buffer (FIFO) 1
The output 7 of the variable-length coding circuit 16 has a variable rate and the rate of the transmission path is fixed, and therefore 7 serves as a buffer that absorbs the difference between the generated code amount and the transmitted code amount.

The output of the quantization circuit 15 is input to the inverse quantization circuit 19 and inversely quantized. Further, the output of the inverse quantization circuit 19 is input to the inverse DCT circuit 20 and returned to the original signal. This signal is input to the frame delay circuit 22 via the adder circuit 21. The output of the frame delay circuit 22 is supplied to the motion compensation circuit 23 and the motion evaluation circuit 13, respectively. Motion evaluation circuit 13
Is the input signal from the input terminal 11 and the frame delay circuit 2
The output signal of 2 is compared to detect the overall motion of the image, and the phase position of the signal output from the motion compensation circuit 23 is controlled. In the case of a still image, the original image and the image one frame before are compensated so as to match each other. The output of the motion compensation circuit 23 can be supplied to the subtraction circuit 12 via the switch 24, and can also be fed back from the addition circuit 21 to the frame delay circuit 22 via the switch 25.

Next, the basic operation of the above system will be described.

2. The signal input to the pixel configuration input terminal 11 forms a block, a super block, and a macro block by collecting a plurality of effective pixels in one screen. This configuration is based on DigiCipher
(Trademark) as an example, but MPEG or DSC-HDTV: Ze
It goes without saying that the block configuration used in the nith + ATT method or the like may be used.

The definition of the block configuration will be described with reference to FIG.

Block: An area of 64 pixels composed of 8 pixels in the horizontal direction and 8 pixels in the vertical direction (see FIG. 2).
(See (d)).

Super block: 4 in the horizontal direction of the luminance signal
A block is an area composed of two blocks in the vertical direction. This area includes one block as the color signals U and V. The image motion vector obtained from the motion evaluation circuit 13 can be set in units of super blocks (see FIG. 2 (c)).

Macroblock: 11 superblocks in the horizontal direction. In addition, when the code is transmitted, the DCT coefficient of the block is converted into a code determined by the number of consecutive zero coefficients and the amplitude of the non-zero coefficient, and these are transmitted as a set to transmit the code of the block. Finally, an end of block signal is added. Then, the motion vector of the motion correction performed in units of super blocks is
It is added as overhead data in units of macroblocks and transmitted (see FIG. 2B).

That is, in this band compression system, as described above, the 11 super blocks in the horizontal direction are called macro blocks, and 44 in the horizontal direction of one screen.
Super block exists. That is, in one frame, there are a total of 240 macroblocks of 4 macroblocks in the horizontal direction and 60 macroblocks in the vertical direction.

In this band compression system, FIG.
As shown in (a) to (h) and FIGS. 4 (a) to (c), refresh is performed in units of four macroblocks in each vertical column of the superblock, and all the superblocks are generated in a cycle of 11 frames. Is refreshed. That is, as shown in FIG. 4D, the refreshed super block is accumulated for 11 frames, so that the intra-frame processing is performed in all the areas.

One screen: 1050 scanning lines, which are interlaced. The effective pixel is horizontal 14
It is composed of 08 pixels and 960 pixels in the vertical direction. Video signals for one screen are processed by four processors (Fig. 2
(See (a)).

FIG. 5 shows the relationship between one screen and a super block address (hereinafter referred to as SBA = Super Block Address). There are 44 super blocks in the horizontal direction and 60 super blocks in the vertical direction. Therefore, there are 2640 super blocks in one screen. The address S. B. Assign A. If the horizontal superblock address is x and the vertical superblock address is y, S.S. B. A = 60 ・ x + y
Have a relationship.

3. Intra-frame / inter-frame coding The first basic operation of this system is intra-frame coding processing and inter-frame coding processing. The intraframe coding process is performed as follows. When this process is performed, both switches 24 and 25 are off. The video signal of the input terminal 11 is converted from the time domain to the frequency domain by the DCT circuit 14 and quantized by the quantization circuit 15. The quantized signal is subjected to a variable length coding process and then output to a transmission line via a rate buffer (FIFO) 17. The quantized signal is returned to the original signal by the inverse quantization circuit 19 and the inverse DCT circuit 20,
It is delayed by the frame delay circuit 22. Therefore, in the intra-frame coding process, it is equivalent to that the information of the input video signal is variable length coded as it is. This intra-frame processing is performed at a proper cycle in units of predetermined blocks and scene changes of the input video signal. The periodic in-frame processing will be described later.

Next, the interframe coding process will be described. When the interframe coding process is executed, both switches 24 and 25 are turned on. Therefore, the subtraction circuit 12 obtains a signal corresponding to the difference between the input video signal and the video signal one frame before. This difference signal is
It is input to the DCT circuit 14, converted from the time domain to the frequency domain, and then quantized by the quantization circuit 15. Further, since the differential signal and the video signal are added by the adding circuit 21 and input to the frame delay circuit 22,
A predicted video signal that predicts the input video signal from which the differential signal was created is created and input. Generally, the generated code amount of the image processed in the frame is larger than the generated code amount of the image processed in the inter-frame.

4. Intra-frame / inter-frame switching process 4.1 Image adaptive intra-frame process Switching between the intra-frame coding process and the inter-frame coding process is controlled by the intra-frame / inter-frame determination circuit 31 shown in FIG. There are two types of this control method. First, the first method is a method of performing inter-frame processing on a signal having inter-frame correlation and performing intra-frame processing on a signal having no inter-frame correlation in accordance with the content of an input video signal. . When a scene change or the like occurs, in-frame processing is performed. The intra / interframe determination circuit 31 compares the prediction error energy between the signal of the current frame from the input terminal 11 and the prediction signal output from the motion compensation circuit 23 with the energy of the current signal.

In FIG. 6, the current signal is input to the input terminal 11. This current signal is input to the energy comparison circuit 36 and the subtraction circuit 37. Input terminal 33
The prediction signal of the output of the motion compensation circuit 23 is input to, and the subtraction circuit 37 calculates the prediction error which is the difference between the current signal and the prediction signal. The current signal is obtained by the current signal energy calculation circuit 36a,
The prediction error is calculated by the prediction error energy calculation circuit 36b and the energy is compared. Examples of energy calculation formulas for the current signal and the prediction error are as follows.

[0048]

[Equation 1] FIG. 7 shows an example of the intra-frame / inter-frame discrimination method in the energy comparison circuit 36. In the figure, the horizontal axis represents the energy of the current signal and the vertical axis represents the energy of the prediction error. Further, a solid line drawn from the origin 0 in a slanted line shows a case where the energy of the prediction error and the energy of the current signal are equal. Since the energy of the prediction error is smaller in the area below the solid line, inter-frame processing is performed. Also, since the energy of the current signal is smaller above the solid line, intra-frame processing is performed. The output of the energy comparison circuit 36 outputs an intra-frame / inter-frame discrimination signal adapted to the input signal, the addition circuit 38 combines the signals, and the output signal is output from the output terminal 34.

4.2 Forced In-frame Processing (Refresh) The second method is a method of forcibly performing in-frame processing regardless of the correlation of video signals. In this case, the in-frame processing is periodically performed on a predetermined area of the screen. There are two purposes for performing this forced in-frame processing. It is necessary for the user to recognize the image within a certain time when the user changes the channel. This is so that special reproduction can be realized in a recording medium such as a VTR or a disc. This forcible in-frame processing is called refresh.

The time required for refreshing a predetermined area is called the refresh time. As shown in FIG. 6, the refresh timing generation circuit 39 inputs a sync signal from the input terminal 32 and generates an intraframe selection signal at a predetermined cycle in synchronization with the sync signal. Within this frame of this signal and energy comparison circuit 36
The inter-frame discrimination signal is added by the adder circuit 38, and the intra-frame / inter-frame switching signal is output from the output terminal 34.

5. Refresh Refresh of each of the following methods will be described in detail.

5.1 DigiCipher Refresh In DigiCipher, as described above, 11 super blocks in the horizontal direction are called macro blocks, and 44 super blocks exist in the horizontal direction of one screen. That is, in one frame, there are a total of 240 macroblocks of 4 macroblocks in the horizontal direction and 60 macroblocks in the vertical direction. Then, in the band compression system described in the present invention, as shown in FIGS. 3A to 3H and FIGS. Refresh is performed, and all the super blocks are refreshed every 11 frames. That is, as shown in FIG. 4D, the refreshed super block is accumulated for 11 frames, so that the intra-frame processing is performed in all the areas. The advantage of this refreshing is that refreshing is performed uniformly for each frame, so that the capacity of the rate buffer may be small.

This DigiCipher refresh is shown in FIG. 8 using the super block address shown in FIG. In the figure, the vertical axis represents the super block address, the horizontal axis represents the frame number, and the portion surrounded by a square r represents the portion processed in the frame. In the figure,
Only refresh blocks are shown. In the figure, all the super blocks of one screen are refreshed in 11 frames with frame numbers F _{0 to} F ₁₀ . Since the same processing is performed by the four processors, the refresh operation for each processor in FIG.
Refresh will be described with reference to FIG.

That is, S. B. Address = 0 to 659
Will be described. In FIG. 9A, the portion subjected to the refreshing and the image adaptive intra-frame processing is shown by enclosing r in a square. For example, assuming that a scene change has occurred at F ₀ , the S. B. Address 0
Intra-frame processing is applied to all the areas of 659. Further, in F ₁₄ , S. B. In-frame processing is performed in the area of addresses 0 to 59.

FIG. 9B shows the DigiCipher refresh time. A part of the area is refreshed per frame, and the refresh is completed in the 11-frame period, so that 11 frames become the refresh time. In addition, this refresh completes the refresh of one screen no matter what 11-frame period. That is, 1 of F _{0 to} F ₁₀
Refresh is completed in one frame period or 11 frame periods of F _{1 to} F ₁₁ .

As shown in FIG. 9C, the minimum acquisition time is one frame period and is obtained when the initialization starts when a scene change occurs. Further, the maximum acquisition time in FIG. 9D is a case where the image adaptive intra-frame processing does not occur at all, and is 11 frame periods. When the signal switching and the editing of the recording / reproducing apparatus are realized with the refresh block as the starting point, at each refresh block address, as shown in FIG.
One frame period is the refresh interval.

5.2 MPEG Refresh First, refresh used in MPEG will be described with reference to FIG. In MPEG, refresh is performed in frame units. The frame that has been refreshed is called an I picture. The cycle of this I picture, that is, the refresh cycle is set in units of frames, and 12, 15, ... Frames are selected. This situation will be described with reference to FIG. Note that only the case where the scanning line is 1050 will be described for simplification of description, but it goes without saying that other block configurations may be used.

In FIG. 10A, the vertical axis indicates the super block address. This super block address corresponds to the super block address defined in FIG. The horizontal axis represents the frame number. Further, the blackened portions indicate the portions that have been subjected to the in-frame processing. Here, frame numbers 0 and 1
2, 24, 36, ... Intra-frame processed images periodically inserted, frame numbers 13, 15, 17, 19, 2
The blackened portions indicated by 1 and 23 indicate the portions subjected to the image adaptive frame processing.

In this example, the refresh time is as shown in FIG.
It is 12 frames as shown in (b). In order to obtain an image on one screen when the user initializes by changing the channel, in-frame processing must be performed on the entire area of one screen. Therefore, this time is defined as follows.

Acquisition time: Time required for intra-frame processing to be applied to all areas of one screen.

This acquisition time also depends on the timing at which the user changes the channel. Figure 10 (c)
Shows the minimum acquisition time. The minimum acquisition time is when the start of initialization and refresh or scene change occur at the same time, and one screen image can be obtained in one frame period. FIG. 10D shows the maximum acquisition time. The maximum acquisition time is when the initialization starts immediately after the refresh is completed. In this case, one screen image is obtained in 12 frame periods.

Let us consider a case where signal switching and editing of the recording / reproducing apparatus are to be realized with a refresh block, which is a periodical intra-frame process, as a starting point. Since the refresh cycle is basically 12 frames, the refresh interval is 12 as shown in FIG.
It becomes a frame.

7. The DCT two-dimensional DCT circuit (14 in FIG. 1) will be described. First, the image is divided into small blocks (N × N) consisting of N pixels in both horizontal and vertical directions, and each block is a two-dimensional D
CT is performed. The size of N at this time is 8 to 8 from the conversion efficiency.
It is set to 16. In this embodiment, N = 8 is used. Two
The transform coefficient of the dimension DCT is given by the equation 1, and its inverse transform equation is given by the equation 2.

[0064]

[Equation 2] Here, F (0,0) represents the coefficient of the DC component, and F (0,0)
(U, v) includes a high frequency horizontal frequency component as u increases, and includes a high frequency vertical frequency component as v increases. First, the property of the coefficient of the DC component of F (0,0) will be described. F (0,0) corresponds to a DC component representing the average luminance value in the image block, and its average power is usually considerably higher than other components. Further, when the DC component is roughly quantized, noise (block distortion) peculiar to the orthogonal transformation, which is visually noticeable as a large image quality deterioration, occurs. So F
A large number of bits (usually 8 bits or more) is assigned to (0, 0) and uniform quantization is performed.

Next, the conversion coefficient F (u, v) excluding the DC component
Describe the nature of. The average value of F (u, v) is
It becomes "0" excluding that of the DC component F (0,0). For efficient coding, when allocating a certain number of bits to a small block of an image for coding, a large number of coding bits are allocated to the transform coefficient of the low frequency component, and conversely By allocating a small number of coding bits to the transform coefficient for coding, it is possible to reduce deterioration in image quality and perform coding at a high compression rate.

The image is converted into a small block of 8 × 8 = 64 pixels consisting of 8 pixels in both the horizontal and vertical directions, and the two-dimensional C
When DT is applied, the transformed coefficients for each frequency component become 8 × 8 = 64 two-dimensional coefficients as shown in FIG. In FIG. 11, the upper left is a DC coefficient (direct current component).
The other 63 are AC coefficients (AC components), and the spatial frequency becomes higher toward the lower right. Since the AC component has a two-dimensional spread, it is converted into one dimension by zigzag scanning shown in the order of 0 to 63 during encoding and transmission.

Here, the 64 DCT coefficients are converted to DCT _i
It is represented by [i = 0 to 63]. In the case of an image signal, the number of quantization bits for quantizing each pixel is often 8 bits. This 8-bit pixel is DCT
The DCT coefficient of the converted output may be represented by 12 bits.

8. Quantization Next, the quantization circuit (15 in FIG. 1) will be described. The 64 DCT coefficients described above are linearly quantized with a different step size for each coefficient position using a quantization table that defines a quantization step size for each coefficient. There are two types of quantization step setting methods, but basically the same method.

The first method is a method of transmitting a code indicating the quantization table using a quantization table in which a quantization step is determined for each of 64 DCT coefficients. FIG. 12 shows an example of the quantization table. In the figure, q = 0 to q
= 9 is a quantization table code representing a quantization table, and by transmitting this code, the decoder can perform inverse quantization. In addition, 64 arranged in a square
Each number indicates the number of quantized bits and has a correspondence relationship with the 64 two-dimensional coefficients shown in FIG. For example, q
The upper left 7 in the quantization table of = 0 indicates that the DC component is quantized with 7 bits. Hereinafter, each coefficient is similarly quantized with the number of bits shown in the quantization table.

In the second method, first, 64 DCT coefficients are weighted by a weighting matrix. After this, quantization width data QS (Quantize
-Scale), each coefficient is uniformly divided and then quantized. When transmitting, a code corresponding to the quantization width data is sent. Also, the weighting matrix has a default value. Furthermore, it is possible to transmit a specific type of weighting matrix.

As an example, MPEG. In I, 5 bits are assigned to the code of the quantization width data QS, and 32 types can be designated. Therefore, this value is set to QS _j [j =
0 to 31].

Here, the quantization width data QS _{j will be} defined.

The coefficient value of the DCT is quantized with the maximum number of quantization bits, and j = 0 is represented, and QS ₀ = 1.

Further, the case where the coefficient value of the DCT is not transmitted is represented by j = 31, and in this case, the number of quantization bits described later is QL ₃₁ = 0.

Here, j is named a quantization level.

In FIG. 13, MPEG. The default value of the weighting matrix of the luminance signal used in I is shown. In the figure, 64 numbers of 8 × 8 have a correspondence relationship with the 64 two-dimensional coefficients shown in FIG. 11, and indicate weighting values for each DCT coefficient.
In the encoder, each DCT coefficient is divided by the corresponding weighting value and the quantization width data QS.

The 64 DCT coefficients are represented by DCT _i = [i =
0-63] and each value of the weighting matrix is represented by W
EIGHT _i [i-0 to 63], each value after quantization is Q _i
When represented by [i = 0 to 63],

[Equation 3] It is represented by.

The number of quantization bits at this time is

[Equation 4] It is represented by.

An example is shown below. MPEG. The first AC component in the vertical direction of the luminance signal of I is D in FIG.
It is represented by CT ₁ . Also, the weighting matrix D
The value corresponding to CT ₁ is WEIGHT ₁ = 16.
This corresponds to the part marked with a circle in FIG.
Further, when the quantization width data QS ₀ = 1

[Equation 5] Since the coefficient of DCT _i is represented by 12 bits, log ₂ D
The maximum value of CT _i is 12. The number of quantization bits at this time is

[Equation 6] Becomes

FIG. 14 shows the maximum required number of quantization bits after passing through the weighting matrix when QS ₀ = 1. This diagram is a matrix representing the number of quantization bits of 8 × 8 = 64, and each number indicates the number of quantization bits corresponding to each position of the DCT coefficient shown in FIG.

FIG. 15 and FIG. 16 quantitatively show typical 9 types of quantization tables among the quantization tables when 32 types of quantization width data QS _j are set.

This table is based on the quantization width data QS in order to explain the case of using the above-mentioned second method concerning the quantization table.

Here, j = 31 is an example in which no data is generated, and it corresponds to quantizing all the coefficients with 0 bits. Further, j = 0 is the quantization width data QS ₀ = 1
Therefore, it is equivalent to quantization with a weighting table. That is, in this case, the bit allocation is based on the weighting table shown in FIG.

In FIGS. 15 and 16, the horizontal axis is DC.
Each of the 64 coefficients of T is shown, which corresponds to the order of zigzag scanning shown in FIG. In addition, the vertical axis represents the number of bits to be transmitted in each coefficient of DCT.

When quantizing the DCT coefficient, M
SB (Most Significant Bit) to LSB (Least Sign
ificant Bit) exists. When limiting the number of bits to be transmitted, naturally, the MSB is preferentially transmitted.

As described above, when the number of quantization bits for the DC component is reduced, block distortion or the like becomes conspicuous. Therefore, there is an example of separately treating the DC component or assigning a certain number of quantization bits. Here, it is assumed that 8 bits are assigned.

MPEG. In the case of the luminance signal of I, the maximum value of the AC component is 8 bits as described above.

The number of quantization bits and the quantization width data will be quantitatively described with reference to FIGS. 15 and 16. The generated code amount becomes maximum when j = 0, the generated code amount decreases as j increases, and becomes 0 when j = 31, and the code is not generated. It is possible to control the amount of code generated by controlling the quantization width data.

10. Code amount control There are two types of code amount control methods. The first method is a method of controlling the quantization level as described above. In this case, since the generated code amount of the refresh block is suppressed, the image quality of the refresh block itself is deteriorated. However, in the next frame, since the difference between the intra-frame processed signal of the refresh block and the video signal of the next frame is sent, the image quality is only momentarily degraded. This method will be described in detail later.

The second method is to divide the code, which has been quantized once, into two, and calculate the code amount of the MSB or the low frequency component by VTR.
It is a method that keeps the code amount that can be read out at the time of high-speed reproduction on a recording medium such as. Regarding this, 11. More on this in the chapter.

The control of the coded information amount when the first method is used will be described below.

10.1 Macroblock Code Amount Control When the video signal is high-efficiency coded using variable length coding as in the present embodiment, the generated information amount is generally not constant. This is because the amount of information contained in the video signal varies with time.

On the other hand, when a fixed rate transmission system is used, coding control is required to keep the coded information amount constant.

The general method of fixed rate conversion is to prepare a buffer memory at the output of the encoder, input this buffer memory at a variable rate, and perform the output at a fixed rate to smooth the encoded information amount. Is. Since the amount of data in the buffer memory changes according to the amount of input information, there is a possibility that overflow or underflow will occur. In order to prevent this, when overflow or underflow is likely, the encoding parameter is changed so as to reduce or increase the encoded information amount, respectively. For example, the quantization characteristic may be made coarser or finer.

The larger the capacity of the buffer memory is, the higher the smoothing effect is, but the coding delay and the cost are limited.

In addition, since a relatively small buffer memory allows finer control of encoding depending on the local nature of the image, a buffer memory of about 1 frame may be used.

The control of the macroblock code amount will be specifically described. The capacity of the rate buffer is used for controlling the code amount of the macroblock. In the method using the rate buffer, as shown in FIG. 17, the encoder and the decoder are provided with rate buffers of equal capacity.

The input / output code amount and the buffer occupancy of these buffers will be described with reference to FIG.
Reference numeral a in FIG. 17 indicates an input signal of the rate buffer b of the encoder. This signal is the output signal of the variable length coding circuit 16 of the encoder. The characteristic of this signal is that each block is input at a constant cycle, but the generated code of each block is a variable length code, so that it has a variable length rate. The output signal c of the rate buffer of the encoder is transmission data, and the code is output at a fixed rate. Further, the input signal d of the rate buffer e of the decoder is a code input of a fixed rate, and the output signal f is a code output of a variable rate.

The characteristics on the encoder side and the decoder side will be described in detail with reference to FIGS. 18 and 19, respectively. 18 (a)-(c) and 19 (a)-
The horizontal axis of (c) shows the frame number. Here, FIGS. 18A to 18C and FIGS. 19A and 19B are the same as the input frame number, but FIG.
The frame numbers of are shifted by 8 frames. This is necessary in order to absorb the fluctuation of the delay time of the transmission code of the encoder and the decoder due to the use of the variable length code.

18 (a) to 18 (c) and FIG. 19 (a).
The vertical axes of (c) to (c) indicate the code amount. In this example, the capacity of the rate buffer is 4 Mbits, and the transmission code amount per frame is 0.5 Mbits / frame. Note that FIGS. 18A to 18C show characteristics on the encoder side, and FIGS. 19A to 19C show characteristics on the decoder side.

FIG. 18A shows the amount of generated codes per frame. The broken line in the figure is shown with reference to the capacity of the rate buffer. Since the variable length code is used, the generated code amount of each frame differs depending on the frame. In F _{1 to} F ₉ in which the frame number is represented by F _n , examples of code generation when the buffer overflows and underflows are shown. At F ₁ , a 4.5 Mbit code is generated,
F ₂ ~F occur until ₉ code is set to 0.

The maximum value of the generated code amount of each frame is determined by the sum of the buffer capacity and the transmitted code amount. In the case of this example, the buffer capacity is 4 Mbits, and the transmitted code amount per frame is 0.5 [Mbits. / Frame], the maximum possible code amount per frame is 4.5 Mbits. F
Until ₂₀ to F _30, an example of a case where the control generated code amounts of the respective frames by the buffer occupancy.

FIG. 18B shows the occupancy of the encoder buffer. In this example, the buffer capacity is 4M
The capacity of the buffer is indicated by a broken line. F
_{Since a} large amount of generated code is generated in ₁ frame, F
_At the time of ₁ , a buffer overflow has occurred. F
_{Since the} code is not generated at all from _{2 to} F ₉ , the buffer underflow occurs at the time of F ₉ .

FIG. 18C shows the transmission code amount from the encoder. A solid straight line A drawn diagonally in the figure shows the cumulative transmission code amount. This inclination indicates the amount of transmitted code per frame. In this example, 0.5M bits are transmitted per frame time. Frame rate is 30
In the case of [Hz], 30 × 0.5 [M / Frame] =
The transmission code amount is 15 [Mbps]. The broken line shows the maximum value determined by the maximum capacity of the buffer.

The polygonal line shown in FIG. 18 (c) is
The cumulative generated code amount is shown. That is, FIG. 18 (a)
Is the integrated value of the generated code amount per one frame.
When the accumulated generated code amount contacts the broken line, the buffer overflows, and when it contacts the solid line, the buffer underflows. The dotted line drawn horizontally between the cumulative generated code amount and the cumulative transmitted code amount indicates the delay time in the encoder buffer when transmitting the generated code, and the longer one indicates the longer time until transmission. This shows that.

In FIG. 19 (a), the solid line B shows the cumulative received code amount. This quality straight line B is shown in FIG.
Is the same as the real straight line A. The polygonal line indicates the projection code amount of each frame when the image is output. This is
This corresponds to a value obtained by integrating the projection code amount per frame in (c). Further, the dotted line drawn horizontally represents the delay time when the received code is displayed, and the sum of the delay time in the encoder and the delay time in the decoder is all equal, and the buffer delay shown in FIG. Time (Buffer D
elay).

FIG. 19B shows the occupancy of the decoder buffer. Here, FIG. 18B and FIG.
Compare with (b). Figure 1 shows only the buffer delay time.
When 8 (b) is shifted, FIG. 18 (b) and FIG. 19 (b) are vertically inverted. That is, an encoder overflow results in a decoder underflow, and an encoder underflow results in a decoder overflow.

FIG. 19C shows the projected code amount per frame of the projected code. FIG. 18A and FIG.
9 (c) is delayed by the buffer delay time of the encoder and the decoder.

When the subscriber changes the channel, it is possible to output the video after accumulating the code of the required code amount in the buffer of the decoder. This accumulated amount is
It is equal to the value for accumulating the received code amount only for the time shown by the dotted line in FIG. This value has a corresponding relationship with the NMP signal of the conventional example. That is, the decoder may store the code in the buffer for the time determined by the NMP signal and then output the video.

As shown in F ₁ of FIG. 18A, when the maximum code amount occurs in the first frame, the maximum buffer delay time occurs in the decoder buffer.
In this case, it is possible to output a normal video signal after accumulating the received code in the buffer for the time indicated as buffer delay in FIG. In this case, the video signal is output normally after the buffer of the decoder is filled with the received code.

That is, the received codes are accumulated from F _{0 to} F ₈ and a normal video signal is output after the initialization state filling the buffer memory is completed. When the projection code is output in F ₁ of FIG. 19C, the buffer of the decoder is underflowed. In addition, FIG.
When the state in which the projection code is not output from F _{1 to} F _{9 in} (c) continues, the buffer of the decoder overflows at F ₉ . This corresponds to the state in which the buffer state of the encoder is delayed by 8 frames and the overflow and underflow are inverted.

When the subscriber changes the channel, in order to output a normal video signal, it is necessary for the buffer of the decoder to store the code for the time according to the NMP signal. It is possible to output an incomplete image as shown by the dotted line in c).

FIG. 20 shows an example of the relationship between the buffer occupancy and the increase / decrease in the quantization level set for each macroblock. The quantization level is not changed while the occupancy of the buffer is at a predetermined value, and the quantization level is increased or decreased when the buffer occupancy exceeds the predetermined value. In FIG. 20, when the occupancy of the buffer is 45 to 55%, the quantization level is not changed,
When this value is exceeded, the quantization level is changed. This makes it possible to control the rate of the buffer.

Since the quantization level is roughly quantized when the value of j is large and the generated code amount is small, the quantization level is lowered when the buffer occupancy is small, and the quantization level is decreased when the buffer occupancy is large. Operate in the raising direction.

FIG. 21 shows a configuration for realizing the above operation. To determine the macroblock quantization level, the quantization level setting circuit 53 and the super block code amount calculating circuit 54 are used.

First, a method of calculating the code amount of the super block will be described in detail with reference to FIG. The output of the quantization circuit 15 is input to the variable length coding circuit 16. In the variable length coding circuit 16, an 8 × 8 DCT is used in the zigzag scanning circuit 16a by the scanning method shown in FIG.
The coefficient of is read, the number of consecutive 0 coefficients and the amplitude of the non-zero coefficient are combined and input to the Huffman coding circuit 16b.

Further, the number of consecutive 0 coefficients and the amplitude of the non-zero coefficient are input to the super block code amount calculating circuit 54.
This super block code amount calculation circuit 54 calculates the generated code amount using a ROM (read only memory) that stores the table shown in FIG.

Although FIG. 22 is also used in the conventional example, the horizontal axis shows the amplitude of the non-zero coefficient and the vertical axis shows the number of consecutive 0 coefficients. The numbers in the frame indicate the number of bits of the code. The number of bits of this code is added to calculate the generated code amount in units of super blocks.

Further, in order to determine the quantization level of the macroblock, the macroblock code amount calculation circuit 55
Then, the code amounts of the 11 super blocks are added to calculate the code amount of the macro block.

Further, the transmission code amount stored in the transmission code amount ROM 56 is subtracted from this value, and the rate buffer occupancy rate is calculated by the rate buffer code amount calculation circuit 57.

The macroblock quantization level setting circuit 58 is based on this rate buffer occupancy rate and the graph of FIG.
Then, the quantization level for each macroblock is set.

10.2 Superblock code amount control The code amount control per superblock can be controlled only in the direction in which the quantization level is coarser than the quantization level determined by the macroblock.

This is because, for example, if there is a superblock processed in the frame, the code amount processed in the frame is larger than the code amount processed in the interframe.
This is because the code amount may be significantly increased in this super block processed in the frame.

On the other hand, the human visual characteristic is that when the contents of the image change, for example, when a scene change occurs or when a part hidden behind a moving object appears (this is called a covered back). , The eyes cannot react quickly and precisely, and a certain amount of time is required.

Therefore, it is difficult to determine the deterioration of the image quality of the intra-frame processing portion caused by the change of the image content, even if the quantization level is coarse. That is, the code amount can be reduced in the portion where the image adaptive intra-frame processing has occurred.

A configuration for realizing this operation will be described with reference to FIG. Super block quantization level setting circuit 60
The image adaptive intra-frame / interval determination signal which is the output of the energy comparison circuit 36 in the intra-frame / interval determining circuit 31 is input to the input terminal 61. Further, the output signal of the DCT circuit 14 is input from the input terminal 62 and is input to the DCT coefficient energy calculation circuit 63, the energy of the DCT coefficient is calculated, and the correction level of the quantization level is determined by this energy. This value is input to the quantization circuit 15 through the addition circuit 64 that adds the value to the macroblock quantization level. The relationship between this energy and the correction level is shown in FIG.
There is the relationship shown in (a).

Further, even in the super block subjected to inter-frame processing, if the energy is extremely large, it means that there are many high frequency components, and in this case also, it is difficult to determine the deterioration of the image quality. The conversion level may be coarse. In this case, the correction level is set as shown in FIG.

13. Bitstream structure The bitstream structure of each block is shown below.

In FIG. 1, overhead data of the output of the overhead data generating circuit 67 is added to the output of the variable length coding circuit 16, and the result is output to the output terminal 68.

The bit stream output from the band compression apparatus is sent using the bit stream of the macro block shown in FIGS.

14. Block Layer Bitstream Structure A block is composed of 64 DCT coefficients obtained by DCT-transforming 8 × 8 pixels adjacent to each other in luminance or color difference. 6
The four DCT coefficients are subjected to zigzag scanning in the order shown in FIG. 11, and two-dimensional Huffman coding is performed using a run length of zero coefficient and an amplitude of nonzero coefficient as a pair to form a bit stream. At the end point of the code of one block of DCT,
A Huffman code of EOB is added.

15. Super block layer bit stream structure A super block is composed of 8 adjacent luminance blocks in the horizontal direction 4 and 2 in the vertical direction, and a total of 10 color difference blocks of U and V that are at the same position on the image. It The order of transmission is Y ₀ , Y ₁ , Y ₂ , T
₃ , T ₄ , Y ₅ , Y ₆ , Y ₇ , U and V. As the DC component of the luminance signal, a value obtained by calculating the difference between adjacent blocks is sent.

16. Macroblock Address First, the relationship between the position of the macroblock on the screen and the address is defined. FIG. 25 shows an example of the address setting method.

As shown in FIG. 24, the macroblock is 1
It consists of one super block, and consists of one refresh block and ten non-refresh blocks. Further, the address of the super block on one screen is set as shown in FIG.

16.1 Macro Block Address As shown in FIG. 25, the macro block address is assigned the same address value as the address value of the super block at the head of the macro block.

16.4 Address Value As shown in FIG. 5, this address value is S.0 when the horizontal super block position is x and the vertical super block position is Y. B. It is represented by Address = 60x + y.

Here, since the DigiCipher uses four processors in the horizontal direction, I indicates this processor.
If D is PID and the ID indicating the vertical position is VID, the address value is MBA (Macro Block Address) = (60 · 11) · PID + 60 · x ₀ + VID RBA (Refresh Block Address) = (60 · 11) ) · PID +60 · x ₀ + VID NRBA (Non Refresh Block Address) = (60 · 11) · PID + 60 · x ₀ + VID

Here, x ₀ is the horizontal position of the macro (non-) refresh block when PID = 0 and VID = 0.

Although FIG. 25 shows the case where x ₀ = 0, naturally x ₀ = _{0 to} 43 are used. Also this x
₀ corresponds to frame count in the conventional example.

17. Macro (non-) refresh block bitstream structure 17.1 Macroblock bitstream structure Figure 26 shows a macroblock bitstream structure.

With regard to the bit stream shown in FIG. 26, the items conventionally used will be described first. This content is based on the following two documents, and each exhibiting document number is shown.

(A) "DigiCipher Description" Aug.
22 1991 (b) “Channel compatible DigiCipher HDTV System
”April 3. 1992 Details about each item in the bitstream.

In FIG. 26, the bitstream structure in the macroblock is composed of overhead data and variable length code.

Processor ID: Since DigiCipher uses four processors, the number of this processor is indicated by 2 bits (reference b).

Macroblock Quantization Level (MQL):
The quantization level QL is represented by 5 bits, and the larger the value, the coarser the quantization, the macroblock quantization level MQ.
L = 31 indicates a state in which no code is generated.

2-bit correction quantization level: The correction quantization level is set in the direction of coarser quantization than the macroblock quantization level MQL (reference a). Further, the correction quantization level is 2 bits per superblock (reference b). Also, it is set for 11 super blocks (reference a). This corresponds to the corrected quantization level described in Chapter 10, Section 10.2.

Field / frame discrimination: DCT 8 ×
The pixel configuration of 8 pixels specifies whether to use the field pixels or the frame pixels, and is set for each super block unit (reference a).

PCM / DPCM Discrimination: Super-block intra-frame processing (PCM) or inter-frame processing (DPC)
M) distinction (reference a).

Motion vector: The motion vector of each super block is shown (reference a).

Next, a new bit stream structure will be described.

Path ID (PSID): When PSID = 0, the path through which the macroblock quantization level exists is taken.

When PSID = 3, the special mode (T
RK).

When PSID = 2, the block ID,
Take the route where the block address exists.

When PSID = 1, the path is the path in which the Fill Bits code length and the Fill Bits code exist.

Trick quantization level TQL: It is possible that superblocks of a plurality of band compressors are mixed in one macroblock. In this case, the following two points are required.

First, when a plurality of superblocks having different band compressors are present in one macroblock, each superblock requires a quantization level of 5 bits.

Secondly, it is necessary to specify the position of the super block in which the data in the macro block is ignored.

In order to specify this position, skipping in super block units is required. Therefore, when the band compression signal is switched, it is set so as to pass through the path of the trick quantization level TQL.

The trick quantization level TQL has an absolute quantization level of 5 bits for each super block. Therefore, 11 super blocks contain 55-bit quantization levels.

Further, by setting TQL = 31, it becomes possible to skip variable length codes in units of super blocks.

As a result, it becomes possible to arrange the variable length codes of the super blocks of the plurality of band compression devices at arbitrary positions within the macro block.

As shown in FIG. 26, there is a correspondence relationship between the trick quantization level TQL and the variable length code of each super block. TQL ₀ is a super block 0 TQL ₁ is a super block 1: TQL ₁₀ is a super block 10. 3 shows the respective trick quantization levels TQL of

When switching signals, super blocks 0 to 0
Of 10, the variable length codes of the super blocks of the plurality of band compression devices are arranged at the corresponding super block positions in the macro block, and the other super block parts set the trick block quantization level TQL = 31, Performs skips in super block units.

As another example of the bitstream structure representing skip, there is also a method of inserting EOB (ent of block) at the position of the variable length code of the corresponding superblock.

Special mode (TRK): When sending a bit stream of broadcast waves or sending a bit stream during normal reproduction, set TRK = 0 and set the path of 2-bit correction quantization level (PQL = 0). Pass through.

In the signal switching mode, TRK =
Set to 1 and go through the path indicating the trick quantization level described above.

Block ID: ID indicating the distinction between macroblock refresh blocks.

Block address: Indicates an address which is an absolute position on the screen of the macro. This block address is V
Even when an error occurs during TR reproduction or high-speed reproduction, the projection position information is sent to the decoder so that the video can be restored again instantly.

When PSID = 1 and PID = 2, the path of Fill Bits code length and Fill Bits code is passed. Here's an explanation of Fill Bits. Since the amount of code to be transmitted is constant, when the amount of band-compressed code is smaller than the amount of transmission code, a predetermined code is compulsorily inserted up to the amount of transmission code. This code is called a Fill Bits code, and this code length is called a Fill Bits code length.

Fill Bits code: A predetermined code is forcibly inserted when the generated code amount of the variable length code is small. The code that is forcibly inserted is called Fill Bits. In particular, when the band compression signal is switched, the generated code amount may decrease. Since the amount of transmitted code is constant, Fill Bits that are forcibly inserted are required.

Fill Bits Code Amount: By inserting the code length of the Fill Bits described above before the Fill Bits, the Fill Bits
Clarify the ending point of the sign of s. This makes it possible to clarify the boundary with the macroblock.

Macroblock code length: The sum of the code lengths of the macroblock overhead data and the macroblock variable length code in the macroblock of FIG. By using the above bit stream as the bit stream of the broadcast wave, the decoder that receives the broadcast wave can receive the signal whose band compression signal has been switched.

Vertical ID (VID _M ): Not present in the bitstream, but VID _M is defined as follows:
ID indicating the vertical position within one screen, 6 in the vertical direction
Since there are 0 macroblocks, VID _M = 0 to
It becomes 59.

25. Decoder Basic Configuration The basic configuration of the decoder will be described in detail with reference to FIG.

FIG. 29 shows a circuit using overhead data. Circuit name is shown on the horizontal axis and data name is shown on the vertical axis.
The marked area is the circuit used.

The normal bit stream and the broadcast wave bit stream in which signals are not switched have the same macroblock configuration.

In the case of a broadcast wave bit stream, the overhead data detection circuit 111 is used to detect the overhead data and decode it. The normal operation is
This operation is the same as the operation of decoding a broadcast wave, so this operation will be described first.

First, the variable length code of the bit stream of the macro block shown in FIG. 26 at the input terminal 127 is input to the variable length code decoding circuit 114. When extracting this variable length code, the end of block (EOB) is detected to extract the variable length code of each block from the bitstream. In the variable length code decoding circuit 114,
The Huffman code is sequentially detected by comparing the code with the Huffman table from the start position of the variable length code.
Using the detected Huffman code, the quantized DCT
Obtain the number of zero coefficients that follow (run length) and the nonzero coefficient (amplitude). Since the coefficients are arranged in the order in which the zigzag scanning is performed, the order of the coefficients can be rearranged as needed by the inverse DCT circuit 115.

The signal obtained by decoding the variable length code is input to the inverse quantization circuit 116. In the inverse quantization circuit 116, the macroblock quantization level is corrected with the superblock correction quantization level, and the quantization level is obtained in units of superblocks.

Next, each of the 64 coefficients per block is first multiplied by a weighting value according to a weighting table.

Next, by multiplying each of the 64 coefficients by a quantization scale value according to the quantization level of the super block unit, inverse quantization is performed and DCT coefficients are obtained. (Here, the case of the second quantization method described in Chapter 8 has been described.) The 64 DCT coefficients are passed through the inverse DCT circuit 115, and the coefficients in the frequency domain are converted into the time domain. Then, a signal of 64 pixels of 8 pixels in the horizontal direction and 8 pixels in the vertical direction is obtained.

The output of the inverse DCT circuit 115 is input to the adder circuit 117.

Further, the addition circuit 117 has a switch 118.
Signal is input and is added to the output signal of the inverse DCT circuit 115. The switch 118 is controlled by the intra-frame / inter-frame switching circuit 119. The output signal of the adder circuit 117 is input to the deblocking circuit 120 and the frame delay circuit 121.

The frame delay circuit 121 is composed of a frame memory, and the output signal of this frame memory is input to the motion compensation circuit 122 and the deblocking circuit 120.

The output signal of the motion compensation circuit 122 is input to the switch 118.

The deblocking circuit 120 includes the adder circuit 11
7 and the signal from the frame delay circuit 121 are used to perform band compression signal processing and processing for matching the display order of TV scanning lines,
The luminance signal and the color difference signals U and V are output from the output terminals 123 to 125.

The decoder operation includes intraframe processing and interframe processing. In the switch 118, in-frame processing is performed when the switch 118 is off.
When is on is the inter-frame processing. This switch 11
8 ON / OFF control circuit 1 for switching between frames
19 perform.

PCM / DPC in overhead data
The M discrimination signal is input to the intra-frame / inter-frame switching circuit 119 through the connection terminal 126. Here, PCM means intra-frame processing, and DPCM means inter-frame processing. PC
Switch off with M, switch 118 with DPCM
Turn on. As described in Chapter 3, intraframe / interframe processing includes image adaptive intraframe processing and refresh (forced intraframe processing).

First, the operation of the intraframe processing will be described. During the intra-frame processing, the output signal of the inverse DCT circuit 115 is output to the frame delay circuit 121 and the deblocking circuit 1.
20 and outputs a luminance signal Y and color difference signals U and V.

Next, the operation of the interframe processing will be described.
In this case, 1 stored in the frame delay circuit 121
The prediction signal before the frame is read out, and the motion compensation circuit 122
To enter.

Further, the motion vector of the overhead data is input to the motion compensation circuit 122 from the connection terminal 126,
Shift the position of the predicted signal on the screen. Inverse DCT circuit 115
Output from the motion compensation circuit 122, a predictive signal corresponding to the position on the screen of the output signal of
It is input to the adder circuit 117 through 18. Adder circuit 11
7, the output of the inverse DCT circuit 115 and the prediction signal are added, and the frame delay circuit 121 and the deblocking circuit 1 are added.
Enter in 20. Then, the luminance signal Y and the color difference signals U and V
Are separated and output from the output terminals 123 to 125.

The variable length code decoding circuit 114, the inverse quantization circuit 116, and the inverse DC for the broadcast wave and the normal time described above.
The writing process to the T circuit 115 and the frame delay circuit 121 is always performed based on the macro block.

That is, the processing of these circuits per processor is based on the sequential processing of 11 super blocks in the macro block, and the macro blocks are sequentially processed on the screen from top to bottom.

28. Frame Delay Circuit The frame delay circuit 121 has a memory write address generation circuit 121a as shown in FIG.

Here, the operation of the frame delay circuit will be described by taking the case of DigiCipher as an example. However, other methods (MP
(EG etc.), the basic matters are the same.

In the case of DigiCipher, the processing is performed by four processors, and there are four macroblocks in the horizontal direction. Therefore, one macroblock is processed in the horizontal direction for each processor.

Therefore, per processor, macroblocks are processed from top to bottom in units of 11 superblocks in the macroblock.

A circuit for performing processing by these four processors is a variable length code decoding circuit 114, an inverse quantization circuit 116,
Inverse DCT circuit 115, adder circuit 117, motion compensation circuit 1
22, an intra-frame / inter-frame switching circuit 119 and a switch 118, and a write address generation circuit 121a in the frame delay circuit 121.

Codes are distributed to the four processors by using the processor ID (PID) included in the macroblock overhead data.

Since the operations of these four processors are the same, the operation of one processor will be described. Even if the number of processors is small in other methods, the operation of each processor is the same.

Since the bit stream in the normal state is the bit stream of the macro blocks shown in FIGS. 26 and 27, the macro block address at the head of the macro picture layer, that is, the macro slice layer is used to
By setting the projection start position, and then using the processor ID,
Addresses for normal reproduction are sequentially generated.

FIG. 31 is a diagram showing the operation of the write address generating circuit 121a during normal reproduction. First, an overhead data detection circuit 111 detects the macroblock address at the head of the macro slice layer, and the connection terminal 12
6 is input to the write address generation circuit 121a.

FIG. 31 shows an example of the case of the processor 1.
First, the M.D. B. Read A = 0. This M. B. A = 0 indicates the projection position of the super block at the head of the macro block of processor 0.

Since the projection position of the super block at the head of the macro block of the processor PID is expressed by the following expression, when the processor PID = 1, the head super block address of the macro block is 660 as shown in the following expression.
Becomes

S. B. A = M. B. A + 660 × PID = 0 + 660 × 1 = 660 During normal reproduction, first, as indicated by an arrow in FIG. B. A = 66
From 0, 720, ..., 1260, 11 super blocks are processed, and one macro block is processed in the vertical direction.
That is, S. B. After A = 1260, S. B. A =
, 1261 are processed.

Next, the read address generation circuit 121g
Reads out the luminance signal Y and the color signals U and V according to the scanning line order of the TV.

The frame delay circuit 121 and the memory write / read address generation circuits 121a and 121g also function as the deblocking circuit 120.

Chapter 29 Skip When a coded super block is exactly the same as a predicted super block, it is said that no data of this coded super block layer is sent and this is skipped. The bitstream structure at this time is described in Chapter 17, Section 17.1, Figure 2.
As described in the macroblock bitstream structure of No. 6, the trick quantization level is set to TQL _n = 31 (n is a superblock number), the corresponding variable length code is skipped, and the process goes to the next superblock. That is, no valid data is generated in the corresponding super block.
Here, TQL = 31 will be called a skip code. As another method of constructing a bit stream for expressing skip, EOB (End of Block) may be inserted at the position of the variable length code of the corresponding super block.

29.1 Circuit Operation During Skip Circuit operation during skip will be described with reference to FIGS. 28 and 30. The overhead data detection circuit 111 detects the skip code in the bitstream structure (FIG. 26), and the skip signal is output from the connection terminal 126 to the skip control circuit 135.
To enter. The skip control circuit 135 causes the frame delay circuit (memory) 121, the deblocking circuit 120, the switch 136, and the switch 141 to generate necessary skip control signals.

Switch 136 and switch 1 of FIG.
Reference numeral 41 shows the operation concept at the time of skip. At the time of skip, since there is no valid data in the bit stream, the output signal of the adder circuit 117 is not used. That is, the switch 136 is in the open state, and writing to the frame delay circuit (memory) 121 is not performed. Further, since it is the same as the image data of the prediction super block at the time of skip, the image data stored in the frame delay circuit (memory) 121 is read to output the video signal to the output terminals 123 to 125. That is, the switch 141 is in the on state.

In the non-skip mode, the write operation to the frame delay circuit 121 is performed in the same manner as the operation described in Chapter 25 Decoder Basic Configuration, Chapter 28 Frame Delay Circuit.

29.2 Operation Example During Skipping A specific example of the operation of the frame delay circuit (memory) 121 during skipping will be described with reference to FIGS. 30 and 32. In the bit stream (FIG. 26), an example will be described in which the variable length code of the refresh block exists in super block 0 and the variable length code does not exist in super block 1 to super block 10. Trick quantization level TQ
L ₀ represents a variable length code of the refresh block, and trick quantization levels TQL _{1 to} TQL ₁₀ are 31 representing skip. The operation of the write address generation circuit 121a at the time of skip will be described with reference to FIG. The write address generation circuit 121a in the frame delay circuit 121 of the decoder firstly performs the trick quantization level TQL in the macroblock bitstream of FIG.
Confirm that _{1 to} TQL ₁₀ are all in the skip state. As a result, as shown in FIG. 32, the super blocks 1 to 10 in the macro block are
Recognize that it is a skip. Since skip means that writing to the frame memories 121d, 121e, 121f is not performed, no address is generated in the skip portion. That is, as a result, the address is generated only in the portion where the refresh block exists, so that the address is generated in the vertical direction. Di in Figure 32
The case of giCipher is shown.

In the case of DigiCipher, as shown in FIG. 3A, since one processor is inevitably provided with refresh blocks arranged in the vertical direction, the write address generation circuit 121a consequently has vertical lines. The super block address is generated in the direction. That is, S. B. A: 6
The super block addresses are generated in the order of 00, 301, ..., 658, 659.

Next, the read address generating circuit 121g
Reads out the luminance signal Y and the color signals U and V according to the scanning line order of the TV. The frame delay circuit 12
1. Memory write / read address generation circuit 121
a and 121g also serve as the operation of the deblocking circuit 120. When the above frame memory writing and reading are performed, the read address is set in the scanning line order in the horizontal direction, and in the writing, it is written in the vertical direction.

Chapter 30 Inter-frame Band-compressed Signal Switching Circuit When transmitting the inter-frame band-compressed signal described above to a broadcasting or CATV (cable television) transmission line or recording it on a VTR, a plurality of inter-frame band-compressed signals are transmitted. There are possible uses for switching. In this case, a switching circuit for switching a plurality of inter-frame band compression signals and outputting one inter-frame band compression signal is required. This inter-frame band compression signal switching circuit can be divided into three types according to the application.

FIG. 33 is a diagram showing these three types of switching circuits, and the outline of these three types will be described below.

Case I FIG. 33A shows a case where two types of inputs and outputs of the switching circuit have the same rate.

Case II In FIG. 33B, two types of inputs of the switching circuit have the same rate, and the output of the switching circuit has a rate different from that of the input.

Case III FIG. 33C shows the case where the input rates of the two types of inputs of the switching circuit are different.

Next, the band compression encoder of FIG. 33 will be described in detail. 33 (a) to 33 (c), the same circuit and the same terminal are denoted by the same reference numerals. In FIG. 33, video signals having different contents are input to the input terminals 201 and 204. The video signal input from the input terminal 201 is passed through the inter-frame band compression encoder A202, and the compressed signal A is obtained at the connection terminal 203. Further, the video signal input from the input terminal 204 is passed through the inter-frame band compression encoder B205, and the compressed signal B is connected to the connection terminal 20.
Get from 6.

Here, the video signals of the input terminals 201 and 204 correspond to the signals of the video input terminals 27 to 29 of FIG. 1, the inter-frame band compression encoders 202 and 205 correspond to the circuit of FIG. 1, and the connection terminal 203. , 206 compressed signals A and B
Corresponds to the compressed signal at the output terminal 8 of FIG. The signal at the output terminal 8 has the structure shown in FIG. 42 of the conventional example, and the video signal inside this has the structure shown in FIGS. Also, the connection terminals 203 and 206
Have the same transmission rate and are, for example, 15 Mbps.

In FIG. 33C, the inter-frame band compression encoder B'207 corresponds to the circuit of FIG. 1, but the transmission rate of the compressed signal B'at the connection terminal 208 is higher than the transmission rate at the connection terminal 203. Has become. However, the signal formats correspond to those in FIGS. 10, 26, and 27.

The output signal of the inter-frame band compression encoder or the signal of the same format as this output signal is input to the band compression signal switching circuit. Here, an example of signals of the same format is shown below.

1. A signal obtained by subjecting a band compression encoder signal to error correction encoding processing, demodulation and error correction decoding after being subjected to modulation such as QAM broadcasting or transmission via a cable.

2. Error correction encoding is applied to the band compression signal, and digital modulation (8-12, 8) for recording media is performed.
-13, 8-14 modulation, etc.), recorded on a recording medium (disk, tape), etc., and subjected to digital demodulation and error correction decoding processing during reproduction.

Further, in FIG. 33, the inter-frame band compression encoder A202 may correspond to the broadcast wave, and the inter-frame band compression encoder B205 may correspond to the recording / reproducing apparatus.

Next, input / output signals of the band compression signal switching circuit will be described. Note that the band compression signal switching circuits 212, 214, and 218 in FIG.
The part indicated by the dotted line in the figure indicates that some kind of circuit is inserted.

Case I: Case of Same Input / Output Rate FIG. 33A shows the input / output of the band compression signal switching circuit 212 of the same rate. Terminals 210, 211, 2
Data of 13 has the same rate, for example, data of 15 Mbps can be input and output.

Case II: Same Input Rate, High or Low Output Rate FIG. 33 (b) shows input / output at the same input / output rate but different output rates. The terminals 210 and 211 have the same rate, for example, 15 Mbps, The terminal 215 has a different output rate, for example, 100 Mbps.

Case III: Different Input Rate and Different Output Rate Terminal 210 shown in FIG. 33 (c) is 15 Mbps, terminal 2 is
17 is 30 Mbps, and the terminal 219 is 30 Mbps.

Further, the band compression decoder of FIG. 33 will be described in detail.

The inter-frame band compression decoder 221 of FIG. 33 (a) is a decoder similar to the decoder described in Chapter 25 and FIG. 28.

Here, the terminal 220 outputs a signal having the same rate as that of the inter-frame band compression encoders 202 and 205, for example, 1
A signal of 5 Mbps is input.

A signal matching the output rate of the band compression signal switching circuit 214 is input to the terminal 223 of the partial circuit 225 of the inter-frame band compression decoder of FIG. 33 (b). Further, a necessary control signal is input using the terminal 224.

The partial circuit 228 of the inter-frame band compression decoder of FIG. 33C is the same decoder as the decoder described in Chapter 25 and FIG. 28, but only the transmission rate is the band compression signal switching circuit. Unlike the input of 218, it is set to 20 Mbps, for example.

Chapter 31 Switching Circuit Basic Configuration FIG. 34 is a diagram showing the most basic configuration of an inter-frame band compression signal switching circuit. In the figure, the terminal 21
Reference numerals 0 and 211 or 217 are input terminals for the band compression signal described in FIG. Further, the terminal 209 is used by the user for the band compression signal switching circuit 212, 214 or 21.
8 is a terminal for inputting a switching request. Also, the terminal 21
3 or 215 or 219 is an output terminal of the inter-frame band compression signal switching circuit shown in FIG.

The basic components of the inter-frame band compression signal switching circuit are the A overhead data detection circuit 23.
1, A memory 233, A write / read control circuit 23
4, B overhead data detection circuit 241, B memory 2
43, a B write / read control circuit 244, a switch switching control circuit 250, and a switch 252.

There are the following two items as basic items of the inter-frame band compression signal switching circuit.

1. When the input A is switched to the B, the refresh signal of the B signal (in-frame image) is switched.

2. When a periodic synchronizing signal is inserted in the transmission data, the synchronizing signal is phased.

Details are described in the following sections.

31.1 Refresh Frame Switching FIG. 35 shows an inter-frame band compression signal switching circuit 212.
It is a figure which shows the most basic operation | movement of (214,218). FIG. 35 is a drawing similar to FIG. 10, in which the horizontal axis shows the frame number and the vertical axis shows the position of the super block in one screen shown in FIG. FIG. 35A shows a terminal 210.
The band-compressed input signal A of FIG.
32 (c) shows the band-compressed input signal B of (217), and FIG. 32 (c) shows the output signal C of the terminals 213 (215, 219).

Here, the black-colored portion indicates refresh in which the intra-frame processing is forcibly performed.
In the examples of (a) and (b), the entire area of one screen is refreshed periodically (this refresh is based on the MPEG refresh described in Chapter 5, Section 5.2).

Generally, the band-compressed signals A and B are asynchronous, so the frames to be refreshed are different. When the frame number is represented by F _n , in the example of FIG. 35 (a), refreshing is inserted at 11-frame intervals with frames F ₁ , F ₁₂ , F ₂₃ , and F ₃₄ , and in the example of FIG. 35 (b), F _{9 is used.} , F ₂₀ , F ₃₁ frames are refreshed at 11-frame intervals. Generally, the frames to be refreshed in this way are different.

Here, it is assumed that the user inputs a switching request signal for switching the band compression signals A to B from the terminal 209 at F ₁₇ in FIG. This timing is indicated by the arrow 209 in FIG. The switching circuit output C at this time is shown in FIG. The switching point of the output signal C from A to B is 255
Set to F ₂₀ shown in. This is synchronized with the point of time 256 when the first in-frame processing of the B signal is performed after the user's switching request.

The point when switching from the inter-frame band compression signal A to B is that after the user switching signal, B
Switching the first refresh signal of the signals as a starting point.

That is, to explain with reference to FIG. 35 (c), instead of switching as it is at the switching designation point 209 of the user, it is inputted from the input A at F ₂₀ which is the refresh frame of the band compression signal B in FIG. 35 (b). Switch to B.

31.2 Input signal synchronization When performing inter-frame band compression, the generated code amount per frame is different. Therefore, the two band compression signals A and B cannot be synchronized because the signs of frame switching are different. Therefore, the synchronization signal that is inserted is synchronized independently of this frame switching point.

As described in FIG. 42 of the conventional example, DigiCiph
In the er system, the synchronization (SYNC) signal is inserted in the first line of the transmission signal. The sync signal is periodically inserted in synchronization with the frame rate of the input video signal. It should be noted that the switching of frames of the inter-frame band compression signal is indicated by NMP.

It is necessary that the band compression signals A and B be in phase with each other for this synchronization (SYNC) signal. NM
The switching point of the frame indicated by P is not synchronized between the A signal and the B signal.

31.3 Operation of Switching Circuit Basic Configuration The circuit of FIG. 34 performs the following operations in order to realize the requirements of Sections 31.1 and 31.2. The overhead data detection circuits 231 and 241 detect the synchronization signal of the transmission signal of FIG. 42 and write / read control circuits 234 and 24.
4 through terminals 232 and 242. The write / read control circuits 234 and 244 perform control for setting and outputting respective delay times in the memories 233 and 243 so that the synchronization signals of the band compression signals A and B are synchronized.

The band compression signal A input from the terminal 210 is stored in the A memory 233, and the overhead data detection circuit 231 detects the refreshed frame. To explain with reference to FIG. 35A, F ₁ , F ₁₂ , F ₂₃
(In MPEG.I, a code indicating an I picture, which is a refresh frame, is inserted in the overhead data, so a refresh frame can be detected by detecting the code of this I picture).

Similarly, the band compression signal B from the terminal 211 is stored in the B memory 243. The B overhead data detection circuit 241 detects the refreshed frame. In the example of FIG. 35B, F ₉ , F ₂₀ , and F ₃₁ are detected.

The switch changeover control circuit 250 has the terminal 20
The user switching signal A / B set by the user is input from 9. Further, the refresh frame of the A signal is input from the terminal 232, and the refresh frame of the B signal is input from the terminal 211.

As a result, when switching from the signal A to the signal B as described with reference to FIG. 35, the switch switching control circuit 250 switches the switch 252 so as to start from the refresh frame of the signal B. Further, the switch setting control circuit 250 inputs the switching setting frame to the A and B write / read control circuits 234 and 244, and the read end point of the A memory 233 and the B memory 24.
The read start point of No. 3 is determined, and the memory read control process is performed.

Since the frame rate of the video output signal of the terminal 222 (226, 229) needs to be a predetermined value, one frame before the start frame of the B signal is the last frame of the A signal as shown in FIG. Becomes Specifically, B
If the signal starts at F _20, the last frame of the A signal is F
_Then , the frame image of F ₁₉ is output and the A signal ends.

The overhead data detection circuit 23
If it is necessary to detect a start code to detect an I picture or a code indicating a refresh area (referred to as frame count in the DigiCipher of the above-described conventional example) at 1 and 241, this start code is used to detect overhead data. It goes without saying that the circuits 231 and 241 perform detection.

31.5 Other Embodiments Another embodiment will be described as a similar example.

The main point of this example is that when the user switches from the signal A to the signal B, the signal is switched back to the refreshed frame of the signal B.

When switching from the A signal to the B signal, the start point of the B signal is often more important than the end point of the A signal.

Therefore, at time 258 in FIG. 35, that is, F ₂₇
In the case where the switching request from the user occurs, switching from the reverse climbing A signal to F ₂₀ subjected to refresh the B signal to the B signal.

The circuit for realizing this embodiment is shown in FIG.
The memory capacities of the memory 233 and the B memory 243 may be larger than the maximum code amount generated in the refresh cycle. That is, in this example, the memories 233 and 24
The memory capacity of 3 is a value exceeding the transmission code amount for 11 frames in the refresh period.

32. Measures against rate buffer occupancy during band compression signal switching When a difference occurs between the buffer occupancy of band compression signal input A and the buffer occupancy of band compression signal input B, this measure is required. The countermeasure method differs depending on the case where the input and output transmission rates shown in FIG. 33A are the same and the case where the input and output transmission rates shown in FIG. 33B are different. The case where the input and output transmission rates of the switching circuit are the same will be described in Chapters 33 and 34.

33. Rate Buffer Countermeasure Switching Circuit (FIG. 36) As described above, when the input and output transmission rates of the switching circuit are the same, the band compression encoder and the decoder connected to the input and the output of the switching circuit are 202 and 20 of FIG.
It looks like 5,221. The internal block of the band compression signal switching circuit 212 has the configuration shown in FIG.

In FIG. 36, the terminals and blocks designated by the same numbers as those in FIGS. 33 and 34 operate in the same manner.

In the inter-frame band compression signal processing device, the generated code amount differs for each frame, and the occupancy of the rate buffer constantly changes. Therefore, it is necessary to correct the difference in the rate buffer occupancy of the two interframe band compression devices. Overhead data detection circuit 260, 263
Detects the buffer occupancy value in addition to the synchronization signal and the refreshed frame. Here, the synchronization signal and the refreshed frame refer to Chapter 31, Section 31.1-
This is the same as that described in section 31.3. The method of detecting this code is the overhead data detection circuit 23 of FIG.
It is the same as 1, 241.

To the terminals 305 and 306, the sync signal described in Chapter 31, the refreshed frame, and the buffer occupancy value other than that are output. Similar to the switch switching control circuit 250 described in Chapter 31, FIG. 34, the switch switching control circuit 264 performs phase matching of the synchronization signal and switches from the refresh signal of the B signal when switching from the input A to the input B.

Further, the switch switching control circuit 264, based on the buffer occupancy values of the inter-frame band compression signals A and B, the write / read control circuits 262 and 265, the switching overhead data generation circuit 307, and the switch 26.
6 is controlled. Details of the buffer occupancy value and the switch switching control method will be described in Chapter 34. The switching overhead data generation circuit 307 generates transient state overhead data in the transitional state of switching from the interframe band compression signal A to B. There are the following two types of transient state overhead data.

1. Dummy data for setting the bit stream at a constant rate This is dummy data to be inserted to match the transmission data rate when the generated code amount of the video signal is small.
DigiCipher calls it Fill Bits. In addition, MPEG. In I, macroblock stuffing (mc
roblock stuffing) and the pattern is "000
It is an 11-bit code of 0 0001 111 "and is used for the purpose of preventing buffer underflow. The decoder ignores this code.

2. Skip Code The DigiCipher skip code has been explained in Chapter 29 Skip and Chapter 13 Bitstream. MPEG. I
Two types of methods can be used to represent this skip in the bit stream of. (1) A method of designating the slice vertical position with a slice start code, (2) Indicates the difference between the address of a macroblock that was last encoded (not skipped) by macroblock address increment and the current macroblock address be able to.

Overhead data generation circuit 3 at switching
07 includes overhead data detection circuits 260 and 263.
The sync signal, the refresh signal, and the buffer occupancy value are input. Further, the switch control signal is input from the switch switching control circuit 264 from the terminal 268. Furthermore, by inputting the switching timing signal from the terminal 267,
Generates overhead data when switching. The overhead data at the time of switching includes dummy data and a skip code, and a method of generating this will be described later.

Next, the switch 266 switches the output of the A memory 233, the B memory 243, and the switching overhead data generating circuit 307, and outputs the output from the terminal 213.

Chapter 34 Operation of Rate Buffer Countermeasure Switching Circuit The operation of the rate buffer countermeasure switch circuit (FIG. 36) will be described with reference to FIGS. 35 and 37 to 39. FIG. 37 and FIG. 38 are diagrams showing a code transmission state when switching between two band compression signals A / B. In the figure, the horizontal axis represents the frame number. Note that FIG. 37A and FIG.
The upper part of the horizontal axis of 8 (a) is the frame number on the encoder side,
The lower row shows the frame number on the decoder side. Also,
The vertical axis represents the code amount (this figure is shown in FIG.
(It is a diagram in which the transmission code of (c) and the reception code of FIG. 19 (a) are combined).

A solid line 270 in the figure indicates the amount of transmission code at the terminal 213 of the band compression signal switching circuit 212.
The slope of the solid line 270 indicates the transmission rate. The upper side of the solid line 270 shows the state of the encoder, and the lower side of the solid line 270 shows the state of the decoder. Where the solid lines 272, 2
Reference numeral 74 indicates the cumulative code amount of the encoder and decoder of the band compression apparatus A, respectively, and solid lines 273 and 275 indicate the cumulative code amount of the encoder and decoder of the band compression apparatus B, respectively.

37 (b) and 38 (b) show the rate buffer 112 inside the inter-frame band compression decoder 221.
FIG. 29 is a diagram showing the degree of occupancy (see FIG. 28).
It is a figure similar to (b). 37 (c) and 38.
(C) is a diagram showing a projection code amount at the time of video output in the decoder. In the figure, black portions correspond to refresh frames. Further, FIG. 37 (c) is shown in FIG.
38 (c) corresponds to FIG. 39 (c), and FIG. 35 (a), (b), FIG. 39 (a),
FIG. 35B shows the processing contents of the two input signals A and B, and FIGS. 35C and 39C show the video output contents at the decoder.

The occupancy of the rate buffer inside the decoder is the solid line 2 in FIGS. 37 (b) and 38 (b).
76 and 277.

This corresponds to the difference between the solid line 274 and the solid line 270 and the difference between the solid line 275 and the solid line 270 in FIGS. 37 (a) and 38 (a). Further, as described in Chapter 10, Code amount control, Section 10.1 Macroblock code amount control, the occupancy of the rate buffers of the decoder and the encoder has an inverted relationship. Therefore, assuming that the difference between the broken line 278 and the solid line 270 is the capacity value of the rate buffer of the encoder, the occupancy of the rate buffer inside the decoder is the solid line 27.
2 and the broken line 278 and the solid line 273 and the broken line 278.

The rate buffer countermeasure switching circuit of FIG. 36 operates in the next step as shown in FIG. Needless to say, when the periodic synchronizing signal is inserted as described in Chapter 31, there is a step of combining the synchronizing signals.

Step 1 When switching from the A signal to the B signal as described with reference to FIGS. 34 and 36, the refresh signal (MPE) of the signal B is changed.
G. In I, it is switched to start from I picture). That is, in the case of FIG. 35 (b) and FIG. 39 (b), since the refresh frame exists in the frame number FB ₂₀ of the B signal, the refresh frame of this FB ₂₀ is switched. Here the frame number of the B signal FB _n, (n is a real number) FA _n the frame number of the A signal to be represented by. As a result, FIG. 35 (c) and FIG.
In the examples shown in (c), FIG. 38 (c) and FIG. 39 (c), the B signal starts from FB ₂₀ which is a refresh frame.

Details of this operation are described in detail in Chapter 31.

Step 2 When the start frame FB _{20 of the} signal B is determined, the rate buffer occupancy RB ₂₀ (definition will be described later) at the start point of FB ₂₀ is detected. Further, the buffer occupancy RA of the signal A
₂₀ , ..., RA _(20-imax) is detected. The buffer occupancy RA ₂₀ indicates the buffer occupancy at the time of the frame FA ₂₀ of the signal A corresponding to the start frame FB ₂₀ of the signal B. RA ₁₉ , ......, RA _(20-imax)
Indicates the buffer occupancy at the time of the frame before FA ₂₀ , and imax is the number of frames calculated by dividing the maximum storage code amount of the rate buffer by the transmission rate. Here, it is assumed that the rate buffer occupancy value of the A signal (this is the value when assuming the decoder not inside the encoder) is RA _n , and the rate buffer occupancy value of the B signal is RB _n .

Here, n indicates a frame number. This value is shown in FIGS. 37 and 38. The rate buffer occupancy value is
It is inserted in the bitstream. In DigiCipher, NMP corresponds to this rate buffer occupancy value. This NMP is a synchronization signal (Vertical
-) It is located after SYNC. MPEG. For I, the video buffer delay (vbv-delay) corresponds to the rate buffer occupancy value. Video buffer delay is 1/9000
It is a 16-bit integer in units of seconds, and the delay amount corresponding to the buffer remaining amount in the picture layer is calculated by the following equation from the relationship with the bit rate.

Vbv-delay = 90000 * (buffer remaining amount / bit rate) Step 3 Rate buffer occupancy RB _{20 at} the start point of the start frame FB ₂₀ of signal B and frame number FA _{20 of} signal A
Using the rate buffer occupancy RA ₂₀ of ΔR = RA ₂₀ −R
Calculate B ₂₀ . Here, ΔR> 0, ΔR = 0, ΔR <
The operation of the inter-frame band compression signal switching circuit in FIG. 36 differs depending on the case of 0.

34.1 When outputting dummy data When ΔR> 0, the following operation is performed Step 4.1 In this case, since the rate buffer occupancy RA ₂₀ is larger than RB ₂₀ , it is shown in FIG. 37 (a). As described above, the sending timing of FB ₂₀ is later than the sending timing of FA ₂₀ . In this case, if the start frame of the B signal is determined to be FB ₂₀ , the final frame of the A signal is determined to be FA ₁₉ .

The reason for this is that the frame rate of the video signal output from the band compression decoder (221 in FIG. 33) has a predetermined value. For this frame rate, for example, 29.97 Hz has been proposed in a system of 1050 scanning lines, and is determined by the system. The inter-frame band compression signal switching circuit must be switched so that the frame rate matches. Therefore, when sending FB ₂₀ , it is not possible to send signals after FB ₂₀ .

Therefore, FA ₁₉ is switched to FB ₂₀ at the time indicated by point 280. Regarding the rate buffer occupancy of the signal A and the signal B at this time point, RA ₂₀ is point 281 and point 2
82 difference, RB ₂₀ is shown by the difference between points 283 and 281. Here, the point 282 indicates the value of the frame number 20 of the solid line 272 indicating the cumulative amount of generated code of the A signal, and the point 2
Reference numeral 83 indicates the value of the frame number 20 on the solid line 273 indicating the cumulative generated code amount of the B signal.

ΔR = RA ₂₀ −RB ₂₀ is point 282 and point 28
This corresponds to the difference of 3 and corresponds to the existence of the point 283 above the point 282 when ΔR> 0.

Step 5.1 Next, the switch switching operation of the switch switching control circuit 264 will be described with reference to FIG. The solid line 270 is shown in FIG.
Output terminal 2 of the inter-frame band compression signal switching circuit 6
13 signals. Since the transmission rates of the input and output signals are the same, it is a straight line. The solid line 270 shows the switching timing of the signal A, the dummy data, and the signal B. The timing for ending the output of the final frame FA ₁₉ of the A signal indicated by the point 282 is the intersection 284 of the dotted line drawn from the point 282 in the horizontal direction and the solid line 270. Further, the timing of starting the output of the start frame FB ₂₀ of the B signal indicated by the point 283 is the intersection 285 of the dotted line drawn from the point 283 in the horizontal direction and the solid line 270. Dummy data is generated during the period between points 284 and 285. Figure 3
7B shows the state of the rate buffer 112 inside the decoder when the signal of FIG. 37A is input to the inter-frame band compression decoder 221. The solid line 276 shows the occupancy of the rate buffer. Solid line 2 in FIG. 37 (a)
Since only the A signal is input up to the point 284 of 70, only the A signal exists up to the point 286 on the solid line 276. Since dummy data is input from the points 284 to 285 of the solid line 270, the dummy data starts increasing from the time of the point 286 to the time of the point 288 in the rate buffer. Since the B signal is input from the point 285 of the solid line 270, the B signal starts to be input from the point 289.
The dummy data is erased at the point 287 on the solid line 276, and after the point 287, only the B signal exists in the rate buffer.

FIG. 37 (c) shows the output signal of the decoder 221. The A signal is output up to frame number F _19, and the B signal is output from F _{20. The} B signal is output from the decoder with the refresh frame as the start frame. Yes (refresh frame is the black part). This output signal is shown in FIG.
It becomes like (c).

34.2 When outputting a skip code When ΔR <0, the following operation is performed.

Step 4.2 Since RA ₂₀ is smaller than the rate buffer occupancy RB _{20 in} this case, the end frame of the A signal is not set before FA ₂₀ in order to output it from the refresh frame FB ₂₀ of the B signal. must not. Explaining with reference to FIG. 38A, the cumulative code amount of FA ₂₀ of the A signal is represented by a point 291 and the rate buffer occupancy RA ₂₀ is represented by the difference between the points 291 and 292. The cumulative code amount of FB ₂₀ of the B signal is point 29.
The rate buffer occupancy RB ₂₀ is represented by a point 290.
And the point 292. Since the point 291 exists above the point 290, in order to output the B signal from the FB ₂₀ , the end frame of the A signal must be set before FA ₁₉ .

The output timing of the start frame of the signal A is the intersection 29 of the dotted line drawn horizontally from the point 290 and the solid line 270.
Output from point 3. Therefore, the A signal must end the output at the point 293. So point 293
The A signal must be terminated at the frame of the intersection 294 between the dotted line drawn horizontally from the point 290 and the accumulated code amount 272 of the A signal.

If the frame number of the point 294 is FA _(20-i) , the rate buffer occupancy RA _(20-i) and RB at this time are
Assuming that the output data rate per frame of ₂₀ and the solid line 270 is γ, the A signal is output up to the frame number FA _(20-i) where RA _(20-i) = RB ₂₀ -γ · i.

Step 5.2 The switch switching operation of the switch switching control circuit 264 is shown in FIG.
This will be described using 8 (a). The A signal is output up to a point 293 on the solid line 270. The final frame of the A signal at this time is an FA that satisfies RA _(20-i) ≧ RB ₂₀ −γ · i described above.
_(20-i) . In this example, after the point 293, which is FA ₁₅ , the refresh frame FB ₂₀ of the B signal is output as the start frame. FIG. 38B shows the state of the rate buffer 112 when the signal of FIG. 38A is input to the decoder 221. A solid line 277 shows the occupancy of the rate buffer.

Since the A signal is input up to the point 293 on the solid line 270, only the A signal exists up to the point 296 in FIG. 38B, and the B signal exists in the rate buffer after the point 296. At 297, the A signal disappears and only the B signal exists.

FIG. 38 (c) shows the output signal of the decoder 221, which is the A signal up to frame number F ₁₅ , and F ₁₆ to.
F ₁₉ outputs the image in which F ₁₅ is held, and the B signal is output from F _20, and the B signal is output from the decoder with the refresh frame as the start frame (the black portion is the refresh frame). This output signal is as shown in FIG.

34.3 When ΔR = 0 Step 5.3 When ΔR = 0, the A signal is output to FA ₁₉ and the B signal is output from FB ₂₀ .

The present invention is not limited to the above embodiments, but can be variously modified and implemented without departing from the scope of the invention.

[0299]

As described above, according to the present invention, a high quality switching image can be obtained when switching a plurality of inter-frame band compression signals.

[Brief description of drawings]

FIG. 1 is a block diagram showing an embodiment of an inter-frame band compression signal switching circuit according to the present invention.

FIG. 2 is a diagram shown for explaining a pixel region in the embodiment.

FIG. 3 is a diagram shown for explaining refreshing of the embodiment.

FIG. 4 is a diagram shown for explaining refreshing of the embodiment.

FIG. 5 is a diagram shown for explaining a super block address in the embodiment.

FIG. 6 is a block configuration diagram showing details of an intra-frame / inter-frame determination circuit in the embodiment.

FIG. 7 is a diagram for explaining intra-frame / inter-frame determination characteristics according to the embodiment.

FIG. 8 is a diagram shown for explaining forced refresh in the embodiment.

FIG. 9 is a diagram for explaining forced refresh per processor in the embodiment.

FIG. 10 is a diagram for explaining MPEG refresh in the embodiment.

FIG. 11 is a diagram showing a scan order when a DCT coefficient is zigzag scanned.

FIG. 12 is a diagram showing an example of a quantization table.

FIG. 13 is a diagram showing an example of a weighting table.

FIG. 14 is a diagram showing an example in which the same weighting table is converted into the number of bits.

FIG. 15 is a diagram showing the number of generated bits according to a quantization table.

FIG. 16 is a diagram showing the number of generated bits based on a quantization table.

FIG. 17 is a diagram showing a configuration of a rate buffer.

FIG. 18 is a diagram showing the operation of a rate buffer on the encoder side.

FIG. 19 is a diagram showing the operation of the rate buffer on the decoder side.

FIG. 20 is a diagram showing increase / decrease in buffer occupancy and quantization level.

FIG. 21 is a block configuration diagram showing details of a quantization level setting circuit of the same embodiment.

FIG. 22 is a diagram showing a generated code amount when variable length coding is performed.

FIG. 23 is a diagram showing the relationship between DCT coefficient energy and corrected quantization level.

FIG. 24 is a diagram showing macroblocks and (non-) refresh blocks.

FIG. 25 is a diagram for explaining a macroblock address.

FIG. 26 is a diagram shown for explaining a bitstream structure of a macroblock.

27 is a macro slice layer, picture layer, G. O. P
The figure which shows the structure of a layer.

FIG. 28 is a block diagram showing an embodiment of the decoder side of the present invention.

FIG. 29 is a diagram showing a relationship between an index and overhead data and each circuit.

FIG. 30 is a block diagram showing details of a frame delay circuit.

FIG. 31 is a diagram shown for explaining the normal operation of the frame delay circuit.

FIG. 32 is a diagram shown for explaining an example of an operation at the time of skipping of the frame delay circuit.

FIG. 33 is a diagram showing an application of an inter-frame band compression signal switching circuit.

FIG. 34 is a first circuit diagram of an inter-frame band compression signal switching circuit.
FIG.

FIG. 35 is a diagram showing a switching operation of an inter-frame band compression signal switching circuit.

[FIG. 36] A second inter-frame band compression signal switching circuit
FIG.

[FIG. 37] A third inter-frame band compression signal switching circuit
The figure which shows the generated code amount of the Example of FIG.

[FIG. 38] A fourth inter-frame band compression signal switching circuit
The figure which shows the generated code amount of the Example of FIG.

FIG. 39 is a diagram showing a switching operation of an inter-frame band compression signal switching circuit.

FIG. 40 is a diagram showing the operation of the inter-frame band compression signal switching circuit.

FIG. 41 is a block diagram showing a conventional band compression system.

FIG. 42 is a diagram showing a format of a signal transmitted from the conventional system.

FIG. 43 is a diagram showing refreshable refresh blocks of frames 1 to 8 during normal reproduction in the conventional system.

FIG. 44 is a diagram showing refreshable blocks that can be reproduced in frames 9 to 11 and refresh blocks that have accumulated 11 frames during normal reproduction in the conventional system.

FIG. 45 is a diagram showing a track pattern in the conventional system.

[Explanation of symbols]

11 ... Input terminal, 12 ... Subtraction circuit, 13 ... Motion evaluation circuit, 14 ... DCT circuit, 15 ... Quantization circuit, 16 ... Variable length coding circuit, 17 ... FIFO circuit, 18 ... Output terminal,
19 ... Inverse quantization circuit, 20 ... Inverse DCT circuit, 21 ... Addition circuit, 22 ... Frame delay circuit, 23 ... Motion compensation circuit,
24, 25 ... Switch, 26 ... Magnetic tape, 27-29
... video input terminal, 30 ... blocking circuit, 31 ... intra-frame / interval determining circuit, 32, 33 ... input terminals, 34, 35
Output terminal, 36 ... Energy comparison circuit, 37 ... Subtraction circuit, 38 ... Addition circuit, 39 ... Refresh timing generation circuit, 53 ... Quantization level setting circuit, 54 ... Super block code amount calculation circuit, 55 ... Macro block code amount Calculation circuit, 56 ... Transmission code amount ROM, 57 ... Rate buffer code amount calculation circuit, 58 ... Macro block quantization level setting circuit, 60 ... Super block quantization level setting circuit, 61, 62 ... Input terminal, 63 ... DCT coefficient Energy calculation circuit, 64 ... Addition circuit, 67 ... Overhead data generation circuit, 68 ... Output terminal, 111 ... Overhead data generation circuit, 112 ... Rate buffer, 114
... variable length code decoding circuit, 115 ... inverse DCT circuit, 116
... inverse quantization circuit 117 ... adding circuit, 118 ... switch, 119 ... in-frame / inter-frame switching circuit, 120 ... deblocking circuit, 121 ... frame delay circuit, 122 ...
Motion compensation circuit, 123 to 125 ... Output terminal, 126 ... Connection terminal, 127 ... Input terminal, 135 ... Skip control circuit, 136, 141 ... Switch, 201 ... Input terminal, 2
02 ... inter-frame band compression encoder A, 203 ... connection terminal, 204 ... input terminal, 205 ... inter-frame band compression encoder B, 206 ... connection terminal, 207 ... inter-frame band compression encoder B ′, 208 ... connection terminal, 209 ...
211, 213, 215 to 217, 219, 220 ... Terminals, 221 ... Inter-frame band compression decoder, 223, 2
24 ... Terminal, 225 ... Partial circuit, 231 ... A overhead data detection circuit, 232 ... Terminal, 233 ... A memory, 234 ... A write / read control circuit, 241 ... B
Overhead data detection circuit, 242 ... Terminal, 243
... B memory, 244 ... B write / read control circuit, 2
50 ... Switch switching control circuit, 252 ... Switch, 26
0 ... Overhead data detection circuit, 262 ... Write / read control circuit, 263 ... Overhead data detection circuit, 264 ... Switch switching control circuit, 265 ... Write / read control circuit, 266 ... Switch, 267, 26
8 ... Terminal, 305, 306 ... Terminal, 307 ... Overhead data generation circuit.

Claims (5)

[Claims] 1. A circuit for switching between two band-compressed signals having a periodic synchronization signal inserted independently of a code boundary of each frame into an inter-frame band-compressed signal whose generated code amount changes for each frame, An inter-frame band compression signal switching circuit configured to generate a switching output by matching the phases of periodic synchronization signals of two band compression signals. 2. Two inter-frame band compression signals A and B having refresh processing for periodically performing intra-frame processing.
In the circuit for switching from the signal A to the signal B, the circuit has a memory for storing the maximum generated code amount in the refresh processing period, and when the switching request signal is generated, the signal B is read using the refresh signal of the signal B as a starting point. An inter-frame band compression signal switching circuit having the above-mentioned configuration. 3. Two inter-frame band compression signals A and B having refresh processing for periodically performing intra-frame processing.
In the circuit for switching from the signal A to the signal B, having a memory for storing the maximum generated code amount in the refresh processing period, and for switching the signal B from the refresh signal of the signal B when the switching request signal is generated. And a circuit for generating signal switching overhead data, the inter-frame band compression signal switching circuit. 4. A circuit for switching two inter-frame band compression signals A and B having refresh processing for periodically performing in-frame processing to all areas of one screen from a signal A to a signal B in a refresh processing period. A circuit having a memory for storing the maximum generated code amount, which reads the signal B from the refresh signal of the signal B when the switching request signal is generated, and the rate buffer occupancy RBn (n is the signal B of the signal B at the refresh time). (The frame number of which the refresh has been performed on) and the buffer occupancy RAn of the signal A for the frame on which the signal B has been refreshed, ΔR = RAn−RBn is defined, and when ΔR> 0, the signal A to the signal B The inter-frame band compression signal switching is characterized in that it is configured to generate a maximum ΔR dummy signal when switching to Replacement circuit. 5. A circuit for switching two inter-frame band compression signals A and B having refresh processing for periodically performing in-frame processing to all areas of one screen from a signal A to a signal B in a refresh processing period. A circuit having a memory for storing the maximum generated code amount, which reads the signal B from the refresh signal of the signal B when the switching request signal is generated, and the rate buffer occupancy RBn (n is the signal B of the signal B at the refresh time). (The frame number of which the frame is refreshed) and the buffer occupancy RAn of the signal A for the frame where the signal B is refreshed are defined as ΔR = RAn−RBn, and when RAn <RBn, that is, ΔR <0, RA (N−i) ≧ RBn−r · i (r is the output rate per frame, and n−i of RA (n−i) is the signal A frame Detecting the n-i which is a real number) at beam number, the frame number n-i the signal A as the output signal of the switching circuit, the signal B
Is an inter-frame band compression signal switching circuit, which is configured to output a skip signal during a period from frame number n to frame numbers ni to n.