JP2820630B2 - Image decoding device - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an image decoding apparatus for decoding an encoded image signal.

[0002]

2. Description of the Related Art When transmitting or storing digitally expressed image data, encoding is performed to reduce the amount of data. As a coding method, there is a method of reducing redundancy by utilizing temporal or spatial correlation of image information.

As a method utilizing the temporal correlation, there are methods of encoding a difference between two consecutive screens (frames) and detecting motion of an image to perform motion compensation.
As a method using spatial correlation, an image is divided into blocks of a predetermined size (for example, 8 pixels each in the vertical direction and the horizontal direction), data in the blocks are orthogonally transformed, and transform coefficients are scan-converted. Some (for example, rearrange from low-frequency components to high-frequency components) and perform variable-length codes. An image coding method (hereinafter abbreviated as MPEG2), which is being standardized by the Moving Picture Experts Group (MPEG), uses both of the above two methods.
The provisional recommendation for MPEG2 is “Generic Coding of Moving P
ISO / IE entitled “ictures and Associated Audio”
C13818-2.

FIG. 5 shows an example of the configuration of an image decoding apparatus for decoding data encoded by such a method. In FIG. 5, reference numeral 30 denotes a memory storage unit, which comprises a buffer memory control unit 31 and a buffer memory 32. Decoding means 40 includes a variable length decoder 41, a scan converter 42, an inverse quantizer 43, an inverse DCT unit 44, a motion compensation image reproducing unit 45, and a frame memory 46. Reference numeral 100 denotes an input bit stream representing an encoded image, and reference numeral 200 denotes a reproduced image.

Next, the operation will be described. The input bit stream 100 is stored in the buffer memory 32 under the control of the buffer memory control unit 31. The data read from the buffer memory 32 is subjected to variable length decoding by the variable length decoder 41.

Although not all data is variable-length coded, fixed-length codes are also decoded by the variable-length decoder 41. Next, the order of the data is rearranged by the scan converter 42 and then inversely quantized by the inverse quantizer 43. Next, the inverse DCT unit 44 performs an inverse discrete cosine transform. When the inter-frame difference is received, the motion-compensated image reproducing unit 45 stores the reference data in the frame memory 46.
, And after adding the received data, the reproduced image is written to the frame memory 46. When data encoded in the frame is received, the received data is written to the frame memory 46 as it is.

[0007] The image data decoded as described above is read out, and the frame memory 46 is read by the control reproduction image section 47.
If the decoded image is an interlaced image, the frame image is converted into a field image, and the reproduced image 2
00 is output.

Next, the structure of the MPEG2 bit stream will be briefly described. The bit stream has a hierarchical structure, and the highest-order structure of the bit stream of the encoded image is called a video sequence.

FIG. 6 shows the high-level structure of a video sequence. A video sequence starts with a sequence header (sequence header) and ends with a sequence end (sequence).
quence end). If there is a sequence extension immediately after the sequence header, it is an MPEG2 bit stream.
It is a bit stream of EG1 (ISO / IEC117172-2). Then, a sequence header is inserted for a plurality of picture data. Note that * indicates an option.

[0010]

When a plurality of video sequences are transmitted and one of them is selected for decoding,
When the video sequence is switched, decoding cannot be performed until a sequence header appears in the bit stream, and the display cannot be displayed on the display during that time. In digital TV, this is a problem called channel hopping.

SUMMARY OF THE INVENTION The present invention has been made to solve the above-mentioned problem, and has as its object to provide an image decoding apparatus in which the decoding start time after channel switching is shortened.

[0012]

An image decoding apparatus according to the present invention has a table storing data necessary for decoding for each video sequence.

The MPEG2 decoder has a table for storing the contents of a sequence header and a sequence extension for each assumed video sequence.

The table stores information necessary for decoding obtained by previous decoding.

Although the code for designating the start of decoding is determined in the grammatical structure of the bit stream, other start codes have means for controlling the start of decoding.

A digital TV decoding apparatus using MPEG2 has a table storing a sequence header and a sequence extension for each sequence, that is, for each channel.

[0017]

In the present invention, since data necessary for decoding is prepared in a table in advance, it is not always necessary that all data is included in the bit stream. Particularly, in the MPEG2 decoder, the data in the sequence header and the sequence extension is not necessarily required in the bit stream. Conventionally, decoding is started after a sequence header always appears in a bit stream. However, in the present invention, decoding from a group of picture header or a picture header can be started, and the decoding processing start time can be shortened. In particular, in a digital TV using MPEG2, the data in the sequence header and the sequence extension is considered to be fixed for each channel. Therefore, a table storing these data is provided. When the channel is switched, the data is stored in the table. By starting decoding from the group of picture header and the picture header using the data, the channel hopping problem is improved. Also,
The table stores information necessary for decoding obtained by previous decoding. Also, decoding can be started from the middle of the input bit stream. Further, in a system that receives a plurality of sequences, by having the data of the table for each sequence, it is possible to decode from the middle of the input bit even when switching to any sequence.

[0018]

【Example】

Embodiment 1 A first embodiment of the present invention will be described with reference to FIGS.

First, the configuration of the present invention will be described with reference to FIG.

In FIG. 1, reference numeral 10A denotes the entire image decoding apparatus, 11 denotes a selector, 12 denotes an image decoding unit, 13 denotes a display device such as a television, 14 denotes a CPU, 15A, 15B, 1
5C is a table (use 15 to show the whole),
A, B, and C represent video sequences.

As an input, a plurality of video sequences are input from a plurality of transmission paths. In FIG. 1, video sequences A, B, and C are input from three transmission paths. One of the plurality of video sequences is selected by the selector 11. The selection is controlled by an input selection signal from the CPU 14. The CPU 14 outputs an input selection signal of the selector 11 and, at the same time, selects a table containing information of a video sequence to be selected from among a plurality of tables 15 containing information necessary for decoding an image. Output a signal. Upon receiving the table selection signal, the table 15 starts outputting the stored information (initial setting data) to the image decoding unit 12. At the same timing, the CPU 14 transmits a load signal to the image decoding unit 12 and instructs the image decoding unit 12 to receive the initial setting data.

Next, the operation of the image decoding apparatus 10A will be described with reference to FIG. Note that (1) to ( 7 ) in the figure indicate each step.

The image decoding unit 12 knows that the video sequence has been switched by the load signal, terminates the decoding of the current video sequence, receives the initial setting data from the table 15, and performs various necessary decoding based on the initial setting data. The value of the parameter is updated (1), and the start code prefix (start_code_pre
fix) is detected (2). When the start code prefix is detected, the subsequent start code is extracted (3). At this time, the sequence header and sequence extension (Sequence Extenti
on), Extension & User
er), Group of Pictures header
res Header), picture header (Picture Header) decode (decoding) the beginning to the bit stream on the basis of the detected predetermined start encoding any of (4), Sequence
When the end is reached (7), the process ends . Further, vbv delay the timing of decoding: if controlled by (vbv_delay. Accumulated amount of virtual input buffer encoders decoder is indicated by time 90KH z clock), because they are needed the information of the picture header, picture header Picture Coding Extension (Picture Coding Ext)
Encoding) and decoding from a slice header including picture data (Picture Data) are not realistic, so the next start code prefix is detected (5). Also, if a sequence end-code is received, a predetermined decoding end processing is performed (6). Conventionally, decoding has not been started until a start code representing a sequence header appears.

With the above operation, the decoding start time immediately after switching the video sequence can be advanced.

Although FIG. 1 shows a case where a plurality of transmission paths are used, it is needless to say that the present invention can be applied to a case where a plurality of sequences are multiplexed on a single transmission path. [Embodiment 2] The configuration of a second embodiment of the present invention will be described with reference to FIG.

In FIG. 3, 10B shows the entire image decoding apparatus, 16 is an antenna, 17 is a tuner, 18A, 1
8B are tables (generally referred to as 18), and 12 to 14 are the same as those in FIG.

In this embodiment, it is assumed that a bit stream compressed by MPEG2 is broadcast and received. In the figure, the antenna 16 has an input bit stream 100
Means the transmission path through which the message is sent. In terrestrial broadcasting and BS broadcasting, reception is performed by the antenna 16, but in CATV, it means a cable. The tuner 17 is a means for selecting one channel from a plurality of channels (or programs) and extracting it as an input bit stream 100. It also includes descrambling and error correction. Image decoding unit 12
Is a means for decoding an MPEG2 bit stream and outputting it to a display device 13 such as a TV. The CPU 14 is a means for instructing selection of a channel and controlling the image decoding unit 12. The table 18 stores the sequence header of each channel and the parameters of the sequence extension, and is composed of a ROM or the like. The parameters of the sequence header and the sequence extension represent the size of the image, the bit rate, etc.
It is considered that it is constant for each channel and does not change.

Next, the operation of the embodiment of FIG. 3 will be described with reference to FIG.

In FIG. 4, T1 indicates a channel switching occurrence point, T2 indicates a decoding start point according to the present embodiment, and T3 indicates a decoding start point according to the conventional example. T1 'indicates the end point of loading of initial parameters necessary for decoding.

The CPU 14 is provided with a user by means not shown.
The want to switch the channel, and know that will occur say, sends a channel selection signal to tuners 1 7,
The channel is switched (T1). Tuner 1 7 in accordance with the channel selection signal, and outputs extracts an input bit stream 100 in the specified channel.

The CPU 14 outputs a channel selection signal during the parameter load period shown in FIG. 4, and at the same time, outputs a table selection signal to select a table 18 storing data of a specified channel. Further, a signal instructing the image decoding unit 12 to load the contents of the table 18 is sent, and the image decoding unit 12 replaces the value of each parameter with the contents of the table 18 (T1 ′).

After the parameter replacement is completed, the image decoding unit 12 enters the monitoring state of the input bit stream 100. Decoding is started when a sequence header, a sequence extension, a group of pictures header, and a picture header are detected (T2). In FIG. 4, decoding is started from the group of pictures header. That is, decoding can be started from the middle of the input bit stream. However, decoding starts only when the picture header includes an intra picture (image not using temporal prediction) or an intra slice.

With the above operation, as shown in FIG. 4, the decoding start point T2 according to the present embodiment can advance the decoding start time after the channel switching as compared with the conventional decoding start point T3. Can be displayed on the display device 13 earlier.

The information necessary for decoding stored in the table may be either stored in advance or the information obtained by the first decoding may be stored.

[0035]

According to the present invention, as described in detail above, a bit stream for digitally representing an image encoded by information necessary for decoding and compressed image data is input,
In the image decoding apparatus, information necessary for decoding is stored, and a table for decoding using the stored data at the start of decoding is provided, so that the decoding start time immediately after switching the video sequence can be shortened. it can.

Further, since the information necessary for decoding uses the information obtained by the first decoding, it is not necessary to prepare in advance.

Further, decoding can be started even in the middle of the input bit stream.

Further, in the case of a system that receives a plurality of sequences, since a table is provided for each sequence, any sequence can be handled.

[Brief description of the drawings]

FIG. 1 is a block diagram showing a configuration of a first exemplary embodiment of the present invention.

FIG. 2 is a flowchart for explaining the operation of the embodiment of FIG. 1;

FIG. 3 is a block diagram showing a configuration of a second exemplary embodiment of the present invention.

FIG. 4 is an explanatory diagram showing a comparison between decoding start points of the present invention and a conventional image decoding apparatus.

FIG. 5 is a block diagram illustrating a configuration of a conventional image decoding device.

FIG. 6 is a diagram showing the structure of an MPEG2 bit stream.

[Explanation of symbols]

 Reference Signs List 10A image decoding device 10B image decoding device 11 selector 12 image decoding unit 13 display device 14 CPU 15A to 15C table 16 antenna 17 tuner 18A, 18B table

──────────────────────────────────────────────────続 き Continued on the front page (72) Inventor Ryuji Saito 4-36-19 Yoyogi, Shibuya-ku, Tokyo Inside Graphics Communication Laboratories Inc. (72) Inventor Takayuki Kobayashi Yoyogi, Shibuya-ku, Tokyo 4-36-19, located in Graphics Communication Laboratories, Inc. (72) Inventor Shigeru Komatsu 4-36-19, Yoyogi, Shibuya-ku, Tokyo, located in Graphics Communication Laboratories Inc. (72) Inventor Norihiko Nagai 4-36-19 Yoyogi, Shibuya-ku, Tokyo Inside Graphics Communication Laboratories Co., Ltd. (72) Yoshikazu Kawamura 4-36-19 Yoyogi, Shibuya-ku, Tokyo No. Graphics Communication Co., Ltd.・ Laboratories (58) Fields surveyed (Int.Cl. ⁶ , DB name) H04N ^7/ 24-7/68

Claims (4)

(57) [Claims] 1. An apparatus for inputting information necessary for decoding and an input bit stream for digitally expressing an image encoded by compressed image data and storing the information necessary for decoding in an image decoding apparatus. An image decoding apparatus, comprising: a table for decoding using the stored data at the start of decoding. 2. The image decoding apparatus according to claim 1, wherein the table stores information necessary for decoding obtained by the first decoding. 3. The image decoding apparatus according to claim 1, further comprising means for starting decoding even in the middle of the input bit stream. 4. The image decoding apparatus according to claim 1, wherein the system receives a plurality of sequences, and comprises a table for each sequence.