JPH06141300A - Band compression signal processing unit - Google Patents

Abstract

PURPOSE:To suppress the increase in a code quantity and to prevent the deterioration in the coding efficiency by performing no refresh processing after in-frame processing corresponding to a content of a picture and applying refresh processing only to an area not subjected to in-frame processing within a refresh interval. CONSTITUTION:When motion compensation is implemented in the picture recording and reproduction, an in-frame discrimination history storage circuit 39 in an in-frame/inter-frame decision circuit 30 stores a generated frame for picture adaptive in-frame processing caused at a refresh interval of an output of an energy comparator circuit 35 and by storing a position on a screen, decides an area not applied with forced in-frame processing in the case of refresh processing and the result is inputted to an thinning circuit 40. In the thinning circuit 40, an output signal of a periodic refresh timing signal generating circuit 38 so as to implement periodic in-frame processing only for an area in which no picture adaptive in-frame processing is not generated at the refresh interval, and the resulting signal and an output signal of an energy comparator circuit 35 are added by an adder circuit 37 to control an output of a motion compensation circuit.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an apparatus for converting a video signal or the like into a digital signal and recording / reproducing it.

[0002]

2. Description of the Related Art As is well known, when digitally transmitting a video signal, band compression is performed by combining a transmission method using a variable length coding method and a combination of intraframe coding processing and interframe coding processing. Transmission methods are being studied. Among them, a technique for performing band compression by combining intraframe coding processing and interframe coding processing and transmitting the data is described in, for example, the document IEEE Trans.on Broadcasting.
Vol.36 No.4 DEC 1990 Woo Paik: “Degit
It is a band compression technology as shown in "al compatible HD-TV Broadcast system", and its characteristic part is explained below.

In FIG. 14, the video signal input to the input terminal 11 is supplied to the subtraction circuit 12 and the motion evaluation circuit 13, respectively. The subtraction circuit 12 performs a subtraction process, which will be described later, and the output thereof is input to a DCT (discrete cosine transform) circuit 14. The DCT circuit 14 takes in 8 pixels in the horizontal direction and 8 pixels in the vertical direction as a unit block (8 × 8 pixels = 64 pixels), and outputs a coefficient obtained by converting the pixel array from the time axis domain to the frequency domain. Then, each coefficient is quantized by the quantization circuit 15. In this case, the quantization circuit 15 has 32 types of quantization tables, and each coefficient is quantized based on the selected quantization table. The quantizing circuit 15 is provided with a quantizing table so that the amount of information generated and the amount of information sent are within a certain range.

The coefficient data output from the quantization circuit 15 is zigzag-scanned from the low frequency band to the high frequency band for each unit block, and is extracted.
It is inputted to 6 and variable-length coded by combining the number of zero coefficients (run length) and the non-zero coefficient as one set. The encoder is a variable-length encoder having a different code length depending on the frequency of occurrence of Huffman code or the like. Then, the variable-length coded data is input to a FIFO (first-in-first-out) circuit 17 and read out at a prescribed speed, and then, via an output terminal 18, a multiplexer in the next stage (not shown). [Control signal, voice data, sync data (SYN
C), NMP and the like described later are multiplexed] and sent to the transmission path. Since the output of the variable length coding circuit 16 has a variable rate and the rate of the transmission path is a fixed rate, the FIFO circuit 17 serves as a buffer that absorbs the difference between the generated code amount and the transmitted code amount. .

The output of the quantization circuit 15 is input to the inverse quantization circuit 19 and inversely quantized. Further, the output of the inverse quantization circuit 19 is input to the inverse DCT circuit 20 and returned to the original signal. This signal is input to the frame delay circuit 22 via the adder circuit 21. The output of the frame delay circuit 22 is supplied to the motion compensation circuit 23 and the motion evaluation circuit 13, respectively. Motion evaluation circuit 13
Is the input signal from the input terminal 11 and the frame delay circuit 2
The output signal of 2 is compared to detect the overall motion of the image, and the phase position of the signal output from the motion compensation circuit 23 is controlled. In the case of a still image, the original image and the image one frame before are compensated so as to match each other. The output of the motion compensation circuit 23 can be supplied to the subtraction circuit 12 via the switch 24, and can also be fed back from the addition circuit 21 to the frame delay circuit 22 via the switch 25.

Next, the basic operation of the above system will be described. The basic operation of this system includes intraframe coding processing and interframe coding processing. The intraframe coding process is performed as follows. When this process is performed, both switches 24 and 25 are off. The video signal of the input terminal 11 is converted from the time domain to the frequency domain by the DCT circuit 14 and quantized by the quantization circuit 15. This quantized signal is subjected to variable length coding processing and then output to the transmission line via the FIFO circuit 17. The quantized signal is the inverse quantization circuit 19
The signal is returned to the original signal by the inverse DCT circuit 20, and delayed by the frame delay circuit 22. Therefore, in the intra-frame coding process, it is equivalent to that the information of the input video signal is variable length coded as it is. This in-frame processing is performed in a proper cycle in units of predetermined blocks and scene changes of the input video signal. The periodic in-frame processing will be described later.

Next, the interframe coding process will be described. When the interframe coding process is executed, both the switches 24 and 25 are turned on. Therefore, the subtraction circuit 12 obtains a signal corresponding to the difference between the input video signal and the video signal one frame before. This difference signal is
It is input to the DCT circuit 14, converted from the time domain to the frequency domain, and then quantized by the quantization circuit 15. Further, since the differential signal and the video signal are added by the adding circuit 21 and input to the frame delay circuit 22,
A predicted video signal that predicts the input video signal from which the differential signal was created is created and input.

FIG. 15 shows a line signal in a state in which a video signal of a high-definition television signal is subjected to the intraframe processing and the interframe processing as described above and sent out on the transmission path. This signal is a signal of a transmission line, and is shown in a state in which a control signal, a voice signal, a synchronization signal (SYNC), a system control signal, NMP and the like are multiplexed. FIG. 15A shows the signals of the first line, and FIG. 15B shows the signals of the second and subsequent lines. If this video signal has undergone intraframe processing, a normal video signal can be obtained by inverse conversion. However, in the case of a video signal that has been subjected to interframe coding processing, the difference signal is only reproduced even if this signal is inversely converted. Therefore, a normal video signal can be reproduced by adding the video signal (or the predicted video signal) reproduced one frame before to the difference signal.

According to the above system, all the information in the signal processed in the frame is variable-length coded, and the signal processed in the inter-frame after the next frame transmits the difference information. It means that the compression is realized.

Next, the definition of the set of pixels processed by the band compression system will be described. That is, a block: an area of 64 pixels composed of 8 pixels in the horizontal direction and 8 pixels in the vertical direction.

Super block: 4 in the horizontal direction of the luminance signal
A block is an area composed of two blocks in the vertical direction. This area includes one block as the color signals U and V. The image motion vector obtained from the motion evaluation circuit 13 is included in units of super blocks.

Macroblock: 11 superblocks in the horizontal direction. In addition, when the code is transmitted, the DCT coefficient of the block is converted into a code determined by the number of consecutive zero coefficients and the amplitude of the non-zero coefficient, and these are transmitted as a set to transmit the code of the block. Finally, an end of block signal is added. Then, the motion vector of the motion correction performed in units of super blocks is
It is added and transmitted in macroblock units.

With respect to the transmission signal shown in FIG.
Further explanations will be given on particularly relevant matters. First
The line synchronization (SYNC) signal indicates a frame synchronization signal in the decoder, and one timing synchronization signal is used for one frame to generate all timing signals of the decoder. The NMP signal on the first line indicates the number of video data from the end of this signal to the beginning of the macroblock of the next frame. This is because the code is configured by adaptively switching between the intra-frame coding process and the inter-frame coding process, so that the code amount of one frame differs for each frame, and the code position differs. This is because of Therefore, the position of the code corresponding to one frame is indicated by the NMP signal.

As a countermeasure when the user changes the channel, periodical intraframe processing is performed. That is, in this band compression system, as described above, 11 super blocks in the horizontal direction are called macro blocks, and 44 super blocks exist in the horizontal direction of one screen. That is, in one frame, there are a total of 240 macroblocks of 4 macroblocks in the horizontal direction and 60 macroblocks in the vertical direction. Then, in this band compression system, FIGS.
Also, as shown in FIGS. 17A to 17C, refresh is performed for each vertical row of super blocks in units of four macro blocks, and all the super blocks are refreshed in 11 frame cycles. That is, as shown in FIG. 17D, the refreshed superblocks are accumulated for 11 frames, so that the intraframe processing is performed in all the areas.
Therefore, for example, during normal reproduction of a VTR (video tape recorder) or the like, the above-described intraframe processing is performed at an 11-frame cycle, so that a reproduced image can be viewed without any problem.

Head data is inserted at the beginning of the macroblock. This head data contains
The motion vector, field / frame determination, PCM / DPCM determination, quantization level, etc. of each super block are inserted together.

[0016]

The problem with the conventional example is that the intra-frame processing that occurs depending on the scene occurs during the refresh period in which the intra-frame processing is forcibly performed (the period from one refresh to the next refresh). In that case, there arises a problem that the generated code amount increases.

An object of the present invention is to prevent the encoding efficiency from being lowered by further refreshing when the intra-frame processing occurs according to the contents of the image.

[0018]

In order to solve the above problems, the present invention employs the following technical means. In the intra-frame / inter-frame decision circuit, a refresh interval of f frames is set, a circuit for storing the history of the area in which the image adaptive intra-frame processing occurred within the refresh interval, and an output signal of this intra-frame discrimination history circuit are used. , A circuit for thinning out refresh generated periodically is used.

[0019]

According to the above construction, the refresh is not performed after the intra-frame processing generated according to the image content, and the reduction of the coding efficiency due to the refresh can be avoided.
Higher image quality can be achieved.

[0020]

Embodiments of the present invention will be described below in detail with reference to the drawings. (Note that the new configuration is shown by a double frame in the block diagram.) Basic Configuration FIG. 1 is a diagram showing the basic configuration of the present invention. The luminance signal Y and the color signals U and V of a high definition TV or the like are input to the video input terminals 26, 27 and 28. After subjecting these signals to the necessary pre-processing, the blocking circuit 29 configures a block having a pixel configuration, which will be described later in Chapter 2, and inputs the block to the input terminal 11. The video signal input to the input terminal 11 is supplied to the subtraction circuit 12 and the motion evaluation circuit 13, respectively.
In the subtraction circuit 12, a subtraction process described later is performed,
The output is input to the DCT (discrete cosine transform) circuit 14. The DCT circuit 14 takes in 8 pixels in the horizontal direction and 8 pixels in the vertical direction as a unit block (8 × 8 pixels = 64 pixels), and outputs a coefficient obtained by converting the pixel array from the time axis domain to the frequency domain. Then, each coefficient is quantized by the quantization circuit 15. In this case, the quantization circuit 15
It has 0 or 32 types of quantization tables, and each coefficient is quantized based on the selected quantization table. The quantizing circuit 15 is provided with a quantizing table so that the amount of information generated and the amount of information sent are within a certain range.

The coefficient data output from the quantization circuit 15 is zigzag-scanned from the low frequency band to the high frequency band for each unit block, and is extracted.
It is inputted to 6 and variable-length coded by combining the number of zero coefficients (run length) and the non-zero coefficient as one set. The encoder is a variable-length encoder having a different code length depending on the frequency of occurrence of Huffman code or the like. Then, the variable-length coded data is input to a FIFO (first-in-first-out) circuit 17 and read out at a prescribed speed, and then, via an output terminal 18, a multiplexer in the next stage (not shown). [Control signal, voice data, sync data (SYN
C), NMP and the like described later are multiplexed] and sent to the transmission path. Since the output of the variable length coding circuit 16 has a variable rate and the rate of the transmission path is a fixed rate, the FIFO circuit 17 serves as a buffer that absorbs the difference between the generated code amount and the transmitted code amount. .

The output of the quantization circuit 15 is input to the inverse quantization circuit 19 and inversely quantized. Further, the output of the inverse quantization circuit 19 is input to the inverse DCT circuit 20 and returned to the original signal. This signal is input to the frame delay circuit 22 via the adder circuit 21. The output of the frame delay circuit 22 is supplied to the motion compensation circuit 23 and the motion evaluation circuit 13, respectively. Motion evaluation circuit 13
Is the input signal from the input terminal 11 and the frame delay circuit 2
The output signal of 2 is compared to detect the overall motion of the image, and the phase position of the signal output from the motion compensation circuit 23 is controlled. In the case of a still image, the original image and the image one frame before are compensated so as to match each other. The output of the motion compensation circuit 23 can be supplied to the subtraction circuit 12 via the switch 24, and can also be fed back from the addition circuit 21 to the frame delay circuit 22 via the switch 25.

Next, the basic operation of the above system will be described.

2. The signal input to the pixel configuration input terminal 11 forms a block, a super block, and a macro block by collecting a plurality of effective pixels in one screen. This configuration is based on DigiCipher
The example is based on MPEG, DSC-HDTV: Zenith + AT
It goes without saying that the block configuration used in the T method or the like may be used.

The definition of the block configuration will be described with reference to FIG.

Block: An area of 64 pixels composed of 8 pixels in the horizontal direction and 8 pixels in the vertical direction (see FIG. 2).
(See (d)).

Super block: luminance signal in horizontal direction 4
A block is an area composed of two blocks in the vertical direction. This area includes one block as the color signals U and V. The image motion vector obtained from the motion evaluation circuit 13 can be set in units of super blocks (see FIG. 2 (c)).

Macroblock: 11 superblocks in the horizontal direction. In addition, when the code is transmitted, the DCT coefficient of the block is converted into a code determined by the number of consecutive zero coefficients and the amplitude of the non-zero coefficient, and these are transmitted as a set to transmit the code of the block. Finally, an end of block signal is added. Then, the motion vector of the motion correction performed in units of super blocks is
It is added as overhead data in units of macroblocks and transmitted (see FIG. 2B).

That is, in this band compression system, as described above, the 11 super blocks in the horizontal direction are called macro blocks, and 44 in the horizontal direction of one screen.
Super block exists. That is, in one frame, there are a total of 240 macroblocks of 4 macroblocks in the horizontal direction and 60 macroblocks in the vertical direction. Then, in this band compression system, FIG.
As shown in (a) to (h) and FIGS. 4 (a) to (c),
Refreshing is performed in units of four macroblocks in each vertical column of superblocks, and all superblocks are refreshed in a cycle of 11 frames.
That is, as shown in FIG. 4D, the refreshed super block is accumulated for 11 frames, so that the intra-frame processing is performed in all the areas.

One screen: 1050 scanning lines, interlaced. The effective pixel is horizontal 14
It is composed of 08 pixels and 960 pixels in the vertical direction. Video signals for one screen are processed by four processors (Fig. 2
(See (a)).

FIG. 5 shows the relationship between one screen and a super block address (hereinafter referred to as SBA = Super Block Address). There are 44 super blocks in the horizontal direction and 60 super blocks in the vertical direction. Therefore, there are 2640 super blocks in one screen. The address S. B. Assign A. If the horizontal superblock address is x and the vertical superblock address is y, S.S. B. A = 60
There is a relationship of x + y.

3. Intra-frame / inter-frame coding The first basic operation of this system is intra-frame coding processing and inter-frame coding processing. The intraframe coding process is performed as follows. When this process is performed, both switches 24 and 25 are off. The video signal of the input terminal 11 is converted from the time domain to the frequency domain by the DCT circuit 14 and quantized by the quantization circuit 15. This quantized signal is subjected to variable length coding processing and then output to the transmission line via the FIFO circuit 17. The quantized signal is returned to the original signal by the inverse quantization circuit 19 and the inverse DCT circuit 20, and delayed by the frame delay circuit 22. Therefore, in the intra-frame coding process, it is equivalent to that the information of the input video signal is variable length coded as it is. This in-frame processing is performed in a proper cycle in units of predetermined blocks and scene changes of the input video signal. The periodic in-frame processing will be described later.

Next, the interframe coding process will be described. When the interframe coding process is executed, both the switches 24 and 25 are turned on. Therefore, the subtraction circuit 12 obtains a signal corresponding to the difference between the input video signal and the video signal one frame before. This difference signal is
It is input to the DCT circuit 14, converted from the time domain to the frequency domain, and then quantized by the quantization circuit 15. Further, since the differential signal and the video signal are added by the adding circuit 21 and input to the frame delay circuit 22,
A predicted video signal that predicts the input video signal from which the differential signal was created is created and input. Generally, the generated code amount of the image processed in the frame is larger than the generated code amount of the image processed in the inter-frame.

4. 4. Intra-frame / inter-frame switching process 4.1 Image adaptive intra-frame process Switching between the intra-frame coding process and the inter-frame coding process is controlled by the intra-frame / inter-frame determination circuit 30. There are two types of this control method. First, the first method is a method of performing inter-frame processing on a signal having inter-frame correlation and performing intra-frame processing on a signal having no inter-frame correlation in accordance with the content of an input video signal. . When a scene change or the like occurs, in-frame processing is performed. In the intra / frame determination circuit 30, the input terminal 11
The energy of the current signal is compared with the prediction error energy between the signal of the current frame from and the prediction signal of the output of the motion compensation circuit 23.

In FIG. 6, terminals 11, 31, 32, 3
3, 34 are terminals 11, 31, 32, 33, 34 of FIG.
Is the same as The current signal is input to the terminal 11. This current signal is input to the energy comparison circuit 35 and the subtraction circuit 36. The motion compensation circuit 23 is provided at the terminal 32.
The prediction signal of the output of is input, and the subtraction circuit 36 obtains the prediction error which is the difference between the current signal and the prediction signal. The current signal is calculated by the current signal energy calculation circuit 35a, and the prediction error is compared by the prediction error energy calculation circuit 35b.
Examples of energy calculation formulas for the current signal and the prediction error are as follows.

[0036]

[Equation 1] FIG. 7 shows an example of the intra-frame / inter-frame discrimination method in the energy comparison circuit 35. In the figure, the horizontal axis represents the energy of the current signal and the vertical axis represents the energy of the prediction error. Further, a solid line drawn from the origin 0 in a slanted line shows a case where the energy of the prediction error and the energy of the current signal are equal. Since the energy of the prediction error is smaller in the area below the solid line, inter-frame processing is performed. Also, since the energy of the current signal is smaller above the solid line, intra-frame processing is performed. The output of the energy comparison circuit 35 outputs the intra-frame / inter-frame discrimination signal adapted to the input signal, the addition circuit 37 combines the signals, and the result is output from the terminal 33.

4.2 Forced In-frame Processing (Refresh) The second method is a method of forcibly performing in-frame processing regardless of the correlation of video signals. In this case, the in-frame processing is periodically performed on a predetermined area of the screen. There are two purposes for performing this forced in-frame processing. It is necessary for the user to recognize the image within a certain time when the user changes the channel. This is so that special reproduction can be realized in a recording medium such as a VTR or a disc.

This forcible in-frame processing is called refreshing. Further, the time required for refreshing a predetermined area is named refresh time. As shown in FIG. 6, the refresh timing generation circuit 38 inputs a synchronizing signal from the terminal 31 and generates an intra-frame selection signal at a predetermined cycle in synchronization with this synchronizing signal. This signal and the intra-frame / inter-frame discrimination signal of the energy comparison circuit 35 are added by the adder circuit 37, and the intra-frame / inter-frame switching signal is output from the terminal 33.

5. Refresh Refresh of each of the following methods will be described in detail.

5.1 DigiCipher Refresh In DigiCipher, as described above, 11 super blocks in the horizontal direction are called macro blocks, and 44 super blocks exist in the horizontal direction of one screen. That is, in one frame, there are a total of 240 macroblocks of 4 macroblocks in the horizontal direction and 60 macroblocks in the vertical direction. And in this band compression system, FIG. 3 (a)-(h) and FIG. 4 (a)-
As shown in (c), refreshing is performed in units of four macroblocks in each vertical column of superblocks, and all the superblocks are refreshed in 11 frame cycles. That is, as shown in FIG. 4D, the refreshed super block is accumulated for 11 frames, so that the intra-frame processing is performed in all the areas. The advantage of this refreshing is that refreshing is performed uniformly for each frame, so that the capacity of the rate buffer may be small.

This DigiCipher refresh is shown in FIG. 8 using the super block address shown in FIG. In the figure, the vertical axis indicates the super block address, the horizontal axis indicates the frame number, and the blackened portions indicate the intra-frame processed portions. In the figure,
Only refresh blocks are shown. In the figure, all the super blocks of one screen are refreshed in 11 frames with frame numbers F _{0 to} F ₁₀ . Since the same processing is performed by the four processors, the refresh operation for each processor in FIG.
Refresh will be described with reference to FIG.

That is, S. B. Address = 0 to 659
Will be described. In FIG. 9A, the portion subjected to the refresh and the image adaptive intra-frame processing is shown in black. For example, assuming that a scene change has occurred at F ₀ , the S. B. Address 0-6
In-frame processing is applied to all 59 areas. Further, in F ₁₄ , S. B. In-frame processing is performed in the area of addresses 0 to 59.

FIG. 9B shows the DigiCipher refresh time. A part of the area is refreshed per frame, and the refresh is completed in the 11-frame period, so that 11 frames become the refresh time. In addition, this refresh completes the refresh of one screen no matter what 11-frame period. That is, 1 of F _{0 to} F ₁₀
Refresh is completed in one frame period or 11 frame periods of F _{1 to} F ₁₁ .

As shown in FIG. 9C, the minimum acquisition time is one frame period and is obtained when the initialization starts when a scene change occurs. Further, the maximum acquisition time in FIG. 9D is a case where the image adaptive intra-frame processing does not occur at all, and is 11 frame periods. In the case of recording in the VCR and realizing high-speed reproduction using only the refresh block, at each refresh block address, as shown in FIG.
As shown in (e), the 11-frame period shifted in time becomes the recording interval of the VCR.

5.2 MPEG Refresh First, refresh used in MPEG will be described with reference to FIG. In MPEG, refresh is performed in frame units. The frame that has been refreshed is called an I picture. The cycle of this I picture, that is, the refresh cycle is set in units of frames, and 12, 15, ... Frames are selected. This situation will be described with reference to FIG. Note that only the case where the scanning line is 1050 will be described for simplification of description, but it goes without saying that other block configurations may be used.

In FIG. 10A, the vertical axis shows the super block address. This super block address corresponds to the super block address defined in FIG. The horizontal axis represents the frame number. Further, the blackened portions indicate the portions that have been subjected to the in-frame processing. Here, frame numbers 0 and 1
2, 24, 36, ... Indicate the intra-frame processed images that are periodically inserted, and frame numbers 13, 15, 17, 19,
The black-colored portions indicated by 21 and 23 indicate portions subjected to the image adaptive intra-frame processing.

In this example, the refresh time is as shown in FIG.
It is 12 frames as shown in (b). In order to obtain an image on one screen when the user initializes by changing the channel, in-frame processing must be performed on the entire area of one screen. Therefore, this time is defined as follows.

Acquisition time: The time required for intra-frame processing to be applied to the entire area of the screen.

This acquisition time also depends on the timing at which the user changes the channel. Figure 10 (c)
Shows the minimum acquisition time. The minimum acquisition time is the time when the start of initialization and refresh or the scene change occur at the same time, and one screen image can be obtained in one frame period. FIG. 10D shows the maximum acquisition time. The maximum acquisition time is when the initialization starts immediately after the refresh is completed. In this case, one screen image is obtained in 12 frame periods.

Next, in this case, let us consider a case in which special reproduction on a recording medium such as a VCR is realized by a refresh block which is a periodical intra-frame process. Since it is basically refreshed every 12 frames, VC
The recording interval of the R refresh block is 12 frames.

6. Image adaptive refresh When the content of the image changes, for example, when a scene change occurs, the image adaptive in-frame processing is performed. The code amount processed in the frame is larger than the code amount processed in the inter-frame. Therefore, when image adaptive intra-frame processing occurs during the refresh interval (period of intra-frame processing that is periodically inserted), the generated code amount increases. Actually, since the rate buffer is used to control the amount of generated codes to be constant, if the image adaptive intra-frame processing occurs in the refresh interval, the image quality is deteriorated.

The image adaptive refresh of the present invention is conceivable as a method for preventing this deterioration in image quality. In this method, when the image adaptive intra-frame processing occurs within the refresh interval, the area is not forcibly refreshed. If the image adaptive intra-frame processing does not occur within the refresh interval,
The area is forcibly refreshed in a predetermined frame.

As shown in FIG. 11, in order to realize the image adaptive refresh, an intraframe discrimination history storage circuit 39 and a thinning circuit 40 are newly used in the intraframe / interval determination circuit 30. The intra-frame discrimination history storage circuit 37 stores the occurrence frame and the position on the screen of the image adaptive intra-frame processing that occurred in the refresh interval of the output of the energy comparison circuit 35. As a result, when refreshing is performed, the area where the compulsory in-frame processing is not performed is determined and input to the thinning circuit 40.

The thinning-out circuit 40 thins out the output signal of the periodic refresh timing signal generating circuit 38 so that the periodical intra-frame processing is performed only in the area where the image adaptive intra-frame processing has not occurred in the refresh interval. The output signal of the thinning circuit 40 and the output signal of the energy comparison circuit 35 are combined by the addition circuit 37 and output from the terminal 33. As a result, the refresh is realized except for the area where the image adaptive intra-frame processing is performed at the refresh interval.

6.1 Image Adaptive MPEG Refresh FIG. 12 shows a case where image adaptive refresh is applied to MPEG.
Will be explained. In MPEG, as shown in FIG. 12A, refresh is performed in units of one frame. Here, as an example, it is assumed that refresh is performed in units of f = 12 frames. Since refresh is performed in 12 frames, the refresh interval is set as shown in FIG. It is assumed that the frame numbers F _{0 to} F ₁₁ are assigned to the refresh interval. In frame determination history storage circuit 39 stores the area where the image adaptive intra-frame processing is performed in 11 frames of the frame number F ₀ to F ₁₀ in the refresh interval (f-1 = 12-1 = 11 ) ( Also , The frame number of the image adaptive intra-frame processing is also stored if necessary).

In the frame numbers F _{0 to} F ₁₀ , forced refresh is performed in the last frame F ₁₁ of the refresh interval only in the area where the image adaptive intra-frame processing has not occurred. For example, in FIG. B. In the area of addresses ₀ to 239, image adaptive refresh is performed at frame number F ₀ . Therefore, in F ₁₁ , forced refresh is not performed. Also, S. B. Address 240
In ～479, since refreshing is not performed at the frame number F ₀ to F _10, performs a forced refresh in F _11. In this case, the refresh is completed within the refresh interval period. Also,
Since the image adaptive intra-frame processing and the refresh do not overlap, the image quality deterioration due to the refresh can be prevented.

An example of a circuit that realizes the above operation will be described with reference to FIG. The periodic refresh timing generation circuit 38 generates a signal for refreshing every 12 frames at the frame number F ₁₁ and inputs it to the thinning circuit 40. Further, in the in-frame discrimination history storage circuit 39, the recorded area information subjected to the in-frame processing is thinned out by the thinning circuit 4
Enter 0. In the thinning circuit 40, the frame number F ₁₁
At the time of refreshing, a signal for refreshing is generated except for the area subjected to the intraframe processing at the refresh interval. The output signals of the thinning circuit 40 and the energy comparison circuit 35 are added by the adding circuit 37 and output. Further, the frame number subjected to the image adaptive intra-frame processing is also output as necessary. Image adaptive MPE
The minimum acquisition time of G refresh occurs when the initialization start coincides with the processing within one screen frame, and is one frame period (see FIG. 12C).

The processing within one screen frame is performed in the following cases.

1.1 When a scene change occurs in the entire area of the screen 2. This is a case where the intraframe processing does not occur at all in F _{0 to} F ₁₀ of the refresh interval and the intraframe processing occurs only in F ₁₁ .

When the still picture continues, the intra-frame processing occurs only in F ₁₁ .

Next, the maximum acquisition time is 12 frames when a still picture continues, which is the same as the refresh time of the conventional MPEG. In addition, if the intra-frame processing of the scene change occurs at F ₀ and the initialization is started from F ₁ , the maximum acquisition time is 23.
It becomes a frame. The refresh cycle f and the maximum acquisition time T _aq have the following relationship. T _aq = _2xf -1 = 2x12-1 = 23 In a storage medium such as a VCR, a high-speed reproduction is performed by storing a signal processed in a frame in a refresh interval period and recording the signal at a predetermined position on the tape. realizable.

6.2 Image Adaptive DigiCipher Next, the image adaptive DigiCipher refresh shown in FIG. 13 will be described. This method is divided into small areas as shown in FIG. 13A, two refreshes are performed, and when the image adaptive intra-frame processing occurs at the refresh interval in the small areas, the area is forcibly forced. This is a method that does not perform refreshing.

As shown in FIG. 13E, a refresh interval is set for each small refresh area.
The refresh interval period is set to 11 frame periods. Further, between the small areas, the refresh interval is set at a timing shifted for each frame.
Then, within this refresh interval, refreshing is always performed once. For example,
S. B. In the area of addresses 0 to 59, the refresh interval is set as shown in FIG. The frame number within the refresh interval is F _0.
Set to ~ F ₁₀ . S. B. In the area of addresses 0 to 59, since the image adaptive intra-frame processing is performed in F ₂ , forced refresh is not performed in F ₁₀ . Also,
S. B. In the area of addresses 60 to 119, F _{0 to} F ₉
Since the image adaptive intra-frame processing has not occurred in F, forced refresh is performed in F ₁₀ .

The circuit for realizing this operation is the same as in FIG. Periodic refresh timing generation circuit 38
13 sets a refresh interval for each small area shown in FIG. 13 (e) and generates a signal for refreshing at frame number F ₁₀ every 11 frames. Also,
The intra-frame discrimination history circuit 39 stores the intra-frame processed area in the refresh interval for each small area. The stored area is input to the thinning circuit 40. The thinning circuit 40 outputs the refresh instruction signal only to the area to be refreshed at the frame number F ₁₀ of the refresh interval, excluding the area to which the image adaptive intra-frame processing is performed within the refresh interval. Further, the output signals of the thinning circuit 40 and the energy comparison circuit 35 are added by the addition circuit 37 and output. Further, if necessary, the frame number subjected to the image adaptive frame processing is also output. The minimum acquisition time in this case is one frame period when a scene change occurs in the video signal period of one frame. FIG. 13 (a)
That is the case of the 0th frame. Further, the maximum acquisition time is when the initialization of the receiver starts immediately after the scene change, which is 21 frame periods. In FIG. 13A, the initialization starts from the first frame, and thereafter, the image adaptive intra-frame processing is not performed at all, and the 11th to 21st frames are
This is the case when a refresh is performed.

The maximum acquisition time T _aq.max is determined by the following equation for the refresh cycle f. T _aq.max = _2xf -1 = _2x11-1 = 21 In addition, when the still image continues, the compulsory refresh period becomes the maximum acquisition time, and thus becomes 11 frame periods. In addition, in a storage medium such as a VCR, high-speed reproduction can be realized by accumulating a signal processed in a frame in each refresh area during a refresh interval period and recording the signal at a predetermined position.

[0066]

As described above, according to the configuration of the present invention, the refresh is not performed after the intraframe processing which occurs according to the image content, and only the area where the intraframe processing is not performed within the refresh interval. Since the refresh is performed, the increase in the code amount due to the refresh can be suppressed to the minimum. Furthermore, the acquisition time of the still image portion when the subscriber changes the channel is the same as the conventional example.

[Brief description of drawings]

FIG. 1 is a block diagram showing an embodiment of the present invention.

FIG. 2 is a diagram shown for explaining a pixel region in the embodiment.

FIG. 3 is a diagram showing refreshable refresh blocks of frames 0 to 7 in the embodiment.

FIG. 4 is a diagram showing reproducible refresh blocks up to frames 8 to 10 and refresh accumulated in 11 frames in the embodiment.

FIG. 5 is a diagram shown for explaining a super block address in the embodiment.

FIG. 6 is a block configuration diagram showing details of an intra-frame / inter-frame determination circuit in the embodiment.

FIG. 7 is a diagram for explaining intra-frame / inter-frame determination characteristics according to the embodiment.

FIG. 8 is a diagram shown for explaining forced refresh in the embodiment.

FIG. 9 is a diagram for explaining forced refresh per processor in the embodiment.

FIG. 10 is a diagram for explaining MPEG refresh in the embodiment.

FIG. 11 is a block diagram showing another example of the intra-frame / inter-frame determination circuit.

[Fig. 12] MPEG in the intra-frame / inter-frame determination circuit
The figure shown in order to demonstrate refresh.

FIG. 13: DigiCiph in the same frame / interval decision circuit
The figure shown in order to demonstrate er refresh.

FIG. 14 is a block diagram showing a conventional band compression signal processing system.

FIG. 15 is a diagram showing a format of a signal transmitted from the same system.

FIG. 16 is a diagram showing refreshable refresh blocks of frames 1 to 8 in the same system.

FIG. 17 is a diagram showing reproducible refresh blocks of frames 9 to 11 and refresh accumulated in 11 frames in the system.

[Explanation of symbols]

11 ... Input terminal, 12 ... Subtraction circuit, 13 ... Motion evaluation circuit, 14 ... DCT circuit, 15 ... Quantization circuit, 16 ... Variable length coding circuit, 17 ... FIFO circuit, 18 ... Output terminal,
19 ... Inverse quantization circuit, 20 ... Inverse DCT circuit, 21 ... Addition circuit, 22 ... Frame delay circuit, 23 ... Motion compensation circuit,
24, 25 ... Switches, 26-28 ... Input terminals, 29 ...
Blocking circuit, 30 ... In-frame / inter-frame determining circuit, 31
˜34 ... Terminal, 35 ... Energy comparison circuit, 36 ... Subtraction circuit, 37 ... Addition circuit, 38 ... Refresh timing generation circuit, 39 ... In-frame discrimination history storage circuit, 40 ...
Thinning circuit.

Claims (1)

[Claims] 1. An intra-frame processed signal obtained by subjecting a video signal to intra-frame encoding processing using information within a frame, and an inter-frame encoded signal subjected to inter-frame encoding processing using difference information between frames. And a band compression means for adaptively repeating a signal processing method for creating a processed signal and performing the inter-frame coding processing after the intra-frame coding processing according to the motion evaluation of the input video signal. When an intra-frame encoding process is performed on the image area of f frames (f is an integer of f ≧ 2), an interval of f frames is provided for each area of the image, and within the interval of the f frame, A band-compressed signal processing apparatus for forcibly performing in-frame processing only in an area in which no in-frame processing has occurred according to the content of an image.