JP3257052B2 - Highly efficient image signal encoding apparatus and method - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an apparatus and a method for encoding an image signal with high efficiency by orthogonally transforming the image signal.

[0002]

2. Description of the Related Art As a method for efficiently coding an image signal, for example, MPEG (Moving Picture Experts Group) is used.
In the standardization plan according to p), a so-called high-efficiency encoding method for image signals for digital storage media is specified. Here, the storage media targeted by this method is a so-called CD (compact disk) or D
A continuous transfer speed of about 1.5 Mbi such as an AT (Digital Audio Tape Recorder), a hard disk, etc.
It is less than t / sec. It is not only directly connected to the decoder, but also a computer bus, LAN
(Local Area Network), connection via transmission media such as telecommunications, etc., as well as special functions such as random access, high speed playback, reverse order playback, etc. Is also considered.

[0003] The principle of the high-efficiency encoding method for an image signal by the above-mentioned MPEG is as follows.

That is, in this high-efficiency coding system, first, the redundancy in the time axis direction is reduced by taking a difference between images, and thereafter, a so-called discrete cosine transform (DCT) process and a variable length code are used. To reduce the redundancy in the space axis direction.

First, the redundancy in the time axis direction will be described below.

In general, in a continuous moving image, an image before and after in time is similar to an image of interest (ie, an image at a certain time). Therefore, for example, as shown in FIG. 44, if the difference between the image to be encoded now and the image ahead in time is calculated and the difference is transmitted, the redundancy in the time axis direction can be reduced. It is possible to reduce the amount of information to be transmitted. The image encoded in this way is a forward predictive-coded picture (P-picture or P-picture or P-picture) described later.
Frame). Similarly, the difference between the image to be encoded and the interpolated image formed from the front or the rear or the front and the rear in time is calculated, and the difference between the small values is transmitted. For example, it is possible to reduce the amount of information to be transmitted by reducing the redundancy in the time axis direction. An image encoded in this way is a bidirectional prediction encoded image (Bidirectio
nallyPredictive-coded picture, B picture or B
Frame). In FIG. 44, the image indicated by I in the figure represents an intra-coded image (Intra-coded picture: I picture or I frame) described later, and the image indicated by P in the figure A picture indicates a picture, and an image indicated by B in the figure indicates the B picture.

In order to generate each predicted image, so-called motion compensation is performed. That is, according to this motion compensation, for example, a block of, for example, 16 × 16 pixels (hereinafter, referred to as a macroblock) constituted by a unit block of 8 × 8 pixels is created, and the block is located near the position of the macroblock in the previous image. By searching for a place with a small difference and calculating the difference with the searched macroblock, it is possible to reduce data to be sent. Actually, for example, in the P picture (forward predicted coded image), the difference between the predicted image after motion compensation and the one without difference from the motion compensated predicted image is obtained. Those with a small amount are selected and coded in macroblock units of 16 × 16 pixels.

However, in the case described above, a large amount of data must be sent, for example, with respect to a portion (image) that comes out after the object has moved. Therefore, for example, in the case of the B picture (bidirectional predictive coded image), the already decoded temporally forward or backward image after motion compensation and the interpolated image formed by adding both of them will be coded from now on. The difference between the image and the image that does not take the difference, that is, the image having the smallest data amount among the four images to be encoded is encoded.

Next, the redundancy in the space axis direction will be described below.

The difference between the image data is not transmitted as it is, but is subjected to a discrete cosine transform (DCT) for each unit block of 8 × 8 pixels. The DCT expresses an image not at a pixel level but by how many frequency components of a cosine function are included. For example, by a two-dimensional DCT, data of a unit block of 8 × 8 pixels is two-dimensional. It is converted into a coefficient block of an 8 × 8 cosine function component by DCT. For example, an image signal of a natural image captured by a television camera is often a smooth signal. In this case, the DCT is applied to the image signal.
By performing the processing, the data amount can be efficiently reduced.

That is, for example, in the case of a smooth signal such as the above-described image signal of a natural image, a large value concentrates around a certain coefficient by applying the DCT. When these coefficients are quantized, most of the 8 × 8 coefficient blocks become 0, and only large coefficients remain. Therefore, when transmitting the data of the 8 × 8 coefficient block, a set of non-zero coefficients and a so-called zero run indicating how much 0 has continued before the coefficient in a so-called zigzag scan order. By transmitting the so-called Huffman code, the transmission amount can be reduced. On the decoder side, an image is reconstructed in the reverse procedure.

FIG. 45 shows the structure of data handled by the above-mentioned encoding method. That is, the data structure shown in FIG. 45 includes, in order from the bottom, a block layer, a macroblock layer, a slice layer, a picture layer, a group of picture (GOP) layer, and a video sequence layer. . Hereinafter, description will be made in order from the lower layer in FIG.

First, in the above-mentioned block layer, a block of the block layer is composed of 8 × 8 pixels (8 lines × 8 pixels) having adjacent luminance or color difference. The DCT (discrete cosine transform) described above is applied to each unit block.

In the above macroblock layer, the macroblocks in the macroblock layer include four luminance blocks (luminance unit blocks) Y0,
Y1, Y2, Y3 and a color difference block (color difference unit block) C at the same position as the luminance block on the image.
r and Cb are composed of a total of six blocks. The order of transmission of these blocks is Y0, Y1, Y2, Y3, C
r, then Cb. Here, in the encoding method, what is used for a predicted image (a reference image for taking a difference)
Alternatively, whether or not the difference need not be transmitted is determined in units of this macroblock.

The slice layer is composed of one or a plurality of macroblocks that are connected in the scanning order of the image. At the beginning of this slice (header), the difference between the motion vector and the DC (direct current) component in the image is reset, and the first macroblock has data indicating the position in the image, so that an error occurs. It is designed to allow you to return if something happens. Therefore, the length of the slice and the starting position are arbitrary and can be changed depending on the error state of the transmission path.

In the picture layer, a picture, that is, an image one by one, is composed of at least one or a plurality of the slices. Then, each of the above-described intra-coded images (I
Picture or I frame), forward predictive coded picture (P picture or P frame), bidirectional predictive coded picture (B picture or B frame), DC intra coded picture (DC coded (D) picture) Classified into images.

Here, in the above-mentioned intra-coded image (I picture), at the time of coding, only closed information in one image is used. Therefore, in other words, when decoding, an image can be reconstructed using only the information of the I picture itself. Actually, encoding is performed by DCT processing without taking a difference. This encoding method is generally inefficient, but if it is included everywhere, random access and high-speed reproduction can be performed.

In the forward predictive coded picture (P picture), an I picture or P picture which is located earlier in time at the input and has already been decoded is used as a predictive picture (picture serving as a reference for obtaining a difference). I do. In practice, the more efficient one of encoding the difference from the motion-compensated predicted image and encoding the difference without taking the difference (intra code) is selected in units of the macroblock.

The above bidirectional prediction coded image (B picture)
Uses three types of predicted pictures, i.e., an I-picture or a P-picture which is located earlier in time and have already been decoded, and an interpolated picture created from both of them. This allows
The most efficient one of the above three types of difference coding after motion compensation and intra coding can be selected in macroblock units.

The DC intra-coded image is an intra-coded image composed only of DCT DC coefficients.
It cannot exist in the same sequence as the other three images.

The group of pictures (GOP) layer includes one or more I pictures and zero or more non-I
And a picture. Here, the input order to the encoder is, for example, 1I, 2B, 3B, 4P * 5B, 6
B, 7I, 8B, 9B, 10I, 11B, 12B, 13
P, 14B, 15B, 16P * 17B, 18B, 19
When I, 20B, 21B, and 22P are used, the output of the encoder, that is, the input of the decoder is, for example, 1I, 4
P, 2B, 3B * 7I, 5B, 6B, 10I, 8B, 9
B, 13P, 11B, 12B, 16P, 14B, 15B
* 19I, 17B, 18B, 22P, 20B, 21B. The reason why the rearrangement of the order is performed in the encoder is, for example, in the case of encoding or decoding the B picture, the I picture or the P picture which is a temporally backward prediction image. This is because the picture must be coded first. Here, the interval between the I pictures (for example, 9) and the interval between I or B pictures (for example, 3) are free. Also, I picture or P
The picture interval may vary within the group of pictures layer. The breaks in the group of picture layers are indicated by *. In addition, I indicates an I picture, P indicates a P picture, and B indicates a B picture.

The video sequence layer has an image size,
It is composed of one or more group of picture layers having the same image rate or the like.

[0023]

As described above, when transmitting a moving picture standardized by the above-described high-efficiency coding scheme based on MPEG, an image obtained by compressing one image in a picture is transmitted first. Then, the difference between this image and the image whose motion has been compensated is transmitted.

However, in the above-described one image, for example, when processing a field as a picture, 2
Since the vertical position will be different in the field alternately,
For example, when transmitting a still image, difference information must be transmitted.

When a frame is processed as a picture, for example, a moving part in the frame must be processed as a so-called comb-shaped image. That is, for example, as shown in FIG. 46, when there is a moving object CA such as a car in front of a stationary background, when one frame is viewed, there is movement between fields. turn into.

Further, for example, when processing an image in which a still portion and a moving image portion are mixed, no matter whether the above-mentioned field is processed as a picture or the frame is processed as a picture, In this case, an image of a portion having a low compression efficiency is formed.

Accordingly, the present invention has been proposed in view of the above-described circumstances. For a moving image having a field structure, an image having little motion or an image having much motion, or an image in which both of them are mixed, is used. It is an object of the present invention to provide a high-efficiency image signal encoding apparatus and method capable of efficiently performing field processing or frame processing.

[0028]

In order to solve such a problem, a first high-efficiency coding apparatus according to the present invention provides a motion-compensated prediction using a macroblock consisting of a two-dimensional array of a plurality of pixels as a unit. And a means for selecting one of motion compensation prediction, frame prediction or field prediction, as a means for encoding each macroblock in a high-efficiency image signal encoding apparatus that performs encoding by orthogonal transformation, Means for selecting any one of the orthogonal transforms, a first restriction mode in which field prediction is selected for all macroblocks in one frame and orthogonal transform is performed by field processing, and each macroblock in one frame is selected. In each case, select either motion compensation prediction, either frame prediction or field prediction, and determine whether to perform field processing or frame processing. A second restriction mode for adaptively selecting one of the orthogonal transforms; a means for selecting one of the restriction modes for each frame; Is good,
Means for selecting an efficient restriction mode, wherein the means for selecting the restriction mode further includes, for each of the first field and the second field of the macroblock, for the bidirectional prediction frame, The motion compensation prediction is performed from the first or second field, and when the second restriction mode is selected, the motion compensation prediction from the first field to the second field of the frame is not performed.

[0029]

[0030]

[0031]

[0032]

[0033]

Further, the second high-efficiency encoding apparatus is characterized in that the restricted mode selecting means in the first high-efficiency encoding apparatus is as follows.
A parameter representing the magnitude of the motion of the entire screen is obtained from the median value of the horizontal and vertical components of the detected motion vector, and the first and second restriction modes are selected based on the parameter. It is.

Further, the third high-efficiency encoding apparatus is characterized in that the restricted mode selecting means in the first high-efficiency encoding apparatus comprises:
A correlation between an odd field and an even field is obtained, and the first and second restriction modes are selected based on the correlation.

Further, the fourth high-efficiency encoding apparatus is characterized in that the restricted mode selecting means in the first high-efficiency encoding apparatus is as follows.
For a macroblock in the current frame to be encoded,
The first and second restriction modes are selected based on a difference between the image and an already decoded image referred to by the motion vector.

Further, the fifth high-efficiency encoding device is characterized in that the restricted mode selecting means in the first high-efficiency encoding device is as follows:
A correlation between the odd field and the even field is obtained, and a value corresponding to the obtained correlation is added over all the macroblocks existing in the current frame to be encoded. The selection of the restriction mode is performed.

Further, the sixth high-efficiency encoding apparatus is characterized in that the restricted mode selecting means in the first high-efficiency encoding apparatus is as follows.
The anisotropy of the vector is detected from the motion vectors of all the detected macroblocks. The selection of the first and second restriction modes is performed based on the addition value over the above.

In order to solve the above-mentioned problem, a high-efficiency encoding method according to the present invention performs encoding by motion-compensated prediction and orthogonal transform in units of a macroblock consisting of a two-dimensional array of a plurality of pixels. In the high-efficiency encoding method of an image signal to be performed, a first restriction mode in which motion compensation prediction is performed by field prediction and orthogonal transformation is performed by field processing for all macroblocks in one frame, and each macroblock in one frame is A second restriction mode in which, for each macroblock, either motion compensation prediction of frame prediction or field prediction is selected, and any orthogonal transform of field processing or frame processing is adaptively selected. Selecting a restriction mode for each frame, and determining which of the first and second restriction modes is more efficient in encoding. And selecting an efficient restriction mode, further comprising the step of selecting the restriction mode, wherein the step of selecting the restriction mode further includes, for each of the first field and the second field of the macroblock, for the bidirectionally predicted frame, before and after. The motion compensation prediction is performed from the first or second field of the frame, and when the second restriction mode is selected, the motion compensation prediction from the first field to the second field of the frame is not performed. is there.

[0040]

[0041]

[0042]

[0043]

[0044]

[0045]

[0046]

According to the first high-efficiency coding apparatus of the present invention, it is possible to switch between frame processing and field processing in units of macroblocks within one frame. Therefore, efficient coding can be selected in units of macroblocks. it can.

[0047]

According to the second high efficiency coding apparatus,
By processing the entire B frame in units of fields and switching the mode in which the even fields of the same frame are not predicted from the odd fields of the same frame in units of frames or slices, the number of frame buffers of the decoding device is two. That is, it can be reduced to four fields.

According to the third encoding apparatus, the number of frame buffers can be reduced to one and a half, that is, three fields.

[0050]

[0051]

[0052]

Embodiments of the present invention will be described below with reference to the drawings. FIG. 1 shows Embodiment 1 of a first high-efficiency encoding apparatus for an image signal according to the present invention.

FIG. 1 shows a first embodiment, in which a macroblock consisting of a two-dimensional array of pixels smaller than one screen (for example, one block of 16 × 16 pixels in the spatial arrangement of input image data in raster scan order) ) Is a high-efficiency encoding apparatus for encoding an image signal, in which a plurality of unit blocks each having a size of 16 × 16 pixels are arranged in a plurality of frames (one screen). Frame memory group 1 stored as
0 and a frame which is a motion detecting means for detecting the sum of the absolute value difference of each pixel with the motion vector between the frames and between the fields which are obtained by scanning the pixels of the frame in odd or even numbers in the macroblock unit. Efficiency of the motion detection circuit 22 and the field motion detection circuit 21 is higher in either the frame prediction mode in which motion compensation is performed in units of frames in the macroblock or the field prediction mode in which motion compensation is performed in units of fields in the macroblock. The motion prediction mode determination circuit 23 and the selector 24, which are the first mode selection means for determining whether the prediction mode is efficient or not, based on information output from the motion detection means, and a frame in the macroblock as a unit. Frames that are blocked to perform orthogonal transformation Which of the processing mode and the field processing mode in which the macroblock is subjected to orthogonal transformation in units of fields in the macroblock is more efficient when performing orthogonal transformation is determined by the motion detection unit and the first mode selection unit. Blocking mode determination circuit 25 that is a second mode selection unit that determines using the output information and selects a mode of an efficient block.
It recognizes whether an odd cycle during a scan of an odd field or an even cycle of a scan of an even field in the interlacing of the encoding process for one frame (one screen), and performs the above-described blocking at the odd cycle. An address generator 11 which is an address generating means for controlling a frame memory group so as to output a macroblock divided into blocks corresponding to the mode; the motion prediction mode information selected by the first mode means; A frame memory group 20 with a motion compensator, which is a motion compensation unit that receives the blocking mode information selected by the second mode selection unit and executes a motion compensation frame or inter-field prediction according to the mode information. Things.

First, using the configuration shown in FIG.
The main flow of the image data to be encoded in will be described.

That is, in FIG.
Is supplied with a digital image signal and stored in the frame memory group 10. From the frame memory group 10, the data of the unit macroblock of 16 × 16 pixels is read out under the control of an address generator 11 described later and transmitted to a difference detector 12. The difference detector 12
Is also supplied with motion-compensated image data from a frame memory group 20 with a motion compensator, which will be described later, and the difference detector 12 detects these differences.

The output of the difference detector 12 is sent to a DCT circuit 13 that performs an orthogonal transform (DCT) process. The DCT coefficient data obtained by the DCT processing by the DCT circuit 13 is sent to the quantizer 14. The quantizer 14
Is output from the output terminal 2 as encoded data through a variable-length encoding circuit 15 that performs variable-length encoding processing such as so-called Huffman encoding or run-length encoding and a buffer 16. You.

The frame memory group with motion compensator 20 stores the quantized data from the quantizer 14 in an inverse quantizer which performs an inverse quantization process of the quantization process in the quantizer 14. Data is supplied via an adder 19 through an inverter 17 and an inverse DCT circuit 18 for performing an inverse DCT process of the DCT process in the DCT circuit 13.
The adder 19 adds the output of the inverse DCT circuit 18 and the output of the frame memory group 20 with motion compensator. From the buffer 16, a signal for preventing the buffer 16 from overflowing is fed back to the quantizer 14.

On the other hand, the image data output from the frame memory group 10 in units of macroblocks is transmitted to a frame motion detection circuit 22 and a field motion detection circuit 21.

The frame motion detecting circuit 22 detects the inter-frame motion vector and the sum of absolute differences of each pixel in units of the macro block, and outputs these data (the motion vector data FMMV between frames and the sum of absolute differences). Data FMAD) is output. Further, the field motion detection circuit 21 detects a motion vector between fields and the sum of absolute value differences of each pixel in the macroblock unit, and outputs these data (data FDMV of the motion vector between fields and sum of absolute value differences). Data FDAD). The data FMMV of each motion vector of the motion detection circuits 21 and 22
/ FDMV is transmitted to the selector 24, and the data FMAD / FDAD of the sum of absolute value differences is transmitted to the motion prediction mode determination circuit 23.

The motion prediction mode determination circuit 23 calculates the absolute value difference sum data F from the frame motion detection circuit 22.
Based on the MAD and the absolute value difference sum data FDAD from the field motion detection circuit 21, the motion prediction processing is performed in the frame unit at the time of the motion prediction processing in the frame memory group 20 with a motion compensator described later, or It is determined whether or not to perform the motion prediction process on a field-by-field basis, and data indicating the more advantageous (efficient) processing mode is output. More specifically, the motion prediction mode determination circuit 23
For example, when it is determined that the difference between the absolute value difference sum data FMAD and the absolute value difference sum data FDAD is larger than a certain threshold value T1 (when FMAD-FDAD> T1),
The circuit 23 outputs data (data MPFD of the field processing mode in the motion prediction) indicating that it is more efficient to perform the motion prediction processing on a field basis.
Conversely, if it is determined that the difference between the absolute value difference sum data FMAD and the absolute value difference sum data FDAD is smaller than or equal to the threshold value T1 (when FMAD-FDAD ≦ T1), the frame unit And outputs data (data MPFM in the frame processing mode in motion prediction) indicating that it is more efficient to perform the motion prediction process. Any one of these motion prediction mode data MPFM / MPFD is sent to the frame memory group 20 with motion compensator, so that the frame memory group 20 performs motion compensation in frame units or field units. These motion prediction mode data MPFM / MPFD are also sent to the selector 24.

The selector 24 receives the motion prediction mode data MPFM / MP from the motion prediction mode determination circuit 23.
According to the FD, data FMMV of a motion vector between frames supplied from the frame motion detection circuit 22;
One of the inter-field motion vector data FDMV supplied from the field motion detection circuit 21 is selectively output. That is, when the motion prediction mode data is the data MPFD indicating the field prediction mode, the motion vector data F
When the motion prediction mode data is the data MPFM indicating the frame prediction mode, the motion vector data FMMV from the frame motion detection circuit 22 is selected.
Select and output. The motion vector data FMMV / FDMV selected by the selector 24 is sent to the blocking mode determination circuit 25.

The blocking mode determination circuit 25 includes:
Output data from the frame memory group 10 and the processing mode data MPFM / MPFD from the motion prediction mode determination circuit 23 are also supplied. In the blocking mode determination circuit 25, the motion prediction mode data MPFM / MPFD and the motion vector data FMMV
/ FDMV, and further, the frame memory group 10
Then, a difference image is created using the image from the image processing unit, and based on the difference image, a block processing mode most suitable for an image output from the frame memory group 10 and subjected to DCT processing by the DCT circuit 13 is selected. In the case of the I picture (or I frame), data of an image (original image) in the frame memory group 10 is used instead of the difference image.

That is, it is assumed here that, for example, the macroblock of the difference image is a macroblock as shown in FIG. 2 (the macroblock of the original picture in the I picture). In FIG. 2, odd lines (o1, o)
2, o3,... ON, where N is a macroblock 16) is indicated by a solid line, and even lines (e1, e2, e3)
,... EN, where N is 1 for a macroblock
6) is indicated by a dotted line. Also, each pixel of the even line is represented as e (i, j), and each pixel o (i,
j). In the difference image or the original image (I-picture image) as shown in FIG. 2, the difference EFD of the difference image in the unit of field can be expressed by the following equation (1), and the difference EFM of the difference image in the unit of the frame is It can be shown by the following mathematical expression 2.

[0064]

(Equation 1)

[0065]

(Equation 2)

In the blocking mode determination circuit 25, specifically, the threshold value T2 in which the difference between the difference EFM obtained in the frame and the difference EFD obtained in the field by using the formulas 1 and 2 is used. Greater than (EFM-EFD> T
2), data indicating that the DCT in the DCT circuit 13 is to be performed in units of fields (data MD in the field processing mode in the block processing).
FD) is output. Conversely, if it is determined that the difference between the difference EFM and the difference EFD is smaller than or equal to the threshold value T2 (when EFM-EFD≤T2), the above D
It outputs data (data MDFM in the frame processing mode in the block processing) indicating that the DCT in the CT circuit 13 is to be performed on a frame basis. Any of the block processing mode data MDFM / MDFD is transmitted to the address generator 11 and the frame memory group 20 with motion compensator. Further, the motion vector data (FMMV
/ FDMV) and the block processing mode data (MDFM
/ MDFD) and the above prediction mode data (MPFM / MPFD)
Is sent to the above-described variable-length coding circuit 15.

In the address generator 11, for the image data stored in the frame memory group 10, for example, macroblocks which are divided into blocks in accordance with the processing mode data MDFM / MDFD in the DCT in units of macroblocks are used. Control the frame memory group to output. That is, in the address generator 11,
The block mode data is DCT in frame units.
In the case of the data MDFM indicating the processing, the frame memory group is controlled so as to output a macroblock in which even and odd are alternately scanned as shown in FIG. As a result, the unit block of the macro block sent to the DCT circuit 13 is a combination of the even field and the odd field. Conversely, when the blocking mode data is data MDFD indicating DCT processing in units of fields, as shown in FIG. 4, even and odd scans are separately divided to output scanned macroblocks. Control the frame memory group. This allows
The unit block of the macro block sent to the DCT circuit 13 has an even field and an odd field separately. However, the DCT circuit 13 performs the DCT transform on the unit block of 8 × 8 pixels as described above. In FIGS. 3 and 4, odd lines are indicated by solid lines, and even lines are indicated by dotted lines.

The frame memory group with motion compensator 20 includes prediction mode data MPFM / MPFD from the motion prediction mode determination circuit 23, processing mode data MDFM / MDFD from the DCT mode determination circuit 25, and The motion vector data FMMV selected by the selector 24
/ FDMV. Therefore, the frame memory group with motion compensator 20 responds to the prediction mode data MPFM / MPFD in the motion prediction and the block mode data MDFM / MDFD in the DCT processing, and performs motion compensation using the motion vector data FMMV / FDMV. Is performed.

FIG. 5 shows a second embodiment of the second high-efficiency coding apparatus according to the present invention. In FIG. 5, blocks denoted by the same reference numerals as those in FIG. 1 have the same functions. Therefore, here, blocks with numbers different from those in FIG. 1 will be described.

That is, the high-efficiency encoding apparatus shown in FIG. 5 is different from the high-efficiency encoding apparatus shown in FIG. It is determined from the information output from the motion detecting means which of the processing mode and the case where the motion compensation is the field prediction mode and the orthogonal transform blocking is the field processing mode is more efficient. A mode determination circuit 43 and a selector 24, which are processing mode selection means for selecting a good processing mode, and an odd cycle or an even field scan during a period of performing an odd field scan in the interlace of the encoding process for one frame (one screen). , The mode of the mode determination circuit 43 is set to the field prediction / An address for controlling a frame memory group so that odd fields of a macroblock are sequentially output for one frame in the above-mentioned odd cycle only in the above-mentioned odd processing, and then, even fields of a macroblock are output sequentially for one frame in the above even cycle. And an address generator 31 as a generating means.

The second embodiment is an encoding apparatus that does not divide the above-mentioned block-forming mode and the above-mentioned motion compensation mode. Of course, the same block diagram as in the first embodiment may be used, but the second embodiment is fundamentally different from the first embodiment in the operation of the address generator as described above.

By the way, the mode determination circuit 43 in FIG.
, Based on the absolute value difference sum data FMAD from the frame motion detection circuit 21 and the absolute value difference sum data FDAD from the field motion detection circuit 21, in the motion prediction process in the frame memory group 20 with a motion compensator described later, on a frame-by-frame basis. It is determined whether to perform the motion prediction process or to perform the motion prediction process in field units, and the determination result (corresponding to the prediction mode data MPFM / MPFD of the first embodiment) and the motion detection circuit (21, 22) ) Motion vector FMMV / FDMV
And an image from the frame memory group 10 to generate a difference image. Based on the difference image, the difference image is output from the frame memory group 10 and the DCT circuit 13
, The mode of the blocking process most suitable for the image subjected to the DCT process is also determined. That is, the mode determination circuit 43 determines which of the frame prediction mode and the frame processing mode PDFM is the motion prediction and the field prediction mode and the field processing mode PDFD is the motion prediction and the field prediction mode. is there. In other words, the mode determination circuit includes the motion prediction mode determination circuit 23 and the blocking mode determination circuit 2 in the first embodiment.
The configuration is such that the five functions are combined.

The specific mode can be determined in the same manner as the determination of the motion prediction mode and the blocking mode in the first embodiment, for example.

The address generator 31 outputs, for the image data stored in the frame memory group 10, a macroblock which is divided into blocks in accordance with the mode data PDFM / PDFD, for example, in units of the macroblock. The frame memory group 10 is controlled so that
That is, in the address generator 31, the mode data is the data P indicating the encoding process in frame units.
In the case of DFM, the frame memory group 10 is controlled so as to output a macroblock in which even and odd are alternately scanned as shown in FIG. As a result, the unit block of the macro block sent to the DCT circuit 13 is a combination of the even field and the odd field. Conversely, if the mode data is data PDFD indicating encoding processing in units of fields, odd fields of the macroblock are sequentially stored in the odd cycle by one.
The frame memory group 10 is controlled so as to output one frame (one screen) for one frame (one screen) and then to output one even field of the macroblock in one frame (one screen) in the even cycle. As a result, in the odd cycle, the unit block of the macro block sent to the DCT circuit 13 becomes a macro block composed of only the odd field,
In an even-numbered cycle, a macroblock is formed by only even-numbered fields. However, the DCT circuit 13 performs the DCT transform on the unit block of 8 × 8 pixels as described above.

That is, in the high-efficiency image signal encoding apparatus according to the first and second embodiments, the frame prediction mode and the field prediction mode in the motion prediction, and the DC
Since the frame processing mode and the field processing mode in the block of the T processing can be switched on a macroblock basis, the most efficient coding can be performed on a macroblock basis.

The encoding apparatuses of the first and second embodiments specifically perform, for example, the following motion prediction and DCT transform processing for each digital VTR format.

Here, in FIG. 6, FIG. 8 and FIG.
The fields constituting the frame of the I frame (I picture) are Io field (odd field of I frame) and Ie field (even field of I frame).
The fields constituting the P frame (P picture) are Po field (odd field) and Pe field (even field), and the fields constituting the B frame (B picture) are Bo field (odd field) and Be field. (Even field).

Further, in the first and second embodiments, as shown in FIG. 3 described above, the frame processing mode in the blocking is configured by combining the odd field and the even field to form the macroblock (that is, the macroblock for each frame). This is a mode in which a macro block is formed as a unit of processing, and as shown in FIG. 4 described above, in the field processing mode in the blocking, a macro block is formed separately for odd fields and even fields. In this mode, a macroblock is formed for each field and this macroblock is used as a processing unit. Therefore, for example, in the case of an I frame, the frame processing mode and the field processing mode are switched for each macroblock.

Further, in the high-efficiency coding apparatuses of the first and second embodiments, an odd cycle of a period during which an encoding process scans an odd field in an interlace and a scanning of an even field are performed for one frame. It is divided by the even cycle of the period.

In the case of the first embodiment, for example,
When a so-called 4: 2: 0 component digital VTR format is handled, as shown in FIG. 7, when the blocking is in the frame processing mode, luminance blocks Y0, Y1, and Y2 composed of odd and even fields are used.
, Y3 and the color difference blocks Cb0, Cr1 of the odd fields.
DCT processing is performed on each unit block of the macroblock composed of. On the other hand, when the blocking is in the field processing mode, the luminance block Y of each odd field
02o, Y13o and luminance block Y02e of each even field
, Y13e and the color difference block Cb of the odd field.
DCT processing is performed on each unit block of the macroblock MB composed of 0 and Cr1.

The motion prediction in the case of the example shown in FIG.
As shown in FIG. 8, in the frame prediction mode, a motion prediction MCP between an I frame and a P frame can be performed. On the other hand, in the field prediction mode, a motion prediction MCo Po between the Io field and the Po field is represented by:
Motion estimation MC between Io field and Pe field
o Pe, motion prediction MCe Po between the Ie and Po fields, and motion prediction MCe Pe between the Ie and Pe fields are possible. That is, in the case of FIG. 8, motion prediction and blocking can exist independently in the frame prediction / processing mode and the field prediction / processing mode. In the frame prediction mode, one motion vector is obtained. Are required.

Therefore, in the first embodiment, for example, when the blocking of the I frame is in the frame processing mode, the Io field and the Ie field are combined in the odd cycle to form the macroblock. Then, for example, in the odd cycle, DCT conversion (DCT is performed for each 8 × 8 unit block), quantization, and variable length coding are performed for each macroblock. On the other hand, no data is sent in the even cycle of this mode.

When the blocking is in the field processing mode, the macroblock is formed in the odd cycle in such a manner that the Io field and the Ie field are separately separated, and DCT conversion (for each macroblock) DCT is performed for each of the 8 × 8 unit blocks), quantized, and variable-length coded. On the other hand, in the even cycle of this mode, no data is sent as can be seen from FIG.

In the case of the P frame, the following processing is performed. For example, when the above-described blocking of the P frame is in the frame processing mode and the motion prediction is in the frame prediction mode, a motion vector MVP during the framing is detected in the odd cycle by using the reference image as a forward image (I-frame image). Then, the difference from the original image is encoded using the macroblock in which the Io field and the Ie field are alternately combined as a predicted image. On the other hand, no data is sent in the even cycle in this mode.

When the P frame is in the frame processing mode and the motion prediction is in the field prediction mode, in the odd cycle, the Io field and the Ie field (or the Po field and the Pe field) are used as reference images, respectively. Motion vector MPoPo between the field and the Po field, the Ie field and the P
o field, the motion vector MVe Po, between the Io field and the Pe field.
The motion vector MVe Pe between the Pe, Ie and Pe fields is detected, and among the predictions of the odd field and the prediction of the even field (for example, the average of the prediction of the even field and the prediction of the odd field), Present P
The prediction that minimizes the prediction error with the frame is selected, and Io
The difference from the original image is encoded using the macroblock in which the field and the Ie field are combined as a predicted image. On the other hand, no data is sent in the even cycle of this mode.

Further, when the above-mentioned blocking of the P frame is in the field processing mode and the motion prediction is in the frame prediction mode, in the odd cycle, the reference image is set as the I frame image (or the P frame image) and the motion between the frames is changed. The vector MVP is detected, and the difference between the macroblock composed of the Io field and the Ie field separately divided and the difference from the original image (the macroblock composed of the Po field and the Pe field divided separately) is calculated as a prediction image. Become On the other hand, in the even cycle of this mode, no data is transmitted as described above.

When the P frame is in the field processing mode and the motion prediction is in the field prediction mode, in the odd cycle, the Io field and the Ie field (or the Po field and the Pe field) are used as reference images, respectively. Motion vectors MVoPo, Io between the Ie and Po fields.
Motion vector MV between field and Pe field
o Pe, the motion vector MVe Pe between the Ie field and the Pe field is detected, and among the prediction of the odd field and the prediction of the even field (for example, the average of the prediction of the even field and the prediction of the odd field). , Select the prediction that minimizes the prediction error with respect to the current P frame,
The macroblock composed of the o field and the Ie field separately divided is used as a predicted image as an original image (Po
The difference between the field and a macroblock composed of separate Pe fields is encoded. On the other hand, no data is sent in the even cycle of this mode.

Further, in the case of the B frame, the following processing is performed. For example, when the blocking of the B frame is in the frame processing mode and the motion prediction is in the frame prediction mode, in the odd cycle, the reference image is a forward and a backward image, and a motion vector between frames, that is, an I frame and a B frame are used. And the motion vector BMVB between the P frame and the B frame.
Of the forward prediction, backward prediction, and bidirectional prediction (average of forward prediction and backward prediction), and selects the prediction that minimizes the prediction error from the current frame, and alternately combines odd and even fields. The difference from the original image is encoded using the macroblock thus obtained as a prediction image. On the other hand, no data is sent in the even cycle of this mode.

When the B frame is in the frame processing mode and the motion prediction is in the field prediction mode, in the odd cycle, the reference image is set to the front and rear images, and the prediction of the odd field is performed for each of these images. The prediction of the even field is performed, and the respective motion vectors, i.e., the motion vector FMVo Bo between the Io field and the Bo field, the Ie field and the B
o Motion vectors FMVe Bo and Io between the fields
Motion vector FM between field and Be field
VoBe, motion vector FMVeBe between the Ie and Be fields, motion vector BMVoBo between the Po and Bo fields, motion vector BMVeBo between the Pe and Bo fields.
, A motion vector BMVoBe between the Po and Be fields, and a motion vector BMVeBe between the Pe and Be fields, and the prediction of the odd field and the prediction of the even field by the respective vectors ( For example, among the predictions of the even field and the prediction of the odd field), the prediction that minimizes the prediction error with respect to the current frame is selected, and the Io field and the Io field are selected.
e field (or Po and Pe fields)
And the difference from the original image is encoded using the macroblock combined with On the other hand, no data is sent in the even cycle of this mode.

Further, when the blocking of the B frame is in the field processing mode and the motion prediction is in the frame prediction mode, in the odd cycle, the reference image is used as the front and rear images, and the motion vector between the frames, that is, the I frame and the I frame are used. The motion vector FMVB between the B frame and the motion vector BMVB between the P frame and the B frame are detected, and the current frame among the forward prediction, the backward prediction, and the bidirectional prediction (average of the forward prediction and the backward prediction) is detected. Is selected so as to minimize the prediction error, and the difference from the original image is encoded using the macroblock, which is formed by separately dividing the odd and even fields, as the predicted image. On the other hand, no data is sent in the even cycle of this mode.

When the B-frame is in the field processing mode and the motion prediction is in the field prediction mode, in the odd cycle, the reference image is set to the front and rear images, and the prediction of the odd field is performed for each of these images. The prediction of the even fields is performed, and the respective motion vectors, ie, the motion vector FMVo Bo between the Io field and the Bo field, and the motion vector FMVe Bo, I between the Ie field and the Bo field.
o The motion vector F between the field and the Be field
MVoBe, motion vector FMVeBe between the Ie and Be fields, motion vector BMVoBo between the Po and Bo fields, motion vector BMVeB between the Pe and Bo fields.
o, a motion vector BMVoBe between the Po field and the Be field, and a motion vector BMVeBe between the Pe field and the Be field are detected, and the prediction of the odd field and the prediction of the even field by the respective vectors are performed. (For example, the average of the prediction of the even field and the prediction of the odd field), the prediction that minimizes the prediction error from the current frame is selected, and the Io field and the Io field are selected.
e field (or Po and Pe fields)
Encodes a difference from an original image using the macroblock separately configured as a predicted image. On the other hand, no data is sent in the even cycle of this mode.

However, in the case of the first embodiment, as can be seen from FIG. 8, the motion prediction between the Io field and the Ie field, the motion prediction between the Po field and the Pe field, the Bo field and the Be field Motion cannot be predicted during

In this case, by using the second embodiment, prediction from an odd field to an even field can be performed in each picture. That is, as shown in FIG. 9, for example, when the above-mentioned blocking is in the frame processing mode, in the odd cycle, luminance blocks Y0, Y1, Y2, and Y3 composed of odd fields and even fields, and color difference blocks Cb0, DCT processing is performed on each unit block of the macro block MB composed of Cr1,
Furthermore, when the blocking is in the field processing mode,
In the odd cycle, DCT processing is performed on each unit block including the luminance blocks Y02o and Y13o of the odd field and the color difference blocks Cb0 and Cr1 of the odd field. Thereafter, each unit block of each of the luminance blocks Y02e and Y13e of the even field is subjected to DCT processing in an even cycle.

The motion estimation in the case of the example of FIG.
As shown in FIG. 9, each motion prediction MVP, MCo P in FIG.
o, MCo Pe, MCe Po, MCe Pe, and Io
Motion prediction between field Io and field Io
And motion prediction SMCP between the Po and Pe fields is possible.

Therefore, in the second embodiment, for example,
When the blocking of the frame is in the frame processing mode, the Io field and Ie are used in the odd cycle.
Fields are combined to form the macroblock. For example, in the odd cycle, DCT conversion is performed for each macroblock (however, DCT is performed for each 8 × 8 unit block), quantization, and variable length coding. Is made. On the other hand, no data is sent in the even cycle of this mode. When the blocking is in the field processing mode, only odd fields of the macroblock are coded in the odd cycle in the same manner. Thus, for example, at the end of the odd cycle, the entirety of the Io field and the macroblock portion of the Ie field in the frame processing mode are obtained on the decoder side described later. Furthermore,
In the even cycle of the I frame, motion prediction is performed on the macroblock of the Ie field in the field processing mode using the Io field as a reference image, and the motion vector SMVI and a difference image from the predicted image are encoded.

In the case of the P frame, the following processing is performed. For example, when the blocking of the P frame is in the frame processing mode and the motion prediction is in the frame prediction mode, in the odd cycle, a motion vector MVP between frames is detected using the reference image as a forward image (I-frame image). Then, the difference from the original image is encoded using the macroblock obtained by combining the Io field and the Ie field as a predicted image. On the other hand, no data is sent in the even cycle of this mode as described above.

When the blocking is in the field processing mode and the motion prediction is in the field prediction mode, in the odd cycle, the Io field and the Ie field (or the Po field and the Pe field) are used as reference image images, respectively, and the Io field and the Io field are used. The motion vector MPo Po between the Po field and the motion vector MPo Po between the Ie field and Po
Detecting a motion vector MVe Po between the field and
From the prediction of the odd field and the prediction of the even field and both predictions (for example, the average of the prediction of the even field and the prediction of the odd field), the prediction that minimizes the prediction error with the odd field of the current frame is selected, and the prediction is performed. Encode the difference from the image. On the other hand, in the even cycle of this mode, the motion vector MVo Pe between the Io field and the Pe field, the motion vector MVe Pe between the Ie field and the Pe field, and The motion vector SMVP between the Po field and the Pe field is detected, and the prediction of the odd field, the prediction of the even field, and the prediction of the odd field of the current frame (the motion prediction from the Po field performed only in the even cycle) by the respective vectors are performed. A prediction that minimizes the prediction error is selected from among the predictions obtained by averaging the two predictions, and the difference from the prediction image is encoded.

Further, for example, when the above-mentioned blocking of the B frame is in the frame processing mode and the motion prediction is in the frame prediction mode, in the above-mentioned odd cycle, the reference image is used as a front and rear image, and a motion vector between frames, that is, an I frame is used. Motion vectors FMVB and P between the B frame
A motion vector BMVB between a frame and a B frame is detected, and a prediction that minimizes a prediction error with respect to a current frame is selected from forward prediction, backward prediction, and bidirectional prediction (average of forward prediction and backward prediction). Then, the difference from the predicted image is encoded. On the other hand, no data is sent in the even cycle of this mode.

When the above-mentioned blocking is in the field processing mode and the motion prediction is in the field prediction mode, the odd picture and the even field are predicted for these pictures by making the reference picture forward and backward in the odd cycle, respectively. The motion vector FMVo between the Io and Bo fields.
Motion vectors FMVeBo between the Bo and Ie fields and the Bo field, motion vectors BMVoBo between the Po and Bo fields, and motion vectors BMVeBo between the Pe and Bo fields are detected. Thereafter, in the same manner as described above, the prediction that minimizes the prediction error is selected, and the difference from the prediction image is encoded. Further, in the even cycle of this mode, the motion vector FMVoBe between the Io field and the Be field is set.
, Ie and Be fields, the motion vector FMVeBe, between the Po and Be fields, the motion vector BMVoBe, Pe field and B
Each prediction by the motion vector BMVeBe between the e field and the prediction of the odd field of the current frame (that is, prediction by the motion vector SMVB between the Bo field and the Be field) is also performed to minimize the prediction error. A prediction is selected, and the difference from the prediction image is encoded.

In the first embodiment, for example, a so-called 4: 2: 2 component digital VTR is used.
When the format is handled, as shown in FIG. 11, in the frame processing mode, the luminance blocks Y0, Y1, Y2, Y3 composed of odd and even fields are used.
DCT processing is performed on each unit block of a macroblock composed of color difference blocks Cb01, Cr01, Cb23, and Cr23 composed of odd and even fields.
In the field processing mode, a macro composed of the luminance blocks Y02o and Y13o of the odd fields and the color difference blocks Cb0123o and Cr0123o of the odd fields, the luminance blocks Y02e and Y13e of the even fields, and the color difference blocks Cb0123e and Cr0123e of the even fields. DCT processing is performed on each unit block of the block.

The motion prediction in the case of the example of FIG. 11 is as shown in FIG. 8 described above. However, this FIG.
Also in the case of 1, the motion prediction between the Io field and the Ie field, the motion prediction between the Po field and the Pe field, and the motion prediction between the Bo field and the Be field cannot be performed.

Therefore, in this case, the second embodiment may be used as described above. That is, for example, as shown in FIG. 12, when the above-mentioned blocking is in the frame processing mode, the luminance blocks Y0, Y1, Y2, Y3 and the color difference blocks Cb01, Cr01, Cb23, composed of odd and even fields in the odd cycle. DCT processing is performed on each unit block of the macro block composed of Cr23,
Further, when the blocking is in the field processing mode, each luminance block Y02 of the odd field is used in an odd cycle.
o, Y13o and each color difference block Cb0 of the odd field.
DCT processing is performed on each unit block of 123o and Cr0123o.
Thereafter, each unit block of the luminance blocks Y02e and Y13e of the even field and the chrominance blocks Cb0123e and Cr0123e of the even field is subjected to DCT processing in an even cycle.

The motion prediction in the case of the example shown in FIG.
Same as 0.

Further, in Embodiments 1 and 2 described above,
When handling the 4: 2: 2 component digital VTR format, in addition to the processing shown in FIGS. 11 and 12, for example, as shown in FIG. When performing motion prediction of a field, a certain macroblock MB
(i, j) and the macroblock MB (i + 1,
j) may be used as a set to perform the odd-field motion prediction and the even-field motion prediction on the macroblock set MBg.

FIG. 14 shows a part of the macroblock extracted from the frame in the example of FIG. It is assumed that the process proceeds in the direction of the arrow in FIG. That is, FIG. 14 shows that a certain macroblock MB (i, j) has the next macroblock MB (i, j + 1) and the macroblock MB (of the next line) located below them (of the next line). i + 1,
j) and MB (i + 1, j + 1).

In the macro block shown in FIG. 14, for example, in the case of the frame processing mode, each macro block MB (i, j), MB (i, j + 1),..., MB (i
+ 1, j), MB (i + 1, j + 1)... For each luminance block Y
0, Y1 and the color difference blocks Cb01, Cr01 are subjected to DCT processing. Therefore, in the case of the frame processing mode,
The processing of each macroblock is not affected by the processing mode of other macroblocks.

On the other hand, in the case of the field processing mode, as shown in FIG.
g, the macroblocks constituting the set of macroblocks MBg are replaced by the macroblocks MB of the odd field.
go and the macroblock MBge of the even field, and the luminance blocks Y0o and Y1o and the color difference blocks Cb01o and Cr01o in the macroblock MBgo of the odd field are represented by D.
Perform CT processing. Here, for example, the set of macroblocks MBg is the macroblock MB (i, j) shown in FIG.
B (i + 1, j), the luminance blocks Y0o and Y1o in the macroblock MBgo of the odd field in the macroblock MBg are odd numbers of the macroblock MB (i, j). It consists of a luminance block of a field and luminance blocks of an odd field of the macroblock MB (i + 1, j), and the color difference blocks Cb01o and Cr01o in the macroblock MBgo of the odd field.
Are the chrominance blocks of the odd fields of the macroblock MB (i, j) and the macroblock MB (i + 1, j)
Are composed of color difference blocks of odd fields.
Similarly, the luminance blocks Y0e and Y1e in the even-field macroblock MBge are the even-field luminance blocks of the macroblock MB (i, j) and the even blocks of the macroblock MB (i + 1, j). Chrominance blocks Cb01e and Cr01e in the even-field macroblock MBge.
Is composed of a color difference block of the even field of the macro block MB (i, j) and a color difference block of the even field of the macro block MB (i + 1, j).

As described above, motion estimation and DC
The relationship between the T conversion and each processing mode is as described below. That is, in the coding apparatus of the present embodiment, for example, when the macroblock MB (i, j) is subjected to the DCT transform in the frame processing mode in the motion prediction in the frame processing mode, for example, the frame memory with the motion compensator is used. The image decoded in the group 20 is used as a reference frame,
The difference between the predicted image extracted from the reference frame and the input image (original image) is subjected to DCT. And that DC
Transmit the T coefficient and the frame motion vector.

Also, for example, the macro block MB
In (i, j), in motion prediction in the field processing mode,
In the case of the DCT transform in the field processing mode, in the macroblock MB (i, j), the difference between the predicted image extracted from the odd field and the original image of the odd field is expressed by:
The motion vector of the odd field is encoded. Also,
In the macroblock MB (i + 1, j), the difference between the predicted image extracted from the even field and the original image of the even field, and the motion vector of the even field are encoded.

Further, for example, the macro block MB
In (i, j), in motion prediction in the field processing mode,
In the case of the DCT transform in the frame processing mode, in the macroblock MB (i, j), the frame difference between the predicted image and the input image with respect to the position of the macroblock MB (i, j) extracted from the reference frame, and the odd number The motion vector of the field and the motion vector of the even field are transmitted. In the macro block MB (i + 1, j), the macro block MB (i + 1, j) extracted from the reference frame is used.
The frame difference between the predicted image and the input image for the position of j) is transmitted.

Further, for example, the macro block M
In B (i, j), in motion prediction in the frame processing mode,
In the case of the DCT transform in the field processing mode, in the macroblock MB (i, j), the difference between the predicted image extracted from the odd field and the original image of the odd field is expressed by:
The frame motion vector of the macroblock MB (i, j) and the frame motion vector of the macroblock MB (i + 1, j) are transmitted. Further, the macro block MB (i +
In (1, j), the difference between the predicted image in the odd field and the input image is transmitted.

By the way, in the encoding apparatus of the present embodiment, the present code is realized by adding an extension bit to the conventional macro block type to obtain compatibility with the conventional one.

That is, in the case of the first embodiment, for example, in the B frame, there are three macroblock types, ie, pre-prediction, post-prediction, and both predictions as described above. Since there are two types of prediction, odd field and even field, the present code is realized by adding an extension bit for recognizing either prediction. Since there are two types of prediction in this case, it is sufficient to add one bit for the extension bit in one direction (previous and post-prediction). For example, in the case of prediction from an odd field in pre- or post-prediction, code 1 may be added to the conventional macroblock type as an extension bit in the case of prediction from an even field, as code 0. Also, in both predictions, both extension bits are added for the front or rear prediction.

In the frame prediction mode, an extension bit is not added and a conventional bit stream (MPEG)
It has the same format as The above is similarly applied to the case of a P frame.

Next, in the case of the second embodiment, for example, in the B frame, the macroblock type includes pre-prediction, post-prediction, and both predictions as described above. An extension bit must be added to the macroblock type to recognize whether the prediction is from the even field, the prediction from the even field, or the prediction from the odd field in the own frame. That is, in the field prediction mode of the previous prediction, since there is a prediction from within the own frame, one or two extended bits are required to represent three types of predictions including the odd and even numbers with the extended bits. In the field prediction mode of the post-prediction, since there are only two types, odd and even, the extension bit is always 1
A bit is needed. For example, in the previous prediction, a code 1 is added for prediction from an odd field of the previous frame, a code 01 is added for prediction from an even field of the previous frame, and a code 11 is added for prediction from an odd field of the current frame. In the post-prediction, a code 1 may be added to the conventional macroblock type as an extension bit in the case of prediction from an odd field of the subsequent frame, and a code 0 in the case of prediction from an even field of the subsequent frame.

In the frame prediction mode, an extension bit is not added and a conventional bit stream (MPEG)
It has the same format as Also, in both predictions, both extension bits are added for the front or rear prediction. The above is P
The same applies to frames.

Further, as a modification, the number of extension bits in the case of the pre-prediction can be reduced to one bit. That is, in the even cycle in the field prediction mode, as shown in FIG. 16, the prediction from the odd field of the previous frame which is farthest in time and position is abolished, and the number of previous predictions is reduced to two. The pre-prediction mode can be transmitted by extending the bits. Specifically, in the previous prediction in the odd cycle, the code is 1 for prediction from the odd field of the previous frame, the code is 0 for prediction from the even field of the previous frame, and in the even prediction in the previous prediction, the code is 0. In the case of prediction from an odd field of a frame, code 1 is used. In the case of prediction from an even field of the previous frame, code 0 is used. In the case of prediction, code 1 is used for prediction from an odd field of the next frame. In the case of prediction from an even field, the code 0 may be added to a conventional macroblock type as an extension bit.

FIG. 17 is a block diagram of a decoder (a first decoding device and a second decoding device) for an image signal corresponding to the encoding devices of the first and second embodiments. The high-efficiency decoding apparatus according to the present embodiment receives and decodes coded image data to be reproduced and header information, decodes the detected motion vector information, and performs motion compensation and field compensation in units of frames in a macroblock. The motion prediction mode information indicating which one of the motion compensation efficiencies is more efficient, and which one of the efficiency of the blocking in the orthogonal transformation in units of frames in the macroblock and the efficiency of the blocking in the orthogonal transformation in units of fields in the macroblock is higher. Inverse variable length coding circuit 5 for outputting block mode information indicating whether or not it is good and macroblock address increment in header information of the macroblock.
1 and the address increment value in the frame buffers 61, 62, and 64 that store the image decoding data from the macroblock address increment, obtain the start address of each macroblock, and calculate the start address. The frame buffers 61, 62, 64
And the address generators 81, 82, and 83, and the relative addresses of the macroblocks other than the head address are added to the frame buffers 61, 62, and 64 to access data, and the detected motion vector and the motion prediction mode information are added. A motion compensation frame or inter-field prediction corresponding to the mode information, and sends a motion-compensated image signal to the frame buffers 61, 62, and 64. , 60, 63, 65, 66.

In FIG. 17, the data encoded by the high-efficiency encoding devices of the first and second embodiments is temporarily
It is recorded on a storage medium such as a CD. The coded data reproduced from the CD or the like is first decoded by the inverse variable length coding circuit 51 via the input terminal 50 into header information and the like for each sequence, each frame group, and each frame. In the odd cycle of the frame, header information is decoded for each slice (group of macroblocks), and the quantization width is included in the header of this slice. And for each macroblock, the address of the macroblock,
The frame processing mode / field processing mode and the macroblock type indicating the decoding method are decoded, and the quantization width is decoded when updating.

If the macroblock is in the frame processing mode, the entire macroblock is decoded in the odd cycle, and nothing is decoded in the even cycle. When the blocking is in the field processing mode, only the block including the odd field in the macro block is decoded in the odd cycle, and the block including the even field is decoded in the even cycle.

The image information is decoded through an inverse quantizer 53 for performing an inverse quantization process and an inverse DCT circuit 54 for performing an inverse DCT transform process, and it is determined whether or not the image is a difference image according to a macroblock type. According to the determination result, the adder 56 switches the mode switch 57 which switches between adding to the reference image (corresponding to non-intra / intra / intra in MPEG coding) and not adding. The decoded image is input to the frame buffer 64 or 61 in the case of an I frame or a P frame (alternately every time the I frame and the P frame are processed), and
In the case of a frame, it is input to the frame buffer 62.
Each frame buffer is composed of two field buffers, and odd / even field images are stored separately in the respective field buffers. The writing to the frame buffer is controlled by the switch 58.

At this time, the address to be written into the frame buffer is given by the address generator. This address generator calculates the address increment value in the frame buffer from the macroblock address increment in the header information of the macroblock, and obtains the head address of each macroblock.

Further, the quantization width data is stored in the memory 52 for one field. This quantization width data is sent to the inverse quantizer 53 via a switch 55 that is switched according to the output of the inverse variable length encoding circuit 51. Here, in the even cycle, only the macroblock processed in the field processing mode is decoded.
A macroblock type with a macroblock address to be decoded for each macroblock and a motion vector required for the prediction method indicated by this are decoded, and a difference image further transmitted from the reference field to a motion-compensated image is added, Obtain a playback image.

Here, if the encoding apparatus uses an encoding method in which the data of the quantization width of the even field is transmitted independently of the odd field in the even cycle, the data of the quantization width transmitted in the odd cycle is stored. Therefore, the memory 52 for one field is not required.

Each of the frame buffers 64, 6
The data of the motion compensation processing circuits 65, 66,
The motion is compensated by 59, 60 and 63. At this time, each motion compensation circuit performs motion compensation /
Toggles field motion compensation.

These motion-compensated images are sent to selected terminals of the changeover selection switches 67, 68, 71. These changeover selection switches 67, 68, and 71 are switched so that a reference field or a frame indicated by a macroblock type decoding method can be extracted. Here, the switch selection switch 71 is supplied with a signal which is obtained by adding the outputs of the switch selection switches 67 and 68 by the adder 69 and then halving the result by the divider 70, and the output of the switch 67. Is done. The output of the switch 71 is sent to the switch 57.

Further, each of the frame buffers 64, 61, 6
The output of 2 is sent to the display 73 via the changeover selection switch 72. The output of the switch 72, which is switched so as to be displayed in the order of reproduced images, not in the order of decoding, is supplied to the display 73. As a result, an image is obtained.

As described above, for example, as shown in FIG.
In such a case, when one frame is viewed, there is movement between fields, so such a portion becomes a comb-shaped KS.
According to the present embodiment, such a moving part is encoded in the field processing mode, so that it can be processed as a blur-free image for each field, and the motion compensation between odd / even allows for high efficiency and high efficiency. You can play high-quality videos. That is, as shown in FIG. 18, for example, in an odd cycle, a moving part is processed in a field processing mode and a stationary part is processed in a frame processing mode. In addition, the part where the image has already been made in the even cycle,
The hatched portion in FIG. In FIG. 19, the portion other than the hatched portion, that is, the moving portion is decoded by motion compensation.

In the present embodiment, since only the macroblock processed in the field processing mode is decoded in the even cycle, it is necessary to know the macroblock address. There are two methods of knowing the macroblock address. One is the method of transmitting the macroblock address for each even-cycle macroblock described above, and the other is one-field processing in the odd cycle. In this method, mode / frame processing mode information is stored, and the address of a macroblock in the field processing mode is converted from a row of each processing mode. The former advantage is that no additional memory is required, and the latter advantage is that transmission information does not increase.
Similarly, the quantization width can be realized by transmitting each macroblock without using the method of storing one field in the odd cycle described above.

As described above, the first embodiment,
According to 2, the processing of one frame is divided into two cycles of an odd cycle and an even cycle. In the odd cycle, the frame processing mode and the field processing mode are switched in macroblock units. In the frame processing, both the odd field and the even field are used. In the field processing, only the odd fields are decoded in the field processing, and the quantization width in this cycle is stored. In the next even cycle, only the macroblock in the field processing mode is motion-compensated using the stored information. Since the reproduced image is decoded by using this method, efficient encoded data can be transmitted. That is, a high-quality moving image can be reproduced with a small amount of transmission information.

Next, as Embodiments 3 to 6, high-efficiency image signal encoding apparatuses according to the present invention and third to sixth decoding apparatuses corresponding thereto will be described in detail.

FIG. 20 is a block circuit diagram of a high efficiency coding apparatus according to the third embodiment. In FIG. 20, blocks denoted by the same reference numerals as those in FIGS. 1 and 5 have the same function. Accordingly, here, blocks with different numbers from those in FIGS. 1 and 5 will be described. This figure 2
The high-efficiency coding apparatus of 0 performs the process of coding all macroblocks in one frame in the above-described frame processing mode, in addition to the blocks with the same numbers as those of the high-efficiency coding apparatuses of FIGS. Either the first restricted mode in which inhibition is performed, or the second restriction mode in which the process of predicting the even field of the current frame from the odd field of the frame currently being encoded in all macroblocks in one frame is inhibited. Encoding mode determination circuit 34, which is a restriction mode selecting means for selecting a mode of good restriction.
(A) and the selector 24, when the first restriction mode is selected for one frame (one screen), outputs the odd field components of all the macroblocks, and then outputs the even field components of all the macroblocks. If the second restriction mode is selected, a frame is output such that one macroblock is sequentially output in units of frames composed of both odd field and even field components of all macroblocks. An address generator 35 which is an address generating means for controlling a memory group
(A).

That is, in the third high-efficiency encoding apparatus according to the third embodiment, in encoding of a moving image in which one frame is composed of two fields, odd fields (first fields) are used for all blocks in the frame. , An even field (second field) is divided into blocks, and an encoding unit (first restriction mode) that enables motion prediction from the first field to the second field;
Encoding means (second restriction mode) for switching the division / non-division of the second field on a macroblock basis to form a block, and these encoding means are adaptively switched for each frame. Things. Furthermore,
In this case, 1-bit information (information indicating the selected mode) indicating these encoding means is added to the code.

FIG. 21 is a block circuit diagram of a high-efficiency coding apparatus according to the fourth embodiment. Note that FIG.
Blocks denoted by the same reference numerals in FIG. 1 as those in FIGS. 1 and 5 have the same function. Accordingly, here, blocks with different numbers from those in FIGS. 1 and 5 will be described. The high-efficiency encoding apparatus of FIG. 21 encodes all macroblocks in one slice in the above-described frame processing mode, except for the blocks with the same numbers as those of the high-efficiency encoding apparatuses of FIGS. Either the first restriction mode in which the processing is prohibited or the second restriction mode in which the processing of predicting the even field of the current frame in all the macroblocks in one slice from the odd field of the frame currently being encoded is prohibited. When the first restriction mode is selected for one slice, the encoding processing mode determination circuit 34 (b) and the selector 24, which are restriction mode selection means for selecting a mode of efficient restriction, select all macros. Output the odd field components of the block, then output the even field components of all macroblocks, and the second restricted mode is If selected, an address as address generation means for controlling a frame memory group so as to sequentially output one slice of macroblocks in units of frames composed of both odd field and even field components of all macroblocks. Generator 35
(B).

That is, in the fourth high-efficiency coding apparatus according to the fourth embodiment, in coding of a moving image in which one frame is composed of two fields, odd fields (first fields) are used for all blocks in a slice. , The even field (second field) is divided into blocks,
Encoding means (first restriction mode) for enabling motion prediction from the first field to the second field, and encoding for switching the first field and the second field into and out of division on a macroblock basis to form a block (Second restriction mode), and these encoding means are adaptively switched for each frame. Further, in this case, 1-bit information indicating the encoding means (information indicating the selected mode) is added to the code.

First, Examples 3 and 4 will be described in more detail with reference to the drawings.

FIG. 20 shows a third image signal high-efficiency encoding apparatus according to the third embodiment of the present invention, which is a macroblock (for example, raster scan) consisting of a two-dimensional array of a plurality of pixels smaller than one screen. This is a high-efficiency image signal encoding apparatus that performs encoding in units of (blocks each including 16 × 16 pixels in a spatial arrangement of input image data in order).

The third high-efficiency coding apparatus for image signals according to the third embodiment shown in FIG. 20 is a frame (one screen) composed of a plurality of unit blocks (macroblocks) of 16 × 16 pixels. Are stored as a plurality of original images, a frame motion detection circuit 22 which is means for detecting a motion vector between frames and an absolute value difference sum of each pixel in macroblock units, and a frame memory group 10 in macroblock units. It has a motion detecting means comprising a motion vector between fields which are obtained by dividing the scan of the pixels of the frame by odd or even numbers, and a field motion detecting circuit 21 which detects the sum of absolute value differences of each pixel.

The apparatus of this embodiment performs motion compensation in either the frame prediction mode in which motion compensation is performed in units of frames in the macroblock or the field prediction mode in which motion compensation is performed in units of fields in the macroblock. In this case, first mode selecting means for judging whether or not efficiency is high and selecting an efficient prediction mode, and performing block processing so as to perform orthogonal transform (for example, discrete cosine transform; DCT) in units of frames in the macroblock. The motion detection unit and the first mode selection unit determine which of a frame processing mode and a field processing mode in which the orthogonal transformation is performed in units of fields in the macroblock is more efficient in performing the orthogonal transformation. Judgment using information output from A frame / field mode decision circuit 33 comprising a second mode selecting means for selecting the mode of good blocking of.

Further, in the third embodiment, together with the motion detecting means and the frame / field mode determination circuit 33,
The third encoding device adaptively switches the blocking of the orthogonal transform to the frame processing mode or the field processing mode for each macroblock in one frame, and encodes each macroblock based on each mode. Second
And the odd field in the macroblock in the odd cycle (odd cycle) of the period in which the orthogonal transform is blocked in all the macroblocks in one frame in the field processing mode and the odd field in the interlace is scanned. Even cycle (even cycle) of the period during which only one frame is encoded and then scanning of the even field in interlacing is performed
To determine which one of the first restriction mode, which encodes even-numbered fields in a macroblock for one frame, is more efficient in encoding, and selects a more efficient restriction mode. It has a judgment circuit 34 (a).

In the fourth encoding apparatus shown in FIG. 21, the determination circuit 34 (b) performs the above-described orthogonal transform blocking for each macroblock in one slice in the frame processing mode or the field processing mode. A second restriction mode in which each macroblock is coded based on each mode by adaptively switching to each other, and the above-mentioned orthogonal processing of all macroblocks in one slice is blocked in the field processing mode, and an odd number in the interlace is used. Only the odd field in the macroblock is encoded for one slice in the odd cycle (odd cycle) of scanning the field, and the even field in the macroblock is encoded in the even cycle (even cycle) of the scanning of the even field in interlacing. For one slice Either the second limitation mode, it is determined whether efficient when encoding, has a limitation mode selecting means for selecting a restriction mode efficiency.

FIG. 22 shows a modification of the restricted mode selection means of the third embodiment. In the third encoding device, data FDAD and FMAD obtained for each macroblock are integrated for each frame. And integrated data SFD
When AD and SFMAD are obtained and the offset value T is set, the second restriction mode is selected when the integrated data SFDAD is smaller than FMAD + T, and the first restriction mode is selected otherwise.

Further, in the third encoding device, the data FDAD and FMAD obtained for each macroblock are integrated for each slice, and the integrated data SFDAD and SFM are obtained.
When AD is obtained and the offset value T is obtained, the integrated data SF
When DAD becomes smaller than FMAD + T, the second restriction mode is selected, and otherwise, the first restriction mode is selected.

Similarly, the flowchart shown in FIG. 23 is a modified example of the mode determination in the restricted mode selecting means of the third embodiment. In the third encoding device, the odd field (first field) of the current frame to be encoded is used. The restriction mode is selected by using a motion vector from the to the even field (second field). FIG. 24 shows a motion vector Mv (FIG. 24) from the odd field to the even field.
In shown is indicated by the motion vector Mv _1-2).

In the flowchart of FIG. 23, first, in step S21, this motion vector is obtained for all macroblocks in a frame to be encoded.
Then, in step S22, the median (median) of the horizontal (x) component and the vertical (y) component of the motion vector is obtained. Here, the median of the horizontal component is calculated as follows. First, the horizontal components of the motion vectors are arranged in descending power order. Then, the value of the data at the center becomes the median Mv_x of the horizontal component. Similarly, the median Mv_y of the vertical component is obtained.

The vector MV (Mv
_X, Mv_y) are parameters representing the motion of the entire screen. Here, the magnitude r of the vector MV is introduced as a parameter representing the magnitude of the motion of the entire screen. The magnitude r is obtained by the equation (3) of the equation (3).

[0147]

(Equation 3)

Next, in step S24, the size r
The restriction mode is switched by the switch. For example, the first restriction mode is advantageous for an image with fast movement, and the second restriction mode is advantageous for an image with little movement. Therefore, if r is equal to or less than a certain threshold, the second restriction mode is used. Select the restriction mode.

That is, if r <= threshold, the second restriction mode of step S26 is set, and if r> threshold, the first restriction mode of step S25 is set.

In the fourth encoding device, the restriction mode is selected based on the motion vector from the odd field to the even field of the current frame to be encoded in the same manner. A motion vector Mv from odd field to even field over all macroblocks in the slice to be encoded
, And the median (Mv_x,
Mv_y). Similarly, the size r is obtained,
When the magnitude r is equal to or less than a certain threshold value, the second restriction mode is selected, and otherwise, the first restriction mode is selected.

Similarly, the flowchart of FIG. 25 is a modification of the mode selection in the restricted mode selection means of the third embodiment, and the third encoding device performs the correlation between the odd field and the even field of the current frame to be encoded. Use to select the restriction mode.

That is, the correlation between the odd field and the even field is performed by the method shown in FIG. This is a well-known method for selecting a mode of a macroblock in the international standardization of moving picture coding compression currently recommended in ISO / IEC JTC1 / SC2 / WG11. In the present embodiment, this is extended and adopted to select a frame restriction mode.

In the flowchart of FIG. 25, first, var1 and var2 are obtained in step S1. Then, in step S2, the number of macroblocks in the current frame that satisfies var1> = var2 + offset is obtained. This is num_field_mb.

Here, since macroblocks satisfying var1> = var2 + offset have high correlation between fields, it is more advantageous to set the restriction mode to the first restriction mode. Therefore, in step S3, when num_field_mb is equal to or less than a certain threshold value, the second restriction mode is selected. Otherwise, the first restriction mode is selected, and the process is performed again.

That is, num_field_mb <= threshol
In the case of d, the second restriction mode of step S5, num_fi
If eld_mb> threshold, the first restriction mode is entered in step S4.

In the fourth encoding device, the number num_field_mb of macroblocks in the slice to be encoded that satisfies var1> = var2 + offset is similarly obtained, and the restriction mode is selected based on this value. num_fiel
If d_mb is equal to or smaller than a certain threshold value, the second restriction mode is selected. Otherwise, the first restriction mode is selected and the processing is performed again.

Similarly, the flowchart of FIG.
Is a modification of the mode selection in the restricted mode selection means, wherein the third encoding device performs the decoding of the already decoded image referred to by the image and the motion vector for each macroblock in the current frame encoded in step S11. The difference is calculated, the sum of squares of the difference is obtained, and the limit mode is selected in step S12 by using the difference. In each of the first and second restriction modes, the sum of squares of the difference is calculated, and the restriction mode of the smaller square sum (steps S13 and S1) is calculated.
Select 4).

In the fourth encoding device, similarly,
Similarly, the sum of squares of the difference in the slice to be encoded is obtained, and the restriction mode having the smaller value is selected.

Similarly, the flowchart of FIG.
Is a modification of the mode selection in the restriction mode selection means, wherein the third encoding device selects the restriction mode using the correlation between the odd field and the even field of the current frame. First, step S51 in the flowchart of FIG.
And var1 and var2 are obtained.

Then, in step S52, the data is added over all the macroblocks existing in the current frame to be encoded. Next, in step S53, the restriction mode is selected based on the relationship between the values var1 and var2 thus determined. That is, var1> = var2 + offs
If et, the first restriction mode (step S54)
Otherwise, the second restriction mode (step S55) is selected.

In the fourth coding apparatus, v is applied to all macroblocks included in a slice to be coded.
Add ar1 and var2 to obtain Var1 and Var2. Then, the restriction mode is selected from the relationship between Var1 and Var2. When Var1 <= Var2 + offset, the first restriction mode is selected. Otherwise, the second restriction mode is selected.

Similarly, the flowchart of FIG.
The third encoding device selects a restricted mode using a correlation between a motion vector and a first field and a second field of a current frame to be encoded. First, step S31
The motion vector of each macroblock obtained in
32 is a unit vector (n_x [i], n_y [i])
Convert to Assuming that the motion vector is (mv_x, mv_y), Equation (4) of Equation 4 and Equation (5) of Equation 5 are obtained.

[0163]

(Equation 4)

[0164]

(Equation 5)

Then, in step S33, the sum vector SMV (S_x, S_
y). In step S34, a value obtained by dividing the size of the sum vector SMV by the number of macroblocks num_MB is set to R as shown in Expression (6) of Expression 6.

[0166]

(Equation 6)

This value R is a statistic used when testing the anisotropy of the vector. For example, when the motion vector has anisotropy, that is, when the entire image largely moves,
The value R takes a large value.

The value R and the value in FIG.
The restriction mode is determined in step S36 from the relationship of Var2 obtained in the flowchart of FIG. For example, if Var2 is equal to or less than a certain threshold and R is equal to or less than a certain threshold, the second restriction mode (step S38) is selected. Otherwise, the first restriction mode (step S37) is selected. To do.

In the fourth encoding apparatus, R and Var2 are similarly obtained in the slice to be encoded, and the restricted mode is selected. If Var2 is equal to or less than a certain threshold value and R is equal to or less than a certain threshold value, the second restriction mode is selected. Otherwise, the first restriction mode is selected.

Further, the apparatus of this embodiment recognizes whether the cycle is the odd cycle or the even cycle, and when the limited mode is the second limited mode, the mode is switched to the orthogonal transform blocking mode in the odd cycle. The frame memory group 10 is controlled so as to output macroblocks correspondingly divided into blocks. When the limited mode is the first limited mode, the odd and even cycles correspond to the field processing mode. An address generator 35 for controlling the frame memory group 10 so as to output macroblocks that have been divided into blocks, and processing mode information (frame motion prediction / frame orthogonal transform / field motion prediction) selected by the processing mode selecting means.・ Field processing mode data) and a motion compensation frame corresponding to the mode information. A motion compensation means for performing a beam or inter-field prediction motion compensator with a frame memory group 20
It is provided with.

In the encoding device of the present embodiment, FIG.
As shown in FIG. 4, for example, three of intra-frame coding (I frame or I picture), unidirectional prediction inter-frame coding (P frame or P picture), and bidirectional inter-picture coding (B frame or B picture) Encoding can be performed as follows. Each picture is divided into 8 × 8 pixels and is divided into 2 × 2 blocks (that is, 16 × 8 blocks).
A macro block is composed of 16 pixels).

In the coding apparatus according to the third embodiment, the first mode selection means selects which of the frame prediction mode and the field prediction mode is more efficient in performing motion compensation. The second mode selection means can select which of the frame processing mode and the field processing mode is more efficient in performing orthogonal transform. The first and second mode selections are made by the above-described frame / field processing mode determination circuit 33.

The encoding apparatus according to the third embodiment is configured to perform the encoding in each of the two restriction modes with higher efficiency together with the mode selection processing by the processing mode selection means. That is, as described above, as the first restriction mode, all macroblocks in one frame are subjected to orthogonal transform blocking in the above-described field processing mode, and odd-numbered fields (first fields) are scanned in odd numbers. Only the odd field in the macroblock is encoded for one frame in the cycle, and then the even field in the macroblock is encoded for one frame in the even cycle of the scan of the even field (second field). Further, as described above, as the second restriction mode, each macroblock is encoded by adaptively switching between the frame processing mode and the field processing mode for each macroblock in one frame. The restriction mode selecting means determines which of the first and second restriction modes is more efficient for encoding, and selects the more efficient restriction mode.

That is, in the second restriction mode, each frame is divided into a first field (odd field) and a second field (even field) without being divided into blocks and encoded (the frame processing mode). Of the modes in which each frame is divided into first and second fields and divided into fields to be coded (the above-described field processing mode), for example, in a macroblock having a small image motion, the above-described frame processing mode is used. For example, for a macroblock having a large image motion, a process of adaptively switching to use the field processing mode is performed.

Therefore, when the frame processing mode is selected in the second restriction mode, for example, in the motion prediction of the P and B frames, motion prediction is performed from the previous and next frames, and a difference image from the predicted image is obtained. It is orthogonally transformed (DCT). Further, when the field processing mode is selected in the second restriction mode, for example, the motion prediction of the P and B frames is performed by the first macro block.
For each of the field and the second field, motion is predicted from the first or second field of the previous and subsequent frames, and a difference image from the predicted image is subjected to DCT. From this, it can be said that the second restriction mode is encoding without intra-frame inter-field prediction. Also,
In the second restriction mode, the encoding process is performed in the odd cycle. The second restriction mode can be called encoding without intra-frame inter-frame prediction.

Here, in the second restriction mode, motion prediction between fields in a frame (between an odd field and an even field in the same frame) cannot be performed.

Therefore, in the first restriction mode of the third embodiment, as described above, all macroblocks in each frame are subjected to orthogonal transform blocking in the field processing mode. In the cycle, only the odd field in the macroblock is encoded for one frame, and then in the even cycle, the even field in the macroblock is encoded for one frame. Therefore, according to the first restriction mode, since the odd field (the first field) is encoded first, the even field (the second field) can be predicted from the odd field (the first field). Becomes From this, it can be said that the first restriction mode is coding of a frame with intra-frame inter-field prediction.

Returning to FIG. 20, the main flow of image data to be coded by the coding apparatus according to the third embodiment will be described using the configuration of FIG.

That is, in FIG. 20, a digital image signal is supplied to the input terminal 1 and stored in the frame memory group 10. The frame memory group 10
Thereafter, the data of the unit macroblock of 16 × 16 pixels is read out under the control of the address generator 35 described later and transmitted to the difference detector 12. The difference detector 12 includes a frame memory group 2 with a motion compensator described later.
Motion compensated image data from 0 is also supplied, and the difference detector 12 detects these differences.

The output of the difference detector 12 is sent to a DCT circuit 13 that performs an orthogonal transform (DCT) process. The DCT coefficient data obtained by the DCT processing by the DCT circuit 13 is sent to the quantizer 14. The quantizer 14
Is output from the output terminal 2 as encoded data via a variable-length encoding circuit 15 and a buffer 16 for performing variable-length encoding processing such as so-called Huffman encoding or run-length encoding. .

Further, the quantized data from the quantizer 14 is stored in the frame memory group with motion compensator 20 by an inverse quantizer which performs an inverse quantization process of the quantization process by the quantizer 14. Data is supplied via an adder 19 via an inverter 17 and an inverse DCT circuit 18 for performing an inverse DCT process of the DCT process in the DCT circuit 13.
In the adder 19, the output of the inverse DCT circuit 18 and the output of the frame memory group with motion compensator 20 are added. Note that the buffer 1
The information for preventing the overflow of No. 6 is fed back to the quantizer 14.

On the other hand, the image data output from the frame memory group 10 in macroblock units is transmitted to the frame motion detecting circuit 22 and the field motion detecting circuit 21.

The frame motion detection circuit 22 detects a motion vector between frames and the sum of absolute value differences of each pixel in units of the macroblock, and outputs these data (the data FMMV of the motion vector between frames and the sum of absolute value differences). Data FMAD) is output. Further, the field motion detection circuit 21 detects a motion vector between fields and the sum of absolute value differences of each pixel in the macroblock unit, and outputs these data (data FDMV of the motion vector between fields and sum of absolute value differences). Data FDAD). The data FMMV of each motion vector of the motion detection circuits 21 and 22
/ FDMV is transmitted to the selector 24.

The data FMAD / FDAD and the motion vector data FMMV / FDAD of each absolute value difference from the field motion detecting circuit 21 and the frame motion detecting circuit 22 are obtained.
The FDMV is the frame / field mode determination circuit 3
Also sent to 3.

The frame / field mode determination circuit 33 performs the following motion based on the absolute value difference sum data FMAD from the frame motion detection circuit 22 and the absolute value difference sum data FDAD from the field motion detection circuit 21. At the time of the motion prediction process in the frame memory group with compensator 20, it is determined whether the motion prediction process is to be performed in the frame unit or the field prediction unit. ) Is output. Specifically, in the frame / field mode determination circuit 33,
For example, the difference between the absolute value difference sum data FMAD and the absolute value difference sum data FDAD is larger than a certain threshold value T1 (F
If it is determined that MAD-FDAD> T1, the circuit 33 outputs data (data MPFD of the field prediction mode in the motion prediction) indicating that it is more efficient to perform the motion prediction processing in the field unit. I do. vice versa,
Absolute value difference sum data FMAD and absolute value difference sum data FDAD
Is determined to be smaller than or equal to the threshold value T1 (when FMAD-FDAD≤T1), data indicating that it is more efficient to perform the motion prediction process on a frame-by-frame basis ( It outputs frame prediction mode data MPFM) in motion prediction.

Either of these prediction mode data MPFM /
The MPFD is sent to the frame memory group with motion compensator 20. In addition, these prediction mode data MPFM / MPFD
Is also sent to the selector 24.

The selector 24 receives the prediction mode data MP from the frame / field mode determination circuit 33.
In accordance with FM / MPFD, data F of motion vectors between frames supplied from the frame motion detection circuit 22
Either the MMV or the data FDMV of the inter-field motion vector supplied from the field motion detection circuit 21 is selectively output. That is, when the prediction mode data is the data MPFD indicating the field prediction mode, the motion vector data FDMV from the field motion detection circuit 21 is selected and output, and when the prediction mode data is the data MPFM indicating the frame prediction mode, The motion vector data FMMV from the frame motion detection circuit 22
Select and output. The motion vector data FMMV / FDMV selected by the selector 24 is sent to the frame memory group 20 with motion compensator. Thus, in the frame memory group 20, the prediction mode data MPFM / MPFD and the motion vector data FMMV
/ FDMV, it is possible to perform motion compensation in frame units or field units.

Further, the frame / field mode determination circuit 33 is also supplied with the image data in macroblock units read from the frame memory group 10. The frame / field mode determination circuit 33
Then, a difference image is created using the prediction mode data MPFM / MPFD and the motion vector data FMMV / FDMV and the image data from the frame memory group 10,
On the basis of the difference image, a mode (block processing mode / field processing mode) of block processing of orthogonal transform that is most suitable for an image output from the frame memory group 10 and subjected to DCT processing by the DCT circuit 13 is selected. Is performed at the same time. In the case of the I picture (or I frame), data of an image (original image) in the frame memory group 10 is used instead of the difference image.

In the frame / field mode determination circuit 33, specifically, the difference EFM obtained in the frame and the difference EFD obtained in the field using the above-described equations (1) and (2) of the equations (1) and (2) are used. Is greater than the threshold value T2 (when EFM-EFD> T2),
The DCT circuit 13 outputs data (data MDFD in the field processing mode in the orthogonal transform blocking process) indicating that the DCT in the DCT circuit 13 is performed on a field basis. Conversely, if it is determined that the difference between the difference EFM and the difference EFD is smaller than or equal to the threshold value T2 (when EFM-EFD≤T2), the DCT circuit 13
Data indicating that T is performed in the frame unit (data MDFM in the frame processing mode in the orthogonal transform blocking process) is output.

Here, the output of the frame processing mode data MDFM or the field processing mode data MDFD from the frame / field mode determining circuit 33 is performed in accordance with the first limiting mode or the second limiting mode from the limiting mode determining circuit. Encoding mode data EN1 corresponding to
/ EN2.

The limited mode determining circuit 34 uses the image data in macroblock units read from the frame memory group 10 to determine which of the first limited mode and the second limited mode as described above. Determines whether encoding is efficient, and outputs the encoding mode data EN1 or EN2 according to the determination result. Specifically, in the restriction mode determination circuit 34, for example,
The sum of the absolute value difference of each pixel between the odd field (first field) and the even field (second field) of each frame is calculated, and the sum of the absolute value difference is smaller than a certain threshold value T0 (that is, the threshold value T0). If the motion of the image is small), the output of the limited mode data EN1 indicating that it is more efficient to perform the encoding in the second limited mode is output. If the threshold value is equal to or larger than the threshold value T0 (when the motion of the image is large), the limited mode data EN2 indicating that the encoding in the first limited mode is more efficient is output.

It should be noted that when making the determination in the restriction mode determination circuit 34, it is possible to make a determination using the motion vector data FDMV from the field motion detection circuit 21. That is, the motion vector data FDMV between the odd field and the even field has a threshold value t.
If it is less than 0, the second restriction mode may be selected, and if it is not less than the threshold value t0, the first restriction mode may be selected.

The limited mode data EN1 / EN2 from the limited mode determination circuit 34 is sent to the frame / field processing mode determination circuit 33, so that the frame / field mode determination circuit 33 The frame processing mode data MDFM or the field processing mode data MDFD corresponding to the data EN1 / EN2 is output.

That is, if the limited mode data from the limited mode determination circuit 34 is the data EN1 indicating the second limited mode, the frame / field mode determination circuit 33 Then, processing for adaptively switching the frame processing mode or the field processing mode is performed. Therefore, from the frame / field processing mode determination circuit 33,
The adaptively switched frame processing mode M
DFM or field processing mode data MDFD is output.

On the other hand, when the encoding mode data from the encoding processing mode determination circuit 34 is the data EN2 indicating the first restriction mode, the frame / field processing mode determination circuit 33 As described above, the blocking of the orthogonal transform of all the macroblocks in one frame is performed in the field processing mode. Therefore, the frame / field processing mode determination circuit 33 outputs the field processing mode data MDFD
Will be output.

The mode data MDFM / MDFD for blocking the orthogonal transform of either the frame / field output from the frame / field processing mode determination circuit 33 and the limited mode data EN1 / EN2 from the limited mode determination circuit 34. Is transmitted to the address generator 35 and the frame memory group with motion compensator 20. The processing mode data (MDFM / MDFD), the prediction mode data (MPFM / MPFD), the encoding mode data EN1 / EN2, and the motion vector data (FM
MV / FDMV) is also sent to the above-described variable length encoding circuit 15.

The address generator 35 outputs a frame memory group so as to output image data of a macroblock divided into blocks in accordance with the processing mode data MDFM / MDFD and the restriction mode data EN1 / EN2 on a macroblock basis. 10 is controlled. That is, as described above, for example, when the restricted mode data EN1 / EN2 is the data EN1 indicating the second restricted mode, the address generator 35 performs the orthogonal conversion blocking mode (in the odd cycle). The frame memory group 10 is controlled so as to output a macroblock which is divided into blocks corresponding to the data MDFM / MDFD. In the case of the data EN2 indicating the first limited mode, the frame memory group 10 is controlled in the odd and even cycles. Field processing mode (data M
DFD) to control the frame memory group 10 so as to output macroblocks that are divided into blocks.

In other words, for example, when the second restriction mode is selected and the restriction mode data EN1 is supplied to the address generator 35, for example, the processing mode data indicates DCT processing in frame units. If the data is MDFM, the address generator 35 is a macroblock (a macroblock in a frame unit combining an odd field and an even field) in which even and odd are alternately scanned as shown in FIG. Is controlled to output the frame memory group 10. That is, in this case, the address generator 34
As shown in FIG. 3, a macro block consisting of 1 to 16 lines is divided into 1 to 8 lines and 9 to 16 lines.
The frame memory group 10 is divided into lines, and the frame memory group 10 is controlled so that four 8 × 8 blocks (macro blocks) are output.

When the second restriction mode is selected and the restriction mode data EN1 is supplied to the address generator 35, for example, the processing mode data becomes data MDFD indicating DCT processing in field units. If the address generator 35 is in the
As shown in (1), the frame memory group 10 is controlled so as to output the scanned macroblocks (macroblocks in the field units of the odd field and the even field) by separately dividing the even and odd scans. That is, as shown in FIG. 4, the address generator 34 outputs one line, three lines, five lines, seven lines, nine lines, eleven lines, thirteen lines, and fifteen lines (an odd field or each line of the first field). ),
The lines are divided into two lines, four lines, six lines, eight lines, ten lines, twelve lines, fourteen lines, and sixteen lines (even lines or each line of the second field). The frame memory group 10 is controlled so as to output two 8 × 8 blocks (macro blocks).

Further, for example, the first encoding processing mode is selected and the limited mode data E is supplied to the address generator 35.
When N2 is supplied, the address generator 35 outputs the frame memory group 10 so as to output the macroblock which has been divided into blocks corresponding to the field processing mode in the odd and even cycles as described above. Control. That is, when the first restriction mode is selected, the address generator 35 always outputs 8 bits.
The above frame memory group 10 is output so as to output two x8 blocks (only the luminance component as described later).
Control. Specifically, the address generator 35
Means that only the odd field in the odd cycle is 8 ×
Frame memory group 1 so that two macro blocks of 8 blocks are output for one frame (one screen).
0, and then controls the frame memory group 10 so that in the even-numbered cycle, only the even-numbered fields output the macroblocks corresponding to the two 8 × 8 blocks for one frame (one screen).

As described above, the image data output from the frame memory group 10 controlled by the address generator 35 is subjected to the DCT processing by the DCT circuit 13 as described above. That is, for example, when the second restriction mode is selected and the frame processing mode is selected, the DCT circuit 13 performs the DCT conversion on the unit block of 8 × 8 pixels as shown in FIG. 3 described above. Further, for example, when the second restriction mode is selected and the field processing mode is selected, the DCT circuit 13 performs the DCT conversion on the unit block of 8 × 8 pixels as shown in FIG. 4 described above. When the first restriction mode is selected, as described above, only the odd field is subjected to the DCT conversion in the 8 × 8 block in the odd cycle, and the even field is performed in the 8 × 8 block only in the even cycle. In the block of D
Perform CT conversion.

Further, the prediction mode data MPFM / MPFD and the processing mode data MDFM / MDFD from the frame / field mode determination circuit 33 and the selector 2
4, the motion vector data FMMV / FDMV selected in
Restriction mode data E from the restriction mode determination circuit 34
N1 / EN2 is also supplied to the frame memory group with motion compensator 20. Therefore, in the frame memory group with motion compensator 20, the prediction mode data MPFM / MPFD and DCT
In accordance with the processing mode data MDFM / MDFD and the encoding mode data EN1 / EN2 in the processing, motion compensation using the motion vector data FMMV / FDMV is performed.

As described above, the motion estimation of the P and B frames, for example, in the second restriction mode and the frame processing mode is performed as shown in FIG.
Motion is predicted from the previous and subsequent frames. Therefore, in the DCT circuit 13, the difference image from the predicted image is
That is, T transformation (DCT transformation in a unit block of 8 × 8 pixels) is performed. FIG. 29 shows the previous frame, the current frame, and the subsequent frame.
MB indicates a macroblock. Further, in the motion prediction of the P and B frames in the first encoding processing mode and the field processing mode, as shown in FIG. 30, before and after each of the odd and even fields of the macroblock. Motion estimation is performed from odd or even fields (first or second field) of the frame. Therefore, in the DCT circuit 13, the difference image from the predicted image is subjected to DCT (DCT conversion in a unit block of 8 × 8 pixels). FIG. 30 shows the odd field and the even field of the previous frame, the current frame, and the subsequent frame. Arrows in the figure indicate motion vectors, and MB indicates a macroblock.

Further, the motion prediction in the field processing mode in the first restriction mode is performed, for example, by referring to FIG.
As shown in FIG. 1, motion prediction is performed for each of the odd and even fields of the macroblock from the odd or even fields of the previous and subsequent frames, and
Motion prediction between each field in each frame is also performed.
Therefore, in the DCT circuit 13, the difference image from the predicted image is transformed by DCT (D
CT conversion). FIG. 31 shows the odd field and the even field of the previous frame, the current frame, and the subsequent frame. Arrows in the figure indicate motion vectors, and MB indicates a macroblock.

As described above, in the image signal high-efficiency encoding apparatus according to the third embodiment, the field signal in the frame depends on the first and second restriction modes (ie, the magnitude of the motion of the image). Since switching is performed between coding that does not perform inter-prediction and coding that performs inter-field prediction within a frame, the most efficient coding is possible. In particular, the first restriction mode is effective for a frame having a large motion.

By the way, in the coding apparatus of the third embodiment,
This code is realized by adding an extension bit to the conventional macro block type to obtain compatibility with the conventional macro block type.

That is, also in the case of the third embodiment,
For example, in a B frame, there are three types of macroblocks, ie, pre-prediction, post-prediction, and both predictions as described above. Therefore, the present code is realized by adding an extension bit for recognizing one of the predictions. Since there are two types of prediction in this case, it is sufficient to add one bit for the extension bit in one direction (previous and post-prediction). For example, the code "1" may be added to the conventional macroblock type as an extension bit in the case of prediction from an odd field in the case of prediction from an even field in the pre- or post-prediction. is there. Also, in both predictions, both extension bits are added for the front or rear prediction.

In the frame prediction mode, the conventional bit stream (MPE) is not added without adding an extension bit.
It has the same format as G).

The above is similarly applied to the case of a P frame.

Next, in the same manner as in the previous embodiment, the third embodiment
In the case of, for example, in the B frame, the macroblock type includes pre-prediction, post-prediction, and both predictions as described above. However, in the field prediction mode for pre-prediction, prediction from an odd field or prediction from an even field Prediction or
Extension bits must be added to the macroblock type to allow prediction or recognition from odd fields in its own frame. That is, in the field prediction mode of the previous prediction, since there is a prediction from within the own frame, one or two extended bits are required to represent three types of predictions including the odd and even numbers with the extended bits. In the field prediction mode of post-prediction, there are only two types, odd and even, so that one extension bit is always required.

[0211] In the mode of processing with frames, no extension bits are added, and the format is the same as that of a conventional bit stream (MPEG). Also, in both predictions, both extension bits are added for the front or rear prediction.

The above is similarly applied to the case of a P frame.

Further, as a modification, the number of extension bits in the case of the pre-prediction can be reduced to one bit. That is, in the even cycle in the field prediction mode, as in the case of FIG. 16 described above, the prediction indicated by the dashed line in the figure from the odd field of the previous frame that is farthest in time and position is abolished. Can be reduced to two, and the pre-prediction mode can be transmitted with 1-bit extension.

FIG. 32 shows a configuration example of the encoding apparatus according to the second embodiment. It should be noted that in FIG.
The same components as those of 0 are denoted by the same reference symbols, and detailed description thereof will be omitted.

The configuration of the second embodiment is a three-pass encoding apparatus, which performs processing three times to process one frame.

That is, in the second embodiment, in the first pass, processing of the above-described first limited mode (with intra-frame inter-field prediction) using the fixed quantization width is performed.
In the second pass, processing in the above-described second restriction mode (no intra-frame inter-field prediction) using a fixed quantization width is performed.
For the pass, a process in which the number of generated bits is small is selected from the first pass and the second pass, and the process is performed by controlling the quantization width.

Here, in the third embodiment, a macroblock converter 55, a changeover switch 57, a field block conversion circuit 56, and a changeover switch 58, which will be described later, are inserted and connected after the frame memory group 10. You. The image data from the frame memory group 10 is sent to a motion detection circuit 51 that performs frame and field motion detection. The output from the motion detection circuit 51 is sent to a processing mode determination circuit 52 for selecting a frame / field mode for orthogonal transform blocking and motion prediction, the frame memory group 20 and the variable length coding circuit 15.

The output mode data from the processing mode determination circuit 52 is sent to the frame memory group 20 and the variable length coding circuit 15, and the field processing mode data is sent to one input terminal of the two-input AND gate 53. Can be The other input terminal of the two-input AND gate 53 has a changeover switch 59 that is switched via the inverter 54 in accordance with the first, second, and third passes.
Output is supplied. The output terminal of the 2-input AND gate is connected to the changeover switch 57,
58 switching control terminals.

The variable length coding circuit 15 outputs data of the number of generated bits, and based on the data of the number of generated bits, any one of the first and second encoding modes has a smaller number of generated bits. Is sent to a selection circuit (intra-frame inter-field prediction presence / absence determination circuit) 60 for selecting one of the modes. Further, the accumulated amount data from the buffer 16 is transmitted to the changeover switch 6 together with the variable length encoding circuit 15.
1 is supplied to one of the switched terminals. A fixed value of the first and second passes is supplied to the other switched terminal of the changeover switch 61.

In the second embodiment, the image input to the terminal 1 is once stored in the frame memory group 10, and the necessary frame or field data is called out from the frame memory group 10. A motion vector is obtained by the motion detector 51 using these image data. The processing mode determination circuit 52 determines the mode of the field / frame for each macroblock from the motion prediction residual from the motion detector 51. The macroblock converter 55 connected to the subsequent stage of the frame memory group 10 outputs information corresponding to the first, second, and third passes through the changeover switch 59 (that is, the second restriction mode or the second restriction mode). When information of the first restriction mode is received as the information, only blocks of odd fields (first field) are transmitted. After that, the even field (the second field) is transmitted, and the frame processing mode is blocked
Change to F. Further, the image data in which the macroblock is determined to be a block in the frame processing mode based on the information of the second restriction mode in the macroblock generator 55 is output from the residual from the motion detector 51 to the mode determination circuit 52. If the mode is determined to be the field mode, the field block conversion circuit 56 converts the block into a frame processing mode block.

In the first pass and the second pass, encoding is performed with a fixed quantization width, and the bit generation amount is compared by the selection circuit 60. Is selected for each frame, and actual encoding is performed in the third pass. At this time, the information of the selected mode is added by one bit for each frame.

FIG. 33 is a block diagram of a decoder for a corresponding image signal. The third high-efficiency decoding device receives and decodes the reproduced image encoded data and the header information including the detected motion vector information, the processing mode information, and the limited mode information, and decodes the decoded image. Inverse variable-length encoding means for outputting the detected motion vector information, the processing mode information, and the restriction mode information together with the encoded data, and an address / increment value in a frame buffer for storing the decoded image data from the restriction mode information. Calculating, calculating the head address of each macro block, address generation means for giving the head address to the frame buffer, and adding data relative to the macro block other than the head address to the frame buffer to access data, Receiving the detected motion vector information, the processing mode information, and the restricted mode information; Taken, performs motion compensation corresponding to the mode information, in which an image signal motion compensated and a motion compensation unit configured to send to the frame buffer.

That is, the high-efficiency decoding apparatus according to the present embodiment is capable of reproducing encoded image data, detected motion vector information, prediction mode information, blocking mode information (processing mode information), and restricted mode information (restricted mode data). ) Is received and decoded, and the inverse variable length for outputting the detected motion vector information, the prediction mode information, the processing mode information, and the limited mode data of the header information together with the decoded image decoded data. An address increment value in the encoding circuit 51 and in the frame buffers 61, 62, and 64 for storing the image decoding data is calculated from the restriction mode data, a head address of each macro block is obtained, and the head address is calculated. Address generators 81, 82, provided to the frame buffers 61, 62, 64,
83 and the relative addresses of the macroblocks other than the start address are stored in the frame buffers 61, 62, 64.
In addition to the above, receiving the detected motion vector, the prediction mode information, the processing mode information, and the limited mode data, executing a motion compensation frame or inter-field prediction corresponding to the mode information, The obtained image signals are transmitted to the frame buffers 61 and 6.
Motion compensation circuits 59, 6 configured to send the
0, 63, 65, and 66.

In FIG. 33, data encoded by the high-efficiency encoding apparatus of the third embodiment is
And so on. The encoded data reproduced from the CD or the like is input via an input terminal 50,
First, the inverse variable length encoding circuit 51 decodes header information and the like for each sequence, each frame group, and each frame. In the odd cycle of the frame, header information is decoded for each slice (group of macroblocks), and the quantization width is included in the header of this slice. Then, for each macroblock, the macroblock address, frame / field prediction mode and frame / field processing mode information, coding processing mode data, and macroblock type indicating the decoding method are decoded, and the quantization width is updated. Sometimes decrypted.

When the block processing of the macro block is in the frame processing mode, the entire macro block is decoded in the odd cycle, and nothing is decoded in the even cycle. When the blocking is in the field processing mode, only the block including the odd field in the macro block is decoded in the odd cycle, and the block including the even field is decoded in the even cycle.

The image information is decoded via an inverse quantizer 53 for performing an inverse quantization process and an inverse DCT circuit 54 for performing an inverse DCT transform process, and it is determined whether or not the image is a difference image according to a macroblock type. According to the determination result, the adder 56 switches the mode switch 57 for switching between addition and non-addition to the reference image (corresponding to non-intra / intra in MPEG encoding). The decoded image is input to the frame buffer 64 or 61 in the case of an I frame or a P frame (alternately every time the I frame and the P frame are processed), and
In the case of a frame, it is input to the frame buffer 62.
Each frame buffer is composed of two field buffers, and odd / even field images are stored separately in the respective field buffers. The writing to the frame buffer is controlled by the switch 58.

At this time, the frame buffers 61, 62,
The addresses written to 64 are address generators 81, 8
2,83. This address generator 81,
At 82 and 83, the frame buffers 61, 62,
The address increment value at 64 is calculated, and the start address of each macro block is obtained.

Further, the quantization width data is stored in the memory 52 for one field. This quantization width data is sent to the inverse quantizer 53 via a switch 55 that is switched according to the output of the inverse variable length encoding circuit 51. Here, in the even cycle, only the macroblock processed in the field processing mode is decoded.
A macroblock type with a macroblock address to be decoded for each macroblock and a motion vector required for the prediction method indicated by this are decoded, and a difference image further transmitted from the reference field to a motion-compensated image is added, Obtain a playback image.

Each of the frame buffers 64, 6
The data of the motion compensation processing circuits 65, 66,
The motion is compensated by 59, 60 and 63. At this time, each motion compensation circuit switches between frame motion compensation and field motion compensation depending on the processing mode (frame / field) in DCT processing.

These motion-compensated images are sent to the selected terminals of the selection switches 67, 68, 71. These changeover selection switches 67, 68, and 71 are switched so that a reference field or a frame indicated by a macroblock type decoding method can be extracted. Here, the switch selection switch 71 is supplied with a signal which is obtained by adding the outputs of the switch selection switches 67 and 68 by the adder 69 and then halving the result by the divider 70, and the output of the switch 67. Is done. The output of the switch 71 is sent to the switch 57.

Further, each frame buffer 64, 61, 6
The output of 2 is sent to the display 73 via the changeover selection switch 72. The output of the switch 72, which is switched so as to be displayed in the order of reproduced images, not in the order of decoding, is supplied to the display 73. As a result, an image is obtained.

In the present embodiment, since only the macroblock processed in the field processing mode is decoded in the even cycle, it is necessary to know the macroblock address. There are two methods of knowing the macroblock address. One is the method of transmitting the macroblock address for each even-cycle macroblock described above, and the other is one-field processing in the odd cycle. In this method, mode / frame processing mode information is stored, and the address of a macroblock in the field processing mode is converted from a row of each processing mode. The former advantage is that no additional memory is required, and the latter advantage is that transmission information does not increase.
Similarly, the quantization width can be realized by transmitting each macroblock without using the method of storing one field in the odd cycle described above.

Next, advantages of the fifth encoding apparatus shown in FIG. 34 will be described with reference to the drawings. In FIG. 34, the blocks denoted by the same reference numerals as those in FIGS. 1 and 5 have the same function. Accordingly, here, blocks with different numbers from those in FIGS. 1 and 5 will be described.

That is, the high efficiency coding apparatus shown in FIG.
A first restriction mode in which the encoding process is prohibited in all the macroblocks in one frame by the above-described frame processing mode, except for the blocks with the same numbers as those of the high-efficiency encoding devices in FIGS. 1 and 5; In any of the second restriction modes in which the prediction of the even field of the same frame from the odd field of the frame currently being encoded in all the macroblocks in one frame is prohibited, any one of the efficient restriction modes is selected. For a bidirectional predicted frame (image), so-called B-picture, only the above-described first restricted mode is selected, and a restricted mode is selected so as to prohibit prediction of even-numbered fields from odd-numbered fields of this B-picture. Means, the encoding mode determination circuit 34 (c) and the selector 24, and the first limited mode for one frame. Is selected, the odd field components of all macroblocks are output, then the even field components of all macroblocks are output, and if the second restriction mode is selected, all the An address generator 35 which is an address generator for controlling a frame memory group so as to sequentially output one macro slice of a macro block in units of a frame composed of both odd field and even field components of the macro block.
(C).

Here, in the encoding apparatus according to the fifth embodiment, as shown in FIG.
0o, B0e, I1o, I1e, B2o, B2e, P3
o, P3e, B4o, B4o, P5o, P5e, ...
・ ・

The code order (decoding order) of this embodiment is I
1o, I1e, B0o, B0e, P3o, P3e, B2
o, B2o, P5o, P5e, B4o, B4e, ...
・ ・ The order is as follows.

By the way, when the code by the second encoding device is decoded by the decoding device, it can be reproduced by having a maximum of three frame buffers, ie, six fields.

The operation of the decoding apparatus having three frame buffers A, B, and C will be described with reference to FIG. When decoding an I frame or a P frame, the decoded image is stored in the frame buffer A,
B is alternately stored and stored, and the display displays the contents of the frame buffer opposite to the frame buffer used for storing the current frame in the order of the odd field and the even field. In other words, when storing an image in the frame buffer A, the contents of the frame buffer B are displayed,
When storing an image in the frame buffer B, the contents of the frame buffer A are displayed. These are later decoded B
Alternatively, two frames must be stored in the frame buffer to serve as a reference frame for P-frame motion compensation.

When the B frame is decoded, the decoded image is stored in the frame buffer C, and the contents of the frame buffer C are displayed in the order of odd fields and even fields. When decoding is performed in accordance with such a rule, at time 1o, the decoded image of all the components of I1o and the even field components of the macroblocks in the frame prediction mode of frame blocking I1e is stored in the frame buffer A. At 1e, motion compensation is performed by referring to the contents of the frame buffer A, and the decoded image of the even field component of the macroblock in the field-blocking field prediction mode of I1e is stored in the frame buffer A.

At time 1o, the odd components of the frame buffer B are displayed, and at time 1e, the even components of the frame buffer B are displayed. If there is no preceding code, the contents of the frame buffer B at this point are undefined.

At time 2o, the images of the frame buffers A and B are motion-compensated, and the decoded image of all the components of B0o and the even field components of the macroblocks in the frame prediction mode of B0e are stored. Then, motion compensation is performed with reference to the contents of the frame buffers A, B, and C, and the decoded image of the even field component of the macroblock in the field prediction mode B0e in the field blocking mode is stored in the frame buffer A.

Next, at time 2e, the images of the frame buffers A, B, and C are motion-compensated, and the decoded image of the even field component of the macroblock in the field-blocked field prediction mode of B0e is stored in the frame buffer C.
Is stored in

At time 2o, the odd components of the frame buffer C are displayed, and at time 2e, the even components of the frame buffer C are displayed.

At this time, when displaying B0o, the odd cycle of the B frame is decoded, and B0o, B0
The component of e is also included. Therefore, the decoded B0e image component at this time must be stored for later display in time.

When displaying the above B0e, the B frame is
The even cycle decoding is performed, and the remaining components of B0e that are not decoded in the odd cycle are decoded. Therefore, at this time, since it is necessary to perform motion compensation on the images B0o to B0e, the images B0o must also be stored.

Accordingly, a frame buffer for one frame is required for the B frame, and a buffer for a total of three frames is required to decode the code by the second encoding device.

On the other hand, in the fifth encoding device, FIG.
As shown in (1), only the block configuration of the field configuration of the field prediction of the B frame is performed, and further, it is prohibited to predict the even field from the odd field of the B frame. From this, as shown in FIG. 35, only B0o is decoded at time 2o, B0o is displayed at the same time, and since this image is not used for the subsequent motion compensation, there is no need to save it.

At time 2e, only B0e is decoded and B0e is displayed at the same time, so that B0e does not need to be stored. Therefore, the decoding device for decoding the code by the fifth encoding device does not need the above-mentioned frame buffer C, and can be decoded by the decoding device as shown in FIG. Thus, the circuit scale and manufacturing cost of the decoding device can be reduced.

At time 3o, the image of frame buffer A is motion compensated and all components of P3o and P
The decoded image of the even field component of the macroblock in the frame-blocked frame prediction mode of 3e is stored, and motion compensation is performed by referring to the contents of the frame buffers A and B at time 3e, and the field-blocked field prediction mode of P3e is stored. Are decoded in the frame buffer B.

Next, at time 3e, the images of the frame buffers A and B are motion-compensated, and the decoded image of the even field component of the macroblock in the field-blocking field prediction mode of P3e is stored in the frame buffer B.

At time 3o, the odd components of the frame buffer A are displayed, and at time 3e, the even components of the frame buffer A are displayed.

Thereafter, decoding and display are performed in the same manner.

As shown in FIG. 39, the structure of the above GOP is B0o, B0e, B1o, B1e, I2o, I2
e, B3o, B3e, B4o, B4o, P5o, P5
When the decoding is performed in accordance with the above-described procedure even when decoding is performed such that two B frames are used between IP frames or between PP frames as in e,..., the same decoding device as shown in FIG. Can be decrypted.

B between frames or between P and P frames
The same applies to two or more frames.

Next, advantages of the sixth encoding device will be described with reference to the drawings. The configuration of the sixth encoding device is as shown in FIG. 40. In FIG. 40, blocks denoted by the same reference numerals as in FIGS. 1 and 5 have the same function. Accordingly, here, blocks with different numbers from those in FIGS. 1 and 5 will be described.

That is, the high efficiency coding apparatus shown in FIG.
A first restricted mode in which the encoding process in the above-described frame processing mode is prohibited in all the macroblocks in one frame other than the blocks having the same numbers as those of the high-efficiency encoding devices in FIGS. 1 and 5; In all the macroblocks in one frame, any one of the efficient restriction modes is selected from among the second restriction modes in which the process of predicting the even field of the current frame from the odd field of the frame currently being encoded is prohibited. For bidirectional prediction frames (images), so-called B-pictures, only the above-described first restriction mode is selected, and it is prohibited to predict even-numbered fields from odd-numbered fields of the B-pictures. A system that prohibits prediction from odd fields of frames that are reference frames for forward prediction for pictures The encoding processing mode decision circuit 34 (d) and selector 24 is a mode selection means, when the 1 frame is the first limitation mode is selected,
Output the odd field components of all macroblocks,
Then, output even field components of all macroblocks, and if the second restriction mode is selected,
An address generator 35 (d) which is an address generating means for controlling a frame memory group so as to sequentially output one slice of macroblocks in units of a frame composed of both odd field and even field components of all macroblocks; It is provided with.

Here, in the present embodiment, the order of the images during the display time is B0o, B0e, B0 as shown in FIG.
1o, B1e, I2o, I2e, B3o, B3e, B4
o, B4e, P5o, P5e,...

The encoding order of the encoding apparatus of this embodiment is I2
o, I2e, B0o, B0e, B1o, B1e, P5
o, P5e, B3o, B3e, B4o, B4e, ...
.. Are encoded in this order.

Also, the sixth encoding device shown in FIG.
In the fifth coding apparatus, forward prediction from odd fields of a B frame is prohibited as shown in FIG.

Therefore, an image necessary for prediction has a buffer for one frame, that is, two fields for backward prediction, a buffer for one field for forward prediction, and a buffer for three fields in total, as shown in FIG. 43. Can be decrypted by the device.

This will be described with reference to FIG.

When decoding an I-frame or a P-frame, the decoded image is transferred to the field buffers A, B, C, A, B, C,
.. Are stored in the order of... When the field buffer at the start of storage is C, the field buffer A
The contents of field buffer B are displayed when the field buffer at the start of storage is A, the contents of field buffer C are displayed when the field buffer at the start of storage is B, and the B frame is decoded. Does not save the encoded image, but immediately displays it.

When decoding is performed based on such a procedure, the following operation is performed. In 1o, field buffer A
Starts the storage, so that the contents of the field buffer B are displayed.

In 1e, the contents of the field buffer C are displayed since the field buffer B starts storing. If there is no previously decoded image,
The display contents at this time are undefined.

At time 1o, all of I2o and the even component of the macroblock in the frame configuration block prediction mode of I2e are decoded and stored in the field buffers A and B, respectively.

By performing motion compensation on the image of the field buffer A at the time 1e, the even component of the macroblock in the field prediction mode of the field block mode of I2e is decoded and stored in the field buffer B.

At time 2o, since the image to be encoded is a B frame, the images in the field buffers A, B, and C are motion-compensated and B0o-decoded, the decoded image is immediately displayed, and the image is not stored. . The same applies to B0e, B1o, and B1e at times 2e, 3o, and 3e.

In 4o, since the field buffer C starts storing, the contents of the field buffer A are displayed. In step 4e, the storage of the field buffer A is started, so that the contents of the field buffer B are displayed.

At time 4o, field buffers A and B
Is motion-compensated to decode all of P3o and the even-numbered component of the macroblock in the frame configuration block prediction mode of P3e.
A.

At time 4e, field buffers B, C, and A
, The even component of the macroblock in the field-blocking field prediction mode of P3e is decoded and stored in the field buffer A.

As described above, in the sixth encoding device, decoding can be performed with three field buffers, that is, one and a half frame buffers, and the number of buffers in the decoding device is reduced as shown in FIG. Circuit scale and manufacturing cost can be reduced.

By the way, the bit stream output from the transmission buffer 16 described in FIG. 1 and the like is multiplexed with an encoded audio signal, a synchronization signal, and the like, further added with an error correction code, and Is recorded on a recording medium such as an optical disk, tape, or semiconductor memory via a laser beam.

[0273] Also, a bit stream is input to the decoder via a transmission medium. Reproduced data reproduced via a laser beam from a transmission medium from an optical disk or the like is subjected to predetermined demodulation, error correction is performed, and further, audio signals and synchronization signals are multiplexed. , These separations are performed.

Here, the bit stream output from the encoder is recorded on an optical disk, but may be transmitted to a transmission path such as ISDN or satellite communication.

[0275]

As described above, according to the first high-efficiency encoding apparatus for image signals according to the present invention, with respect to a moving image having a field structure, both an image with little motion and an image with much motion, and both of them, Field processing or frame processing can be performed efficiently even in the case of an image in which... Are mixed. For example, in the current frame being coded, an even field image can be predicted from an odd field image, thereby improving the efficiency. You can select the encoding. Therefore, a high-quality moving image can be reproduced with less transmission information at the time of decoding by the high-efficiency decoding device of the present invention later.

[0276]

According to the second high efficiency coding apparatus,
Since all the B frames are processed on a field-by-field basis, and the mode for prohibiting the prediction of the even field of the same frame from the odd field of the same frame is switched on a frame or slice basis, The frame buffer can be reduced to two, that is, four fields.

According to the third high efficiency coding apparatus,
The number of frame buffers can be reduced to one and a half, that is, three fields.

[0279]

[0280]

[Brief description of the drawings]

FIG. 1 is a block diagram illustrating a schematic configuration of a high-efficiency image signal encoding apparatus according to a first embodiment.

FIG. 2 is a diagram showing a macroblock.

FIG. 3 is a diagram showing a macroblock in a frame processing mode.

FIG. 4 is a diagram showing a macroblock in a field processing mode.

FIG. 5 is a block diagram illustrating a schematic configuration of a high-efficiency image signal encoding apparatus according to a second embodiment.

FIG. 6 is a diagram illustrating a state of an encoding process of the encoding devices according to the first and second embodiments.

FIG. 7 shows a specific example of a digital VTR. DC in a frame processing mode / field processing mode in a format.
It is a figure showing a unit block of T processing.

FIG. 8 is a diagram showing a state of motion prediction in FIG. 7;

FIG. 9 is a diagram showing another example of FIG. 7;

FIG. 10 is a diagram illustrating a state of motion prediction in the example of FIG. 9;

FIG. 11 is a diagram showing a unit block of DCT processing in a frame processing mode / field processing mode in another specific example format of a digital VTR.

FIG. 12 is a diagram showing another example of FIG. 11;

FIG. 13 is a diagram showing a set of macro blocks.

FIG. 14 is a diagram for explaining a state of processing in a frame processing mode in the example of FIG. 13;

FIG. 15 is a diagram for explaining a state of processing in a field processing mode in the example of FIG. 13;

FIG. 16 is a diagram for describing a modified example (for pre-prediction) of extension bit addition in the encoding device according to the second embodiment.

FIG. 17 is a block diagram illustrating a configuration of a decoder corresponding to the encoding devices of the first and second embodiments.

FIG. 18 is a diagram showing an odd cycle image.

FIG. 19 is a diagram showing an image of an even cycle.

FIG. 20 is a block diagram illustrating a schematic configuration of a high-efficiency image signal encoding apparatus according to a third embodiment.

FIG. 21 is a block diagram illustrating a schematic configuration of a high-efficiency image signal encoding apparatus according to a fourth embodiment.

FIG. 22 is a block diagram illustrating a schematic configuration of a modified example of the high efficiency image signal encoding apparatus according to the third embodiment.

FIG. 23 is a flowchart for explaining a modified example 1 of the processing of the restricted mode selecting means in the high efficiency image signal encoding apparatus according to the third embodiment.

FIG. 24 is a diagram showing a motion vector from an odd field to an even field.

FIG. 25 is a flowchart for explaining a modified example 2 of the processing of the restricted mode selecting means in the high efficiency image signal encoding apparatus according to the third embodiment.

FIG. 26 is a flowchart for explaining a modified example 3 of the processing of the restricted mode selecting means in the high efficiency image signal encoding apparatus according to the third embodiment.

FIG. 27 is a flowchart for explaining a modified example 4 of the processing of the restricted mode selecting means in the high efficiency image signal encoding apparatus according to the third embodiment.

FIG. 28 is a flowchart for explaining a modification 5 of the processing of the restricted mode selecting means in the high efficiency image signal encoding apparatus according to the third embodiment.

FIG. 29 is a diagram illustrating motion prediction in the case of the frame processing mode in the second restriction mode.

FIG. 30 is a diagram illustrating motion prediction in the case of the field processing mode in the second restriction mode.

FIG. 31 is a diagram illustrating motion prediction in the case of the first restriction mode.

FIG. 32 is a block diagram illustrating a schematic configuration of an encoding device (modification) of the second embodiment.

FIG. 33 is a block diagram illustrating a configuration of a third decoding device.

FIG. 34 is a block diagram illustrating a schematic configuration of a high-efficiency image signal encoding apparatus according to a fifth embodiment.

FIG. 35 is a diagram illustrating a code decoding and display procedure by the fifth encoding device.

FIG. 36 is a diagram showing a code decoding and display procedure by the second (or third) encoding device.

FIG. 37 is a diagram illustrating a state of motion prediction in the fifth encoding device.

FIG. 38 is a block diagram illustrating a configuration of a fifth decoding device.

FIG. 39 is a diagram showing a code decoding and display procedure by the fifth encoding device.

FIG. 40 is a block diagram illustrating a schematic configuration of an image signal high-efficiency encoding apparatus according to a sixth embodiment.

FIG. 41 is a diagram illustrating a code decoding and display procedure by the sixth encoding device.

FIG. 42 is a diagram illustrating a state of motion prediction in the sixth encoding device.

FIG. 43 is a block diagram illustrating a configuration of a sixth decoding device.

FIG. 44 is a diagram for explaining each prediction image.

FIG. 45 is a diagram showing a data structure.

FIG. 46 is a diagram showing an image of a moving object.

[Explanation of symbols]

10 Frame memory group 11, 31, 35 (a), 35 (b), 35 (c), 3
5 (d), 35 (e)... Address generator 12... Difference detector 13... DCT circuit 14. ..... quantizer 15... Variable-length coding circuit 16... Buffer 17... Inverse quantizer 18 ...... Inverse DCT circuit 20 ... Frame memory group with motion compensator 21 ... Field motion detection circuit 22 ... ... Frame motion detection circuit 23 ... Prediction mode determination circuit 24 ... Selector 25 ... Blocking mode determination circuit 33 ... ..... Processing mode determination circuit 34 (a), 34 (b), 34 (c), 34 (d), 3
4 (e).... Limited mode determination circuit

────────────────────────────────────────────────── ─── Continued on the front page (72) Inventor Yasushi Fujinami 6-7-35 Kita-Shinagawa, Shinagawa-ku, Tokyo Inside Sony Corporation (72) Inventor Tomoyuki Sato 6-35, Kita-Shinagawa, Shinagawa-ku, Tokyo Within Sony Corporation (72) Inventor Motoki Kato 6-7-35 Kita-Shinagawa, Shinagawa-ku, Tokyo Sony Inside (72) Inventor Teruhiko Suzuki 6-35, Kita-Shinagawa, Shinagawa-ku, Tokyo S Knee Co., Ltd. (56) References 1992 IEICE Spring National Convention, D-343 “Extension of MPEG Video Coding Algorithm to Inter-Field Prediction” (1992.3) The 1991 Television Society of Japan Tournament 16 -1 "Video coding method for storage media using adaptive motion compensation prediction between frames / fields" (1991.7) Optronics N o. 5 (1992.5) p. 86-98 (Encoding in storage media) (58) Fields investigated (Int. Cl. ⁷ , DB name) H04N ^7/ 24-7/68 H04N 5/91-5/956

Claims (7)

(57) [Claims] 1. A high-efficiency encoding apparatus for an image signal that performs encoding by motion compensation-based prediction and orthogonal transform in units of a macroblock consisting of a two-dimensional array of a plurality of pixels. Means for selecting either motion compensation prediction of frame prediction or field prediction, means for selecting orthogonal transformation of either frame processing or field processing, and 1) field prediction for all macroblocks in one frame. And a first restriction mode in which orthogonal transformation is performed by field processing; and 2) motion compensation prediction of either frame prediction or field prediction is selected for each macroblock in one frame, and field processing is performed. Or a second restriction mode for adaptively selecting any orthogonal transform of frame processing; and any one of the following restriction modes: For each frame, and means for determining which of the first or second restriction mode is more efficient when encoding, and selecting an efficient restriction mode. The means for selecting a mode further includes, for a bidirectional prediction frame, a first field, a
For each of the two fields,
The motion compensation prediction is performed from the first or second field , and when the second restriction mode is selected, the motion compensation prediction from the first field to the second field of the frame is not performed. Encoding device. 2. A method according to claim 1, wherein said limiting mode selecting means obtains a parameter representing the magnitude of the motion of the entire screen from the median value of the horizontal and vertical components of the detected motion vector, and based on said parameter, 2. The apparatus according to claim 1, wherein the restriction mode is selected. 3. The restricted mode selecting means finds a correlation between a first field and a second field, and selects the first and second restricted modes based on the correlation. Item 2. A high-efficiency encoding apparatus for an image signal according to Item 1. 4. The limited mode selecting means, for a macroblock in a current frame to be coded, based on a difference between the image and a previously decoded image referred to by a motion vector. 2. The apparatus according to claim 1, wherein the restriction mode is selected. 5. The restricted mode selecting means finds a correlation between the first field and the second field, and adds a value corresponding to the found correlation over all macroblocks present in the current frame to be encoded. 2. The high-efficiency image signal encoding apparatus according to claim 1, wherein the first and second restriction modes are selected based on the added value. 6. The restricted mode selecting means detects vector anisotropy from motion vectors of all detected macroblocks, and sets a value corresponding to the anisotropy and a first field of a current frame to be encoded. 2. The image signal according to claim 1, wherein the first and second restriction modes are selected based on an addition value of a value corresponding to the correlation of the second field over all macroblocks. 3. Efficiency coding device. 7. A high-efficiency encoding method of an image signal in which a macroblock composed of a two-dimensional array of a plurality of pixels is encoded by motion-compensated prediction and orthogonal transform in units of: For a macroblock, a first restriction mode in which motion compensation prediction is performed by field prediction and orthogonal transform is performed by field processing; 2) For each macroblock in one frame, either a frame prediction or a field prediction motion A second restriction mode for selecting a compensation prediction and adaptively selecting an orthogonal transform of either field processing or frame processing; and selecting any one of the following restriction modes for each frame; Judging which of the second restriction modes is more efficient in encoding, and selecting an efficient restriction mode. Selecting a restricted mode, for further bidirectional prediction frames, the first field of macroblock, the
For each of the two fields,
The motion compensation prediction is performed from the first or second field , and when the second restriction mode is selected, the motion compensation prediction from the first field to the second field of the frame is not performed. Encoding method.