JPH0638171A - Band compression signal processing unit - Google Patents

Abstract

PURPOSE:To easily obtain an excellent reproduced picture at high speed repro duction by arranging signals subject to refresh coding processing around a specific location traced by a head and whose envelope is maximized at the high speed reproduction by a recording and reproducing means. CONSTITUTION:A unit number and a track number being additional information arranged after a unit synchronizing signal in VCR transmission data are read from a terminal 101. Refresh slicing is recorded around a prescribed position on a track through the designation of refresh slicing allocation position. The prescribed position depends on the track number and the unit number, and an RF signal reproduced from a head is inputted to an envelope detection circuit 103 via a terminal 102 at high speed reproduction. The circuit 103 recognizes the envelope shape at high speed reproduction and a track reproduction control circuit 74 controls a rotating phase and a tape feeding so as to maximize the envelope at the position corresponding to the track number and the unit number at which the center position of refresh slicing is in existence.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an apparatus for converting a video signal or the like into a digital signal and performing band compression by combining intraframe coding processing and interframe coding processing.
The present invention relates to a device which can easily obtain a good reproduced image when the output signal is recorded on, for example, a tape by a helical scan method and transmitted to a recording / reproducing device for reproducing the recorded signal. Further, the present invention relates to a device which can record a wide band signal such as a high definition TV for a long time.

[0002]

2. Description of the Related Art As is well known, when digitally transmitting a video signal, band compression is performed by combining a transmission method using a variable length coding method and a combination of intraframe coding processing and interframe coding processing. Transmission methods are being studied. Among them, a technique for performing band compression by combining intraframe coding processing and interframe coding processing and transmitting the data is described in, for example, the document IEEE Trans.on Broadcasting.
Vol.36 No.4 DEC 1990 Woo Paik: “Digit
This is a band compression technique as shown in "al compatible HD-TV Broadcast system", and its characteristic part will be described below. In FIG. 57, the video signal input to the input terminal 11 is the subtraction circuit 12. And the motion evaluation circuit 13. The subtraction circuit 12 performs a subtraction process, which will be described later, and the output thereof is input to a DCT (discrete cosine transform) circuit 14. The DCT circuit 14 operates in the horizontal direction. 8 pixels, 8 images in the vertical direction are used as a unit block (8 × 8
Pixel = 64 images) is taken in, and the pixel array is converted from the time domain to the frequency domain and the coefficient is output. And
Each coefficient is quantized by the quantization circuit 15. in this case,
The quantization circuit 15 has 32 types of quantization tables, and each coefficient is quantized based on the selected quantization table. The quantizing circuit 15 is provided with a quantizing table so that the amount of information generated and the amount of information sent are within a certain range.

The coefficient data output from the quantizing circuit 15 is zigzag-scanned from the low band to the high band for each unit block, and is extracted.
It is inputted to 6 and variable-length coded by combining the number of zero coefficients (run length) and the non-zero coefficient as one set. The encoder is a variable-length encoder having a different code length depending on the frequency of occurrence of Huffman code or the like. Then, the variable-length coded data is input to a FIFO (first-in-first-out) circuit 17 and read out at a prescribed speed, and then, via an output terminal 18, a multiplexer in the next stage (not shown). [Control signal, voice data, sync data (SYN
C), NMP and the like described later are multiplexed] and sent to the transmission path. Since the output of the variable length coding circuit 16 has a variable rate and the rate of the transmission path is a fixed rate, the FIFO circuit 17 serves as a buffer that absorbs the difference between the generated code amount and the transmitted code amount. .

The output of the quantizing circuit 15 is input to the inverse quantizing circuit 19 and inversely quantized. Further, the output of the inverse quantization circuit 19 is input to the inverse DCT circuit 20 and returned to the original signal. This signal is input to the frame delay circuit 22 via the adder circuit 21. The output of the frame delay circuit 22 is supplied to the motion compensation circuit 23 and the motion evaluation circuit 13, respectively. Motion evaluation circuit 13
Is the input signal from the input terminal 11 and the frame delay circuit 2
The output signal of 2 is compared to detect the overall motion of the image, and the phase position of the signal output from the motion compensation circuit 23 is controlled. In the case of a still image, the original image and the image one frame before are compensated so as to match each other. The output of the motion compensation circuit 23 can be supplied to the subtraction circuit 12 via the switch 24, and can also be fed back from the addition circuit 21 to the frame delay circuit 22 via the switch 25.

Next, the basic operation of the above system will be described. The basic operation of this system includes intraframe coding processing and interframe coding processing. The intraframe coding process is performed as follows. When this process is performed, both switches 24 and 25 are off. The video signal of the input terminal 11 is converted from the time domain to the frequency domain by the DCT circuit 14 and quantized by the quantization circuit 15. This quantized signal is subjected to variable length coding processing and then output to the transmission line via the FIFO circuit 17. The quantized signal is the inverse quantization circuit 19
The signal is returned to the original signal by the inverse DCT circuit 20, and delayed by the frame delay circuit 22. Therefore, in the intra-frame coding process, it is equivalent to that the information of the input video signal is variable length coded as it is. This intra-frame processing is performed in a proper cycle in units of predetermined blocks and scene changes of the input video signal. The periodic in-frame processing will be described later.

Next, the interframe coding process will be described. When the interframe coding process is executed, both switches 24 and 25 are turned on. Therefore, the subtraction circuit 12 obtains a signal corresponding to the difference between the input video signal and the video signal one frame before. This difference signal is
It is input to the DCT circuit 14, converted from the time domain to the frequency domain, and then quantized by the quantization circuit 15. Further, since the differential signal and the video signal are added by the adding circuit 21 and input to the frame delay circuit 22,
A predicted video signal that predicts the input video signal from which the differential signal was created is created and input.

FIG. 58 shows a line signal in a state in which a video signal of a high-definition television signal is subjected to the intraframe processing and the interframe processing as described above and sent out on the transmission path. This signal is a signal of a transmission line, and is shown in a state in which a control signal, a voice signal, a synchronization signal (SYNC), a system control signal, NMP and the like are multiplexed. FIG. 58A shows signals on the first line, and FIG. 58B shows signals on the second and subsequent lines. If this video signal has undergone intraframe processing, a normal video signal can be obtained by inverse conversion. However, in the case of a video signal that has been subjected to interframe coding processing, the difference signal is only reproduced even if this signal is inversely converted. Therefore, a normal video signal can be reproduced by adding the video signal (or the predicted video signal) reproduced one frame before to the difference signal.

According to the above system, all the information in the signal processed in the frame is variable-length coded, and the signal processed in the inter-frame after the next frame transmits the difference information. It means that the compression is realized.

Next, the definition of a set of pixels processed by the above band compression system will be described. That is, a block: an area of 64 pixels composed of 8 pixels in the horizontal direction and 8 pixels in the vertical direction. Super block: An area consisting of 4 blocks in the horizontal direction and 2 blocks in the vertical direction of the luminance signal. This area includes one block as the color signals U and V.
The image motion vector obtained from the motion evaluation circuit 13 is included in units of super blocks. Macroblock: 11 superblocks in the horizontal direction. In addition, when the code is transmitted, the DCT coefficient of the block is converted into a code determined by the number of consecutive zero coefficients and the amplitude of the non-zero coefficient, and these are transmitted as a set to transmit the code of the block. Finally, an end of block signal is added. Then, the motion vector of the motion correction performed in units of super blocks is added and transmitted in units of macro blocks.

For the transmission signal shown in FIG. 58,
Further explanations will be given on particularly relevant matters. First
The line synchronization (SYNC) signal indicates a frame synchronization signal in the decoder, and one timing synchronization signal is used for one frame to generate all timing signals of the decoder. The NMP signal on the first line indicates the number of video data from the end of this signal to the beginning of the macroblock of the next frame. This is because the code is configured by adaptively switching between the intra-frame coding process and the inter-frame coding process, so that the code amount of one frame differs for each frame, and the code position differs. This is because of Therefore, the position of the code corresponding to one frame is indicated by the NMP signal.

Further, as a countermeasure when the user changes the channel, periodical intraframe processing is performed. That is, in this band compression system, as described above, 11 super blocks in the horizontal direction are called macro blocks, and 44 super blocks exist in the horizontal direction of one screen. That is, in one frame, there are a total of 240 macroblocks of 4 macroblocks in the horizontal direction and 60 macroblocks in the vertical direction. And in this band compression system, FIG. 59 (a)-(h)
As shown in FIGS. 60 (a) to 60 (c), refresh is performed in units of four macroblocks in each vertical column of superblocks, and all superblocks are refreshed in 11 frame cycles. That is, as shown in FIG. 60 (d), the refreshed super block is accumulated for 11 frames, so that the intra-frame processing is performed in all the areas.
Therefore, for example, during normal reproduction of a VTR (video tape recorder) or the like, the above-described intraframe processing is performed at an 11-frame cycle, so that a reproduced image can be viewed without any problem.

Head data is inserted at the beginning of the macroblock. This head data contains
The motion vector, field / frame determination, PCM / DPCM determination, quantization level, etc. of each super block are inserted together.

By the way, the band compression system described above is
It is used as an encoder for band compression of television signals, and the decoder is used on the receiving side. Now, consider recording the above transmission signal in a VTR.
A general VTR is a system in which a video signal of one field is converted into a fixed length code, a certain amount of information is generated, and recorded on X (X is a positive integer) tracks.

On the other hand, if the transmission signal obtained by the band compression system is used as it is for recording / reproduction on the VTR, the variable length code is used as it is for the intra-frame processing and the inter-frame processing. The position where the code processed in the frame is recorded is not fixed, and a block that is not refreshed may occur during high speed reproduction.

More specifically, FIG. 61 shows a track pattern when the variable-length coded signal as described above is helically recorded on the magnetic tape 26. In track patterns T ₁ through T _11, a portion indicated by a thick line indicates the switching position of the frame F ₁ to F _11. The switching positions of the frames F _{1 to} F ₁₁ are not aligned because the record data is created by the variable length code. In the magnetic tape 26, when normally reproduced by a VTR, all track patterns T _{1 to} T ₁₁ are sequentially scanned by the magnetic head. Therefore, by passing the reproduction output to the decoder, no problem occurs. It is possible to reproduce various video signals. That is, at the time of normal reproduction, it is possible to reproduce all the intra-frame processed codes and the inter-frame processed codes recorded on the magnetic tape 26, so that an image can be constructed using all the codes.

However, in the VTR, there are cases in which only a limited number of tracks are reproduced, such as the double speed reproduction mode in special reproduction. At this time, the magnetic head jumps the track and picks up the recording signal. In this case, there is no problem if the tracks of the signal subjected to the intra-frame coding process are reproduced one after another, but if the tracks subjected to the inter-frame coding process are reproduced, only the image by the differential signal is obtained.

FIG. 62 shows the trace loci X _{1 to} X ₁₁ of the magnetic head when the double speed reproduction is performed. Figure 6
In Fig. 2, since the signals subjected to the intra-frame coding processing are dispersed and recorded in the frames F _{1 to} F ₂₄ , the position of the intra-frame processing portion reproduced in the screen is indefinite. The signals processed in the frame that can be reproduced at the double speed reproduction are shown in FIGS. 63 (a) to (h) and FIGS. 64 (a) to (c). And these 1
When one frame is accumulated, as shown in FIG. 64 (d),
There is no code for which intra-frame processing is performed periodically, that is, there is a portion where a refreshed super block does not exist, and a portion that cannot compose a reproduced image occurs.

[0018]

As described above, the helical scan type recording / reproducing apparatus having the conventional band compression system has a problem that high-speed reproduction such as double-speed reproduction becomes difficult.

Therefore, the present invention has been made in consideration of the above circumstances, and an object thereof is to provide an extremely good band-compressed signal processing device capable of easily obtaining a good reproduced image at high speed reproduction. Another object of the present invention is to provide a device capable of recording a wideband signal for a long time such as a high definition TV.

[0020]

A band-compressed signal processing device according to the present invention forms a (a is a positive integer) image area in a video signal of one screen, and a frame is generated for this video signal. Intra-frame encoding processing is performed by creating intra-frame processing signals that have been subjected to intra-frame encoding processing using information in frames and inter-frame processing signals that have been subjected to inter-frame coding processing using difference information between frames. After that, an inter-frame coding process is performed, and a band compression unit that adaptively repeats this signal processing method according to the motion evaluation of the input video signal, and one frame with f frames (f is an integer of f ≧ 2) as a cycle. Refresh encoding processing means for periodically performing intraframe encoding processing on signals of b image areas of a areas for each;
A means for recording / reproducing a band-compressed signal that has been subjected to a band-compressing means, and a signal for which refresh encoding processing has been performed around a specific position where the head traces and the envelope becomes maximum during high-speed reproduction of the recording / reproducing means It is something that is done.

[0021]

According to the above construction, since the signal subjected to the intra-frame coding processing can be accurately obtained at the time of high speed reproduction, a good reproduced image can be obtained.

[0022]

Embodiments of the present invention will be described below in detail with reference to the drawings. The new configuration is shown by a double frame in the block diagram. 1. Basic Configuration FIG. 1 is a diagram showing the basic configuration of the present invention.

The video signal input terminals 27, 28 and 29 are supplied with a luminance signal Y and color signals U and V for a high quality TV or the like.

After subjecting these signals to necessary preprocessing, the blocking circuit 30 constitutes a block having a pixel configuration which will be described later in Chapter 2 and inputs the block to the input terminal 11.

The video signal input to the input terminal 11 is supplied to the subtraction circuit 12 and the motion evaluation circuit 13, respectively. The subtraction circuit 12 performs a subtraction process described later, and the output thereof is a DCT (discrete cosine transform) circuit 14
Entered in. The DCT circuit 14 has 8 pixels in the horizontal direction and 8 pixels in the vertical direction as a unit block (8 × 8 pixels = 64 pixels)
And outputs the coefficient obtained by converting the pixel array from the time domain to the frequency domain. Then, each coefficient is quantized by the quantization circuit 15. In this case, the quantization circuit 15
Has 10 or 32 types of quantization tables, and each coefficient is quantized based on the selected quantization table. The quantizing circuit 15 is provided with a quantizing table so that the amount of information generated and the amount of information sent are within a certain range.

The coefficient data output from the quantizing circuit 15 is zigzag-scanned from the low frequency band to the high frequency band for each unit block, and is extracted.
It is inputted to 6 and variable-length coded by combining the number of zero coefficients (run length) and the non-zero coefficient as one set. The encoder is a variable-length encoder having a different code length depending on the frequency of occurrence of Huffman code or the like. Then, the variable-length coded data is input to a FIFO (first-in-first-out) circuit 17 and read out at a prescribed speed, and then, via an output terminal 18, a multiplexer in the next stage (not shown). [Control signal, voice data, sync data (SYN
C), NMP and the like described later are multiplexed] and sent to the transmission path. Since the output of the variable length coding circuit 16 has a variable rate and the rate of the transmission path is a fixed rate, the FIFO circuit 17 serves as a buffer that absorbs the difference between the generated code amount and the transmitted code amount. .

The output of the quantization circuit 15 is input to the inverse quantization circuit 19 and inversely quantized. Further, the output of the inverse quantization circuit 19 is input to the inverse DCT circuit 20 and returned to the original signal. This signal is input to the frame delay circuit 22 via the adder circuit 21. The output of the frame delay circuit 22 is supplied to the motion compensation circuit 23 and the motion evaluation circuit 13, respectively. Motion evaluation circuit 13
Is the input signal from the input terminal 11 and the frame delay circuit 2
The output signal of 2 is compared to detect the overall motion of the image, and the phase position of the signal output from the motion compensation circuit 23 is controlled. In the case of a still image, the original image and the image one frame before are compensated so as to match each other. The output of the motion compensation circuit 23 can be supplied to the subtraction circuit 12 via the switch 24, and can also be fed back from the addition circuit 21 to the frame delay circuit 22 via the switch 25.

Next, the basic operation of the above system will be described. 2. The signal input to the pixel configuration input terminal 11 forms a block, a super block, and a macro block by collecting a plurality of effective pixels in one screen. This configuration is based on DigiCipher
The example is based on MPEG, DSC-HDT
It goes without saying that the block configuration used in the V: Zenith + ATT method or the like may be used.

The definition of the block configuration will be described with reference to FIG.

One screen: FIG. 2 (a) is composed of 1050 scanning lines and is interlaced.

The effective pixels are composed of 1408 pixels in the horizontal direction and 960 pixels in the vertical direction.

A video signal for one screen is processed by four processors.

One screen in FIG. 3 and a super block address (SBA = abbreviated as Super Brochck Address)
Shows the relationship with.

There are 44 super blocks in the horizontal direction and 60 super blocks in the vertical direction. Therefore, there are 2640 super blocks in one screen. The address S. B. Assign A.

Supposing that the horizontal superblock address is x and the vertical superblock address is y. B. There is a relationship of A = 60 · x + y.

Block: As shown in FIG. 2 (d), it is an area of 64 pixels which is composed of 8 pixels in the horizontal direction and 8 pixels in the vertical direction.

Super block: As shown in FIG. 2 (c), it is a region consisting of 4 blocks in the horizontal direction and 2 blocks in the vertical direction of the luminance signal. In this area, the color signals U, V
1 block each is included. The image motion vector obtained from the motion evaluation circuit 13 can be set in units of super blocks.

Macroblock: As shown in FIG. 2B, it is 11 superblocks in the horizontal direction. In addition, when the code is transmitted, the DCT coefficient of the block is converted into a code determined by the number of consecutive zero coefficients and the amplitude of the non-zero coefficient, and these are transmitted as a set to transmit the code of the block. Finally, an end of block signal is added. Then, the motion vector of the motion correction performed in units of super blocks is added as overhead data in units of macro blocks and transmitted.

That is, in this band compression system, as described above, 11 super blocks in the horizontal direction are called macroblocks, and 4 in the horizontal direction of one screen.
There are 4 super blocks. That is, one frame has 4 macroblocks in the horizontal direction and 60 in the vertical direction.
There will be a total of 240 macroblocks of macroblocks. Then, in this band compression system, as shown in FIG.
As shown in (a) to (h) and FIGS. 5 (a) to (c),
Refresh is performed for each column of four superblocks in units of four Maroku blocks, and all superblocks are refreshed in a cycle of 11 frames.
That is, as shown in FIG. 5D, the refreshed super block is accumulated for 11 frames, so that the intra-frame processing is performed in all areas. 3. Intra-frame / inter-frame coding The first basic operation of this system is intra-frame coding processing and inter-frame coding processing.

The intraframe coding process is performed as follows. When this process is performed, the switch 24,
25 are both off. The video signal of the input terminal 11 is D
The CT circuit 14 converts from the time domain to the frequency domain,
It is quantized in the quantization circuit 15. This quantized signal is subjected to variable length coding processing and then output to the transmission line via the FIFO circuit 17. The quantized signal is returned to the original signal by the inverse quantization circuit 19 and the inverse DCT circuit 20, and delayed by the frame delay circuit 22. Therefore, in the intra-frame coding process, it is equivalent to that the information of the input video signal is variable length coded as it is. This intra-frame processing is performed in a proper cycle in units of predetermined blocks and scene changes of the input video signal. The periodic in-frame processing will be described later.

Next, the interframe coding process will be described. When the interframe coding process is executed, both switches 24 and 25 are turned on. Therefore, the subtraction circuit 12 obtains a signal corresponding to the difference between the input video signal and the video signal one frame before. This difference signal is
It is input to the DCT circuit 14, converted from the time domain to the frequency domain, and quantized by the next quantization circuit 15. Further, since the differential signal and the video signal are added by the adding circuit 21 and input to the frame delay circuit 22,
A predicted video signal that predicts the input video signal from which the differential signal was created is created and input.

Generally, the generated code amount of the image processed in the frame is larger than the generated code amount of the image processed in the inter-frame. 4. 4. Intra-frame / inter-frame switching process 4.1 Image adaptive intra-frame process Switching between the intra-frame coding process and the inter-frame coding process is controlled by the intra-frame / inter-frame determination circuit 31. There are two types of control methods.

First of all, the first method is to perform inter-frame processing on a signal having inter-frame correlation and to perform intra-frame processing on a signal having no inter-frame correlation in accordance with the content of an input video signal. It is a technique. When a scene change or the like occurs, in-frame processing is performed.

The intra-frame / inter-frame determination circuit 31 compares the prediction error energy between the current frame signal from the input terminal 11 and the prediction signal output from the motion compensation circuit 23 with the current signal energy.

In FIG. 6, input terminals 11, 32, 33
And the output terminals 34 and 35 are the input terminals 11 and 3 of FIG.
2, 33 and the output terminals 34, 35 are the same.

The current signal is input to the input terminal 11. While inputting this current signal to the energy comparison circuit 36,
Input to the subtraction circuit 37. The prediction signal output from the motion compensation circuit 23 is input to the input terminal 33, and the subtraction circuit 37 calculates a prediction error which is the difference between the current signal and the prediction signal.

The current signal is the current signal energy calculation circuit 36a.
Then, the prediction error is calculated by the prediction error energy calculation circuit 36b, and the energies are compared. Examples of energy calculation formulas for the current signal and the prediction error are as follows.

[0048]

[Equation 1] FIG. 7 shows an example of the intra-frame / inter-frame discrimination method in the energy comparison circuit 36.

In the figure, the horizontal axis represents the energy of the current signal and the vertical axis represents the energy of the prediction error. Also,
The solid line drawn from the origin 0 in a slanted line shows the case where the energy of the prediction error and the energy of the current signal are equal.

In the area below this solid line, the energy of the prediction error is smaller, so inter-frame processing is performed. Also, since the energy of the current signal is smaller above the solid line, intra-frame processing is performed.

The output of the energy comparison circuit 36 outputs the intra-frame / inter-frame discrimination signal adapted to the input signal, the addition circuit 38 combines the signals, and the combined signal is output from the output terminal 34. 4.2 Forced intra-frame processing (refresh) The second method is a method of forcibly performing intra-frame processing regardless of the correlation of video signals. In this case, the in-frame processing is periodically performed on a predetermined area of the screen.

There are two purposes for performing this forced in-frame processing.

1. It is necessary for the user to be able to recognize the image within a certain time when the channel is changed. This is so that special reproduction can be realized in a recording medium such as a VTR or a disc.

This forcible in-frame processing is called refreshing. Further, the time required for refreshing a predetermined area is named refresh time.

This refresh generation circuit 39 is shown in FIG.
As shown in (4), a synchronizing signal is input from the input terminal 32, and an in-frame selection signal is generated at a predetermined cycle in synchronization with this synchronizing signal. This signal and the intra-frame / inter-frame discrimination signal of the energy comparison circuit 36 are added by the adder circuit 38, and the intra-frame / inter-frame switching signal is output from the terminal 34. 5. Refresh Next, the refresh of each method will be described in detail. 5.1 DigiCipher Refresh In DigiCipher, as described above, 11 super blocks in the horizontal direction are called macro blocks, and 44 super blocks exist in the horizontal direction of one screen. That is, in one frame, there are a total of 240 macroblocks of 4 macroblocks in the horizontal direction and 60 macroblocks in the vertical direction. Then, in this band compression system, FIGS. 4 (a) to 4 (h) and 5 (a) to
As shown in (c), refreshing is performed in units of four macroblocks in each vertical column of superblocks, and all the superblocks are refreshed in 11 frame cycles. That is, as shown in FIG. 5D, the refreshed super block is accumulated for 11 frames, so that the intra-frame processing is performed in all areas.

The merit of this refresh is that the capacity of the rate buffer may be small because the refresh is performed uniformly for each frame.

This DigiCipher refresh is shown in FIG. 8 using the super block address shown in FIG.

In the figure, the vertical axis indicates the super block address, the horizontal axis indicates the frame number, and the blackened portions indicate the intra-frame processed portions. Only refresh is shown in FIG.

In the figure, frame numbers F _{0 to} F ₁₀
In 11 frames, all the super blocks on one screen are refreshed.

Since the same processing is performed by the four processors, the refresh operation of one processor shown in FIG. 8 will be used to describe the DigiCipher refresh operation with reference to FIG.

That is, S. B. Address = 0 to 659
Will be described.

In FIG. 9A, the portions subjected to the refresh and image adaptive intra-frame processing are shown in black.

For example, assuming that a scene change occurs at F ₀ , S.S. B. In-frame processing is applied to all areas of addresses 0 to 659. Further, in F ₁₄ , S. B. In-frame processing is performed in the area of addresses 0 to 59.

FIG. 9B shows the refresh time of DigiCipher. A part of the area is refreshed per frame, and the refresh is completed in the 11-frame period, so that 11 frames are the refresh time. In addition, this refresh completes the refresh of one screen no matter what 11-frame period. That is, the refresh is completed in the 11 frame periods of F _{0 to} F _{10 and} the 11 frame periods of F _{1 to} F ₁₁ .

As shown in FIG. 9C, the minimum acquisition time is one frame period, which is obtained when the initialization starts when a scene change occurs.

The maximum acquisition time shown in FIG. 9D is 11 frame periods when no image adaptive intra-frame processing occurs.

When high-speed reproduction is realized by recording in the VCR and using only the refresh block, at each refresh block address, as shown in FIG. It becomes the recording interval of the VCR. 7. The DCT two-dimensional DCT circuit (14 in FIG. 1) will be described.

First, the image is divided into small blocks (N × N) each consisting of N pixels in the horizontal and vertical directions, and two-dimensional DCT is applied to each block. The size of N at this time is set to 8 to 16 from the conversion efficiency. In this embodiment, N =
8 is used.

The transform coefficient of the two-dimensional DCT is given by equation 1, and its inverse transform equation is given by equation 2.

[0070]

[Equation 2] Here, F (0,0) represents the coefficient of the DC component, and F (0,0)
(U, v) includes a high frequency horizontal frequency component as u increases, and includes a high frequency vertical frequency component as v increases.

First, the nature of the coefficient of the DC component of F (0,0) will be described. F (0,0) corresponds to a DC component representing the average luminance value in the image block, and its average power is usually considerably higher than other components.

Further, when the DC component is roughly quantized, noise (block distortion) peculiar to the orthogonal transformation, which is visually noticeable as a large image quality deterioration, occurs. Therefore, F (0,0)
Is assigned a large number of bits (usually 8 bits or more) and is uniformly quantized.

Next, the conversion coefficient F (u, v) excluding the DC component
Describe the nature of. The average value of F (u, v) is
It becomes "0" excluding that of the DC component F (0,0).

When a certain number of bits are assigned to a small block of an image for encoding in order to perform efficient encoding, a large number of encoding bits are allocated to the transform coefficient of the low frequency component, and conversely. By allocating a small number of coding bits to the conversion coefficient of the high-frequency component and performing coding, it is possible to reduce image quality deterioration and perform coding at a high compression rate.

The image is converted into a small block of 8 × 8 = 64 pixels consisting of 8 pixels in both the horizontal and vertical directions, and the two-dimensional D
When CT is applied, the converted coefficients for each frequency component become 8 × 8 = 64 two-dimensional coefficients as shown in FIG. In FIG. 10, the upper left is the DC coefficient (direct current component).
The other 63 are AC coefficients (AC components), and the spatial frequency becomes higher toward the lower right. Since the AC component has a two-dimensional spread, it is converted into one dimension by zigzag scanning shown in the order of 0 to 63 during encoding and transmission.

Here, the 64 DCT coefficients are converted to DCT _i
It is represented by [i = 0 to 63].

In the case of an image signal, the number of quantization bits for quantizing each pixel is often 8 bits.

The DCT coefficient of the output obtained by DCT converting the 8-bit pixel may be represented by 12 bits. 8. Quantization Next, the quantization circuit (15 in FIG. 1) will be described.

The above-mentioned 64 DCT coefficients are linearly quantized with a different step size for each coefficient position using a quantization table that defines a quantization step size for each coefficient.

There are two kinds of quantization step setting methods, but basically the same method.

The first method is a method of transmitting a code indicating the quantization table using a quantization table in which a quantization step is determined for each of 64 DCT coefficients.

FIG. 11 shows an example of the quantization table. In the figure, q = 0 to q = 9 are quantization table codes that represent a quantization table, and by transmitting this code, the decoder can perform inverse quantization.

Further, 64 numbers arranged in a square represent the number of quantization bits, and have a correspondence relationship with the 64 two-dimensional coefficients shown in FIG. For example, 7 at the upper left of the quantization table for q = 0 indicates that the DC component is quantized with 7 bits.

Similarly, each coefficient is quantized by the number of bits shown in the quantization table.

In the second method, first, 64 DCT coefficients are weighted by a weighting matrix.

After this, the quantization width data QS (Quantize-S
cale) is used to uniformly divide each coefficient and then quantize it. When transmitting, a code corresponding to the quantization width data is sent. Also, the weighting matrix has a default value. Furthermore, it is possible to transmit a specific type of weighting matrix.

As an example, MPEG. In I, 5 bits are assigned to the code of the quantization width data QS, and 32 types can be designated. Therefore, this value is set to QS _j [j =
0 to 31].

Here, the quantization width data QS _{j will be} defined.

The coefficient value of the DCT is quantized with the maximum number of quantization bits, and the case of quantization is represented by j = 0, and QS ₀ = 1.

Further, j = 31 is represented when the DCT coefficient value is not transmitted, and at this time, the number of quantization bits described later is QL ₃₁ = 0.

Here, j is named a quantization level.

FIG. 12 shows MPEG. The default value of the weighting matrix of the luminance signal used in I is shown.

In the figure, 64 numbers of 8 × 8 are
There is a correspondence relationship with the 64 two-dimensional coefficients shown in FIG. 10, and the weighting value for each DCT coefficient is shown.

In the encoder, each DCT coefficient is divided by the corresponding weighting value and the quantization width data QS.

The coefficients of 64 DCTs are represented by DCT _i = [i =
0-63] and each value of the weighting matrix is WE
IGHT _i [i = 0 to 63] When each value after quantization is represented by Q _i [i = 0 to 63],

[0096]

[Equation 3] It is represented by.

The number of quantization bits at this time is

[0098]

[Equation 4] It is represented by.

An example is shown below.

MPEG. First vertical direction of I luminance signal
The th AC component is represented by DCT ₁ in FIG. 10 described above.

The value corresponding to DCT ₁ of the weighting matrix is WEIGHT ₁ = 16. This is shown in FIG.
It corresponds to the part marked with a circle. Further, when the quantization width data QS ₀ = 1

[0102]

[Equation 5] Since the coefficient of DCT _i is represented by 12 bits, log ₂ D
The maximum value of CT _i is 12. The number of quantization bits at this time is

[0103]

[Equation 6] Becomes

FIG. 13 shows the maximum required number of quantization bits after passing through the weighting matrix when QS ₀ = 1. This figure is a matrix representing the number of quantization bits of 8 × 8 = 64, and each number indicates the number of quantization bits corresponding to each position of the DCT coefficient shown in FIG.

FIG. 14 and FIG. 15 quantitatively show typical nine types of quantization tables among the quantization tables when 32 types of quantization width data QS _j are set.

In order to explain the case of using the above-mentioned second method regarding the quantization table, this table is based on the quantization width data QS.

Here, j = 31 is an example in which data is not generated at all, and corresponds to quantizing all coefficients with 0 bits. Further, j = 0 is the quantization width data QS ₀ = 1
Therefore, it is equivalent to quantization with a weighting table. That is, in this case, the bit allocation is based on the weighting table shown in FIG.

In FIGS. 14 and 15, the horizontal axis is DCT.
64 of each coefficient are shown, which corresponds to the order of the zigzag scanning shown in FIG. In addition, the vertical axis represents the number of bits to be transmitted in each coefficient of DCT.

When the DCT coefficient is quantized, M
SB (Most Significant Bit) to LSB (Least Sign
ificant Bit) exists. When limiting the number of bits to be transmitted, naturally, the MSB is preferentially transmitted.

As described above, if the number of quantization bits for the DC component is reduced, block distortion or the like becomes conspicuous. Therefore, there is an example of separately treating the DC component or assigning a certain number of quantization bits. Here, it is assumed that 8 bits are assigned.

MPEG. In the case of the luminance signal of I, the maximum value of the AC component is 8 bits as described above.

The number of quantization bits and the quantization width data will be quantitatively described with reference to FIGS. 14 and 15.

The generated code amount becomes maximum when j = 0, and the generated code amount decreases as j increases, and j =
It becomes 0 at 31 and no code is generated.

It is possible to control the code amount generated by controlling the quantization width data. 9. Necessary Conditions for High Speed Reproduction Next, conditions required for high speed reproduction will be described. 9.1 Swap of Refresh Block Codes First, an example of the simplest case will be described.

In the conventional example, one screen 264 is composed of 11 frames.
Intra-frame coding processing is applied to 0 areas, so 1
The number of areas a in the screen is a = 2640, and the intraframe coding processing period f is 11 frames. Further, in order to explain the case where one track is divided into two and the average video code for one frame is recorded in one track, the number of divisions of one track d
= 2, the number of tracks for recording an average video code for one frame is c = 1. Therefore, the number of recording medium areas d × c ×
f = 2 × 1 × 11 = 22. Correspondence between the screen area of the refresh block and the recording medium area will be described with respect to the case where the 1: 1 correspondence is made. Number of screen areas in one recording medium area e = a / d × c × f = 2640/2 × 1 ×
11 = 120, and e = 120 for each d × c × f
The case of associating with 22 areas will be described.

FIG. 16 shows the operation timing of this system.

Referring to FIG. A sync signal of the input video signal is supplied to the input terminal 32. The sync signal is input to the sync signal detection circuit 40 and detected.
The sync signal detection circuit 40 generates a sync pulse synchronized with the sync signal from the output terminal 41 and supplies it to the track formation signal generation circuit 42.

FIG. 16A shows an input video signal, Y is a luminance signal, U and V are chrominance signals, and the number written in the frame shows the frame number. FIG.
16B shows a sync pulse of the output terminal 41 obtained from the sync signal detection circuit 40, which is generated in synchronization with the switching point of the frame of the input video signal shown in FIG. 16A. FIG. 16C shows a track formation signal generation circuit 42.
The track formation signal obtained from FIG. A and B attached to the track forming signal specify a period in which the A head and the B head of the rotary drum 43 alternately form tracks. As shown in FIG. 1, the A head and the B head are mounted at positions facing the rotary drum 43 by 180 °. In this embodiment, FIG.
16B shows the timing of generating the synchronizing pulse shown in FIG.
The switching timing of the track forming signal shown in (c) is synchronized. FIG. 16D shows tracks formed by the A head and the B head, and the numbers written in the frame show the track numbers.

The track formation signal output from the track formation signal generation circuit 42 is supplied to the track formation control circuit 44. This track formation control circuit 44
Controls the rotation phase of the rotary drum 43. Further, the sync pulse of the sync signal detection circuit 40 is replaced by the code replacement circuit 45.
By inputting to the head, the timing of supplying the recording signal to the A head and the B head is controlled.

Next, the code exchange method used in this embodiment in order to enable the high speed reproduction of the VTR will be explained. First, the luminance signal Y and the chrominance signals U and V supplied to the input terminals 27, 28 and 29 are combined by the blocking circuit 30, and the subtraction circuit 12 and the motion evaluation circuit from the input terminal 11 serve as input video signals. Is being supplied to 13
The variable-length coding circuit 16 outputs the band compression-coded video code.

Here, in the conventional band compression system shown in FIG. 57, the video signal is variable length coded.
As shown in (i), the switching points of the frames of the video code differ from frame to frame. The NMP signal shown in FIG. 16 (h) indicates the switching point of the frame of this video signal. Conventionally, 264 per frame
There are 0 super blocks and this 2640
16 super blocks are included in one frame period indicated by the NMP signal in FIG.

Further, conventionally, four macroblocks exist in the horizontal direction on one screen, and these macroblocks are composed of 11 super blocks. Then, one superblock in the macroblock per frame is forced to use the intraframe processing. The sequence in which the in-frame processing is forcibly used is included in the system control signal shown in FIG. Here, the super block for which the intra-frame processing is forcibly performed is referred to as a refresh block, and the super block for which the intra-frame processing is not forcibly performed is referred to as a non-refresh block. FIG. 2 shows the relationship between macroblocks, refresh blocks, and non-refresh blocks.

Here, as the definition of words, refresh block: When intra-frame processing is forcibly performed by one super block in one frame period of a macro block, the super block subjected to this intra-frame processing is called a refresh block. . A macro block consists of 11 super blocks, so 1
In-frame processing is forcibly performed in one frame cycle.

Non-refresh block: A super block other than the refresh block described above. Within this super block, there are a block subjected to intra-frame processing and a block subjected to inter-frame processing depending on the contents of the image. For example, when a scene change or the like occurs in the input video signal, in-frame processing may be used, but this is also a non-refresh block.

Here, 240 refresh blocks (= 2640/11) exist in one frame period. Therefore, conventionally, there are 240 refresh blocks in one frame period shown in FIG. 16 (h) as shown in FIG. 16 (g). Then, the conventional signal is directly applied to V
When recording in TR, the position of the refresh block is not fixed and high-speed reproduction cannot be performed as described above.

FIGS. 17A and 17B show video signals of frame numbers F ₅ and F ₆ , respectively. In the figure, the portions indicated by G ₅ and G ₆ indicate refresh blocks, and the portions indicated by H ₅ and H ₆ indicate non-refresh blocks. Then, thereafter, the frame number, during the refresh block number and the non-refresh block number, frame number F _n (n is an integer) the refresh block number G _n frames, the non-refresh block number and H _n.

In the present invention, the arrangement of the refresh block and the non-refresh block on the track is different.

In this embodiment, one track is divided into two and recorded. When one track is divided into two, high-speed reproduction can be performed up to double speed. Three
At the time of high speed reproduction of twice or more, all refresh blocks cannot be reproduced, so that an area in which an image cannot be formed occurs as in the case shown in FIG. 64 (d).
If, as a VTR specification, high-speed reproduction at 20 times speed is desired, one track may be divided into 20. Further, when it is desired to realize fast high speed reproduction, refresh blocks may be arranged on the track at equal intervals.

FIG. 16E shows a timing pulse for dividing one track into two, and the one track period shown in FIGS. 16B and 16C is divided into two substantially equal parts. Then, this one divided period is referred to as a sector.

In other words, as the definition of the word, sector: one track period is divided into approximately equal parts (2 in this case).
The divided period.

In this embodiment, 120 refresh blocks are put in one sector as shown in FIG. 16 (f). In this way, one track consists of two sectors, so 240 refresh blocks are inserted in one track, which is equal to the number of refresh blocks in one frame of the video signal. That is, 1
The number e of refresh blocks in a sector is e = b / c × d, where b is the number of superblocks on which periodic intraframe processing is performed and b intraframe processed signals are recorded on c tracks. (In this case 240/1 ×
2 x 120).

By performing the code exchange as described above, the refresh block for one frame is conventionally arranged in one frame period indicated by the NMP signal, but the refresh block for one frame is replaced in one track period. Can be arranged to be present.

FIG. 18 shows a track pattern.
That is, the tracks T _{1 to} T on the magnetic tape 26
G _{1 to} G ₁₁ entered in the frame of ₁₁ correspond to the refresh block number G _n described above. The relationship between the refresh block and the track T _n is that the refresh block with the number G _n is recorded in the track T _n . Further, H _{1 to} H ₁₁ entered in the frames of the tracks T _{1 to} T ₁₁ correspond to the above-mentioned non-refresh block number H _n . The switching point of the non-refresh block is the thick line portion shown in the frame of the tracks T _{1 to} T ₁₁ .

The relationship between sectors and tracks is shown in the track 46 of FIG. The track 46 is divided into two and d =
It is divided into two sectors. In this one sector, e
= 120 refresh blocks are arranged. The non-refresh block is inserted between the refresh blocks.

[0135] Here, if the track T _5, T ₆ will be described in detail as an example, to record the refresh block G ₅ of the frame F ₅ in the track T _5. Also, track T ₆
The refresh block G ₆ of the frame F ₆ is recorded in. A non-refresh block is recorded in the free space where this refresh block is arranged. The non-refresh blocks H ₅ and H ₆ are recorded on the track T ₅ , and the track T ₅ is recorded.
The ₆ records the non-refresh block H _6, H _7.

Therefore, in order to realize the above-described recording form, the band compression coded video code obtained from the variable length coding circuit 16 in FIG. 1 is supplied to the code swapping circuit 45 again. Further, the refresh timing generation circuit 39 generates the code position signal of the refresh block described above from the output terminal 35, and the code position signal is supplied to the code exchange circuit 45. The code exchange circuit 45 rearranges the variable length code into the refresh block and the non-refresh block based on the sync pulse and the code position signal of the refresh block.

That is, the process of inserting 120 refresh blocks in each of the two sectors provided in one track is performed. In order to perform this processing, the code is once stored in a memory (not shown), and when the code is read from the memory, 120 refresh blocks are read in one sector.

The output of the code exchange circuit 45 is
It is supplied to the index insertion circuit 47. The index inserting circuit 47 inserts an index signal into the control data portion of each sector so that it can be detected at the time of reproduction that the non-refresh block is partially separated and recorded. The index signal is prepared by the index generation circuit 48 to which the code position signal from the refresh timing generation circuit 39 is supplied. Then, the output of the multiplexer 49 including the index inserting circuit 47 is recorded on the magnetic tape 26 via the ECC circuit 50, the unit sync inserting circuit 51, and the modulating circuit 52.

FIGS. 19A and 19B show trace traces X _{1 to} X ₁₁ of the head during double speed reproduction.
Note that the refresh block G _n and the non-refresh block H _n are shown in the frame of each track T _{1 to} T ₂₂ as in FIG. 18. Then, in the head trace during the double speed reproduction shown in FIG. 19, reproducible refresh blocks are shown in FIGS. 20 (a) to 20 (h) and FIG. 21 (a).
~ (C). The frames 1 to 11 shown in FIGS. 20A to 20H and FIGS. 21A to 21C are the same as those shown in FIG.
Head trace locus X ₁ during double speed reproduction shown in 9 (b)
Shows a reproducible refresh blocks to X _11.

For example, in frame 1, by performing head trace X ₁ , it is possible to display refresh block G ₁ in the upper half of the screen and refresh block G ₂ in the lower half of the screen. Similarly, in the frames 2 to 11, the refresh block G ₃
Up to G ₂₂ can be reproduced. Therefore, when reproducible refresh blocks are accumulated in frames 1 to 11, the codes of all screen areas can be reproduced as shown in FIG.

The code subjected to inter-frame processing and the code subjected to intra-frame processing according to the content of the image are put between the codes subjected to the intra-frame coding processing periodically. Then, these codes have no correspondence between the image area and the recording medium area.

As the recording medium, the magnetic tape 26
However, the present invention can be applied to a video disc as well, and in this case, one round of the disc corresponds to one track of the tape. 9.2 Refresh block code amount High-speed reproduction is possible by inserting a refresh block in a predetermined area on the VTR track, but it is necessary to prevent the code amount from exceeding the recordable code amount in the predetermined area. .

The code amount of a predetermined refresh block is
When the amount of code that can be recorded in a predetermined area of the recording medium is exceeded, refresh is not performed at the position on the image corresponding to the exceeded code.

Even if this is not avoided, since the refresh is performed from a certain position on the image, it is highly possible that the contents of the image can be determined, but the refresh is performed more reliably. It is necessary to control the generated code amount of the refresh block.

Therefore, first, the code amount of the refresh block will be described in detail. 9.2 Refresh block code amount First, when DFT is not used as the servo of the VTR and a video signal is recorded by c = 1 head scan per frame and i = 2 × speed is realized as the special reproduction speed, A case will be described in which the code amount of the refresh block is calculated for each 1 / c × i = 1/2 area of the image. When the maximum recording code amount that can be recorded on P = 1 track formed by one scan of the code amount of this refresh block is α, the code amount of the refresh block in the area of 1/2 of one frame is α / c. × i = α / 2 or less. An example in which the VTR head scan is one scan and the average code amount of the video signal of one frame is recorded will be described in detail. In addition, a case will be described in which the special reproduction speed is doubled. In the embodiment, since there are 240 refresh blocks per frame, 120 refresh blocks are recorded per sector.

22A and 22B show a refresh block in one screen and a division method when the refresh block is further divided. F _n shown in FIG. 22A indicates the screen of the nth frame. Further, G _n represents a refresh block in the nth frame. This refresh block is 240
There are individuals. In addition, G shown on the left side of the screen
_n (0) and G _n (1) represent refresh blocks obtained by dividing 240 refresh blocks into two equal parts in the vertical direction. That is, G _n (0) indicates 120 refresh blocks existing above the screen among the G _n refresh blocks. G _n (1) is
The refresh block in the lower area of the screen is shown and includes 120 refresh blocks.
FIG. 22B shows the refresh block with the frame number F _{n + 1} , and the definitions of G _{n + 1} (0) to G _{n + 1} (1) are the same as in FIG. 22A. .

Next, the track pattern of the VTR will be described. FIG. 23 shows a track pattern on the magnetic tape 26. T _{0 to} T ₁₁ indicate tracks recorded using the rotary drum 43. Here, a case where the average generated code amount of one frame is recorded on one track will be described. That is, the case of c = 1 described above will be described. This corresponds to the case where the b = 240 refresh blocks are recorded on one track. That is, the refresh block G having the frame number F _n
n will be recorded on track T _n .

In this structure, when reproducing at a double speed, the reproducing head crosses two tracks. Therefore, one track is divided into two equal parts.
While reproducing the area of 2, the reproduction signal is obtained over two tracks. Here, if one part divided into two is referred to as a sector, one track is formed per frame, so that two sector numbers S ₀ and S ₁ are assigned as shown in FIG.

Incidentally, in general, an area obtained by dividing one track into approximately equal parts is named a sector.

In order to realize high-speed reproduction at i-times speed, the head straddles i tracks, and therefore one track reproduces an area of 1 / i. Therefore, assuming that the maximum high-speed playback speed is i _max , i _max ≦
Set to the relationship of d. Then, the sector names are S _{0 to} S _d-1
Express with.

Next, the relationship between refresh blocks and sectors will be described. When recording the refresh block G _n of the frame number n in one track T _n, G _n (0)
... S ₀ , G _n (1) ... S ₁ is recorded.

If the number of refresh blocks in one sector is evenly arranged, the number of refresh blocks in one sector is as follows. That is, 1
If the number of refresh blocks per frame is b, the number of tracks for recording b refresh blocks is c, the number of track divisions is d, and the number of refresh blocks in one sector is e, then e = b / c × d Become. That is, e = 240/1 × 2 = 120.

In FIG. 23, the head traces X _{0 to} X ₄ represent the head locus at double speed. That is, in the head trace X _0, sector S ₀ of the track T ₀ (refresh block G ₀ (0)), the sector S ₁ of the track T ₁ (refresh block G
₁ (1)), sector S ₀ (refresh block G ₂ (0)) of track T ₂ can be reproduced.

Here, since the recording capacity that can be recorded in the sectors S ₀ and S ₁ of the recording medium on the tape 26 is determined,
Within this recording capacity, the refresh block G _n (0),
The generated code amount of G _n (1) must be suppressed.

That is, when the DTF is not used and the high-speed reproduction speed is i, the 1 / i area of the p tracks formed in one scan is traced.

Similarly to the above, when the maximum code amount that can be recorded on p tracks formed in one scan is α, and when a video signal is recorded by scanning c times per frame, 1
It is necessary to suppress the maximum code amount in the 1 / c × i area of the refresh block of the frame to be α / i or less as described above. In this case, the case where an extremely wide head width is not used as the special reproduction head is shown.

When the DTF is used as the servo system of the VTR, the maximum recording code amount that can be recorded on p tracks formed in one scan is α, and the video signal is recorded by c head scans per frame. In addition, it is necessary to suppress the maximum code amount of the refresh block in the 1 / c area of the video of one frame to be less than or equal to α described above. 10. Code amount control There are two types of code amount control methods. The first method is a method of controlling the quantization level as described above. In this case, since the generated code amount of the refresh block is suppressed, the image quality of the refresh block itself is deteriorated. However, in the next frame, since the difference between the intra-frame processed signal of the refresh block and the video signal of the next frame is sent, the image quality is only momentarily degraded. This method will be described in detail later.

The second method divides the code, which has been quantized once, into two, and determines the code amount of the MSB or the low frequency component by VTR.
It is a method that keeps the code amount that can be read out at the time of high-speed reproduction on a recording medium such as. Regarding this, 11. More on this in the chapter.

The control of the coded information amount when the first method is used will be described below. 10.1 Macroblock Code Amount Control When a video signal is highly efficiently coded using variable length coding as in the present embodiment, the generated information amount is generally not constant. This is because the amount of information contained in the video signal varies with time.

On the other hand, when a fixed rate transmission system is used, coding control is required to keep the coded information amount constant.

The general method of fixed rate conversion is to prepare a buffer memory at the output of the encoder, input this buffer memory at a variable rate, and perform the output at a fixed rate to smooth the encoded information amount. Is. Since the amount of data in the buffer memory changes according to the amount of input information, there is a possibility that overflow or underflow will occur. In order to prevent this, when overflow or underflow is likely, the encoding parameter is changed so as to reduce or increase the encoded information amount, respectively. For example, the quantization characteristic may be made coarser or finer.

The larger the capacity of the buffer memory is, the higher the smoothing effect is, but there is a coding delay and cost limitation.

Further, since a relatively small buffer memory allows finer control of encoding depending on the local nature of the image, a buffer memory of about 1 frame may be used.

The control of the macroblock code amount will be specifically described.

The capacity of the rate buffer is used for controlling the code amount of the macroblock. In the method using the rate buffer, as shown in FIG. 24, the encoder and the decoder are provided with rate buffers of equal capacity.

The code amount of input / output of these buffers and the occupation rate of the buffers will be described with reference to FIG.
Reference numeral a in FIG. 24 indicates an input signal to the rate buffer b of the encoder. This signal is the output signal of the variable length coding circuit 16 of the encoder. The characteristic of this signal is that each block is input at a constant cycle, but the generated code of each block is a variable length code, so that it has a variable length rate. The output signal c of the rate buffer of the encoder is transmission data, and the code is output at a fixed rate. Further, the input signal d of the rate buffer e of the decoder is a fixed rate code input, and the output signal f is a variable rate code output.

The characteristics on the encoder side and the decoder side will be described in detail with reference to FIGS. 25 and 26, respectively. The horizontal axes in FIGS. 25A to 25C and FIGS. 26A to 26C indicate frame numbers. Here, FIG.
26 (a) to (c) and FIGS. 26 (a) and 26 (b) are the same as the input frame numbers, but the frame numbers in FIG. 26 (c) are shifted by 8 frames. This is necessary in order to absorb the fluctuation of the delay time of the transmission code of the encoder and the decoder due to the use of the variable length code.

25 (a) to 25 (c) and 26 (a) to 26 (a).
The vertical axis of (c) indicates the code amount. In this example, the capacity of the rate buffer is 4 Mbits, and the transmission code amount per frame is 0.5 Mbits / frame. 25 (a) to 25 (c) are on the encoder side, FIG.
6 (a) to 6 (c) show the characteristics on the decoder side.

FIG. 25A shows the amount of generated codes per frame. The broken line in the figure is shown with reference to the capacity of the rate buffer. Since the variable length code is used, the generated code amount of each frame differs depending on the frame. In F _{1 to} F ₉ in which the frame number is represented by F _n , examples of code generation when the buffer overflows and underflows are shown. At F ₁ , a 4.5 Mbit code is generated,
F ₂ ~F occur until ₉ code is set to 0.

The maximum value of the generated code amount of each frame is determined by the sum of the buffer capacity and the transmitted code amount. In this example, the buffer capacity is 4 Mbits, and the transmitted code amount per frame is 0.5 [Mbits. / Frame], the maximum amount of code that can be generated per frame is 4.5 Mbits.
F _{20 to} F ₃₀ are examples in which the generated code amount of each frame is controlled by the occupancy of the buffer.

FIG. 25B shows the occupancy of the encoder buffer. In this example, the buffer capacity is 4M
The capacity of the buffer is indicated by a broken line. F
_{Since a} large amount of generated code is generated in ₁ frame, F
_At the time of ₁ , a buffer overflow has occurred. F
_{Since the} code is not generated at all from _{2 to} F ₉ , the buffer underflow occurs at the time of F ₉ .

FIG. 25C shows the transmission code amount from the encoder. A solid straight line A drawn diagonally in the figure shows the cumulative transmission code amount. This inclination indicates the amount of transmitted code per frame. In this example, 0.5M bits are transmitted per frame time. Frame rate is 30
In the case of [Hz], 30 × 0.5 [M / Frame] = 15
The transmission code amount is [Mbps]. The broken line shows the maximum value determined by the maximum capacity of the buffer.

The polygonal line shown in FIG. 25 (c) is
The cumulative generated code amount is shown. That is, FIG. 25 (a)
Is the integrated value of the generated code amount per one frame.
When the accumulated generated code amount contacts the broken line, the buffer overflows, and when it contacts the solid line, the buffer underflows. The dotted line drawn horizontally between the cumulative generated code amount and the cumulative transmitted code amount indicates the delay time in the encoder buffer when transmitting the generated code, and the longer one indicates the longer time until transmission. This shows that.

In FIG. 26 (a), the solid line B indicates the cumulative received code amount. This solid line B is shown in FIG.
Is the same as the real straight line A. The polygonal line indicates the projection code amount of each frame when the image is output. This is shown in FIG.
This corresponds to a value obtained by integrating the projection code amount per frame in (c). Further, the horizontally drawn dotted line represents the delay time when the received code is projected, and the sum of the delay time in the encoder and the delay time in the decoder is all equal, and the buffer delay shown in FIG. Time (Buffer D
elay).

FIG. 26B shows the occupancy of the decoder buffer. Here, FIG. 25 (b) and FIG.
Compare with (b). Figure 2 shows only the buffer delay time.
25 (b) and 26 (b), assuming that 5 (b) is the shift
And are in a vertically inverted relationship. That is,
An encoder overflow results in a decoder underflow, and an encoder underflow results in a decoder overflow.

FIG. 26C shows the projected code amount per frame of the projected code. FIG. 25 (a) and FIG.
6 (c) is delayed by the buffer delay time of the encoder and the decoder.

When the subscriber changes the channel, it is possible to output the video after accumulating the code of the required code amount in the buffer of the decoder. This accumulated amount is
It is equal to the value for accumulating the received code amount only for the time shown by the dotted line in FIG. This value has a corresponding relationship with the NMP signal of the conventional example. That is, the decoder may store the code in the buffer for the time determined by the NMP signal and then output the video.

As shown in F ₁ of FIG. 25A, when the maximum code amount occurs in the first frame, the maximum buffer delay time occurs in the decoder buffer.
In this case, it is possible to output a normal video signal after accumulating the received code in the buffer for the time indicated as buffer delay in FIG. In this case, a normal video signal is output after the buffer of the decoder is filled with the received code.

That is, the received codes are accumulated from F _{0 to} F ₈ and a normal video signal is output after the initialization state filling the buffer memory is completed. When the projection code is output in F ₁ of FIG. 26C, the buffer of the decoder is underflow. In addition, FIG.
When the state in which the projection code is not output from F _{1 to} F _{9 in} (c) continues, the buffer of the decoder overflows at F ₉ . This corresponds to the state in which the buffer state of the encoder is delayed by 8 frames and the overflow and underflow are inverted.

When the subscriber changes the channel, in order to output a normal video signal, it is necessary for the buffer of the decoder to store the code for the time according to the NMP signal. It is possible to output an incomplete image as shown by the dotted line in c).

FIG. 27 shows an example of the relationship between the buffer occupancy and the increase / decrease in the quantization level set for each macroblock. The quantization level is not changed while the occupancy of the buffer is at a predetermined value, and the quantization level is increased or decreased when the buffer occupancy exceeds the predetermined value. In FIG. 27, when the buffer occupation rate is 45 to 55%, the quantization level is not changed,
When this value is exceeded, the quantization level is changed. This makes it possible to control the rate of the buffer.

Since the quantization level is roughly quantized when the value of j is large and the generated code amount is small, the quantization level is lowered when the buffer occupancy is small, and the quantization level is decreased when the buffer occupancy is large. Operate in the raising direction.

FIG. 28 shows a configuration for realizing the above operation.

In order to determine the macro block quantization level, the quantization level setting circuit 53 and the super block code amount calculating circuit 54 are used.

First, the method of calculating the code amount of the super block will be described in detail with reference to FIG.

First, the output of the quantization circuit 15 is input to the variable length coding circuit 16. In this circuit, first, the zigzag scanning circuit 16a reads the 8 × 8 DCT coefficient by the scanning method shown in FIG. 10, combines the continuous number of 0 coefficients and the amplitude of the non-zero coefficient, and the Huffman coding circuit 16b outputs them. input.

The number of consecutive 0 coefficients and the amplitude of non-zero coefficient are input to the super block code amount calculating circuit 54.
The super block code amount calculation circuit 54 calculates the generated code amount using the ROM that stores the table shown in FIG.

Although FIG. 29 is also used in the conventional example, the horizontal axis shows the amplitude of the non-zero coefficient and the vertical axis shows the number of consecutive 0 coefficients. The numbers in the frame indicate the number of bits of the code. The number of bits of this code is added to calculate the generated code amount in units of super blocks.

Furthermore, in order to determine the quantization level of the macroblock, the macroblock code amount calculation circuit 55
The code amount of the 11 super blocks is added to calculate the code amount of the macro block.

Further, the transmission code amount stored in the transmission code amount ROM 56 is subtracted from this value, and the rate buffer code amount calculation circuit 57 calculates the occupancy rate of the rate buffer included in the code exchange circuit 45.

Based on this rate buffer occupancy rate and the graph of FIG. 27, the macroblock quantization level setting circuit 58
Then, the quantization level for each macroblock is set. 10.2 Superblock code amount control The code amount control per superblock can be controlled only in a direction in which the quantization level is coarser than the quantization level determined by the macroblock.

For example, if there is a super block processed in the frame, the code amount processed in the frame is larger than the code amount processed in the inter-frame.
This is because the code amount may be significantly increased in this super block processed in the frame.

On the other hand, the human visual characteristic is that when the contents of the image change, for example, when a scene change occurs or when a part hidden behind a moving object appears (this is called a covered back). , The eyes cannot react quickly and precisely, and a certain amount of time is required.

Therefore, in the intra-frame processing portion caused by the change in the image content, it is difficult to determine the deterioration of the image quality even if the quantization level is roughened. That is, the code amount can be reduced in the portion where the image adaptive intra-frame processing has occurred.

A configuration for realizing this operation will be described with reference to FIG.

Refresh block quantization level setting circuit 5 corresponding to the super block quantization level setting circuit
9 and the non-refresh block quantization level setting circuit 60 are input from the input terminal 61 with the image adaptive intra-frame / interval determination signal which is the output of the energy comparison circuit 36 in the intra-frame / interval determining circuit 31. In addition, the DCT circuit 1
The output signal of No. 4 is input from the input terminal 62 and input to the DCT coefficient energy calculation circuit 63, the energy of the DCT coefficient is calculated, and the correction level of the quantization level is determined by this energy. The value is input to the quantization circuit 15 through the adder 64 that adds the value to the macroblock quantization level. The relationship between this energy and the correction level is shown in FIG.
There is the relationship shown in (a).

Further, even in a super block subjected to inter-frame processing, if the energy is extremely large, it means that there are many high frequency components, and in this case also, it is difficult to determine the deterioration of the image quality. The conversion level may be coarse. In this case, the correction level is set as shown in FIG. 10.3 Refresh block code amount control As described in Chapter 9, Section 9.2, the generated code amount of the refresh block must be kept within a predetermined code amount determined by the recording medium such as the VCR.

In order to realize this, in the present embodiment, the code amount of the refresh block is calculated independently and this value is used to set the quantization level of the refresh block.
As a configuration, the refresh block code amount calculation circuit 6
5. The refresh block quantization level setting circuit 59 is used.

The generated code amount of the refresh block is output from the super block code amount calculation circuit 54, and the refresh block code amount calculation circuit 65 sequentially adds the code amounts of the refresh blocks. In this embodiment, the addition is performed during the period of 120 super blocks that are to be placed in one sector on the tape 26.

By inputting this result to the refresh block quantization level setting circuit 59, the correction value from the macro block quantization level is determined.

The refresh block quantization level setting circuit 59 also has the super block code amount control method described in Section 10.2.

The output of the refresh block quantization level setting circuit 59 is input to the quantization circuit 15 through the switch 66 and the adder 64 for adding a correction value to the quantization level of the macro block.

FIG. 31 shows an example of a refresh block quantization level setting method.

In FIG. 31, the horizontal axis represents the refresh block number. In this embodiment, the refresh block number of the sector 0 and the refresh block number of the sector 1 are shown to record the refresh block of one frame in two sectors. Further, in this example, the recording code amount α / 2 of one sector is not exceeded in 120 refresh blocks.

The vertical axis of FIG. 31 represents the code amount of the refresh block. The maximum code amount is α / 2 as described above.
Set to. Here, it is assumed that α / 2 = 250 K bits. In FIG. 31A, the solid line C is the target code amount of the refresh block, and the generated code amount is controlled so as not to exceed this line. Since this solid line C is an example for control, it need not be a straight line, and what is necessary is to suppress the generated code amount per sector to α / 2. The polygonal line D is a line showing an example of the change in the refresh block cumulative code amount. This shows the output signal of the refresh block code amount calculation circuit 65. The quantization level is determined so that the refresh block target code amount (solid line C) is not exceeded.

FIG. 32 shows the macroblock quantization level,
An example of setting the quantization level of the refresh block will be described.

As shown in FIG. 28, first, the quantization level of the macroblock is determined by the occupation rate from the buffer memory. For the quantization level of this macroblock,
By increasing the quantization level as necessary, the quantization level of the refresh block is set only in the direction of decreasing the generated code amount. The quantization level correction level indicating the quantization level of the difference between the quantization level of the macro block and the quantization level of the refresh block can be transmitted as additional data.

In FIG. 32, the horizontal axis represents the quantization level j = 31 to 0 of the macro block. It shows a state where no code is generated when j = 31 and a state where the maximum code amount is generated when j = 0. Further, the numbers entered below this are examples of the number of bits used to indicate the level for quantization level correction.

The vertical axis represents the quantization level j = 31 to 0 of the refresh block. A circle mark in the drawing indicates a quantization level that can be taken as a refresh block. In each case, a quantization level that reduces the code generation amount is assigned to the macroblock quantization level.

Since the output signal of the DCT circuit 14 is input to the refresh block quantization level setting circuit 59, by comparing with the refresh block accumulated code amount, the refresh block quantization code is set so as not to exceed the refresh block target code amount. It is possible to choose a chemical table.

Details will be described with reference to FIG.

FIG. 31 (b) is an enlarged view of the horizontal axis of FIG. 31 (a). Refresh block number 80 to 8
A method of determining the quantization level to 1 will be described with reference to FIG. First, it is assumed that the refresh block code amount calculation circuit 65 has calculated the code amounts up to the refresh block number 80, which is the code amount indicated by E in FIG. Further, it is assumed that the target code amount is determined by the refresh block number, and the refresh block number 81 has the code amount indicated by F in FIG. 31B.

If the macroblock quantization level is set at j = 15, and if there is the quantization level relationship shown in FIG. 32, j = 15, 19, 23, 27 is set as the refresh block quantization level. It is possible.

Since the refresh block quantization level setting circuit 59 is input with the coefficient signal obtained by DCT of the video signal as the output signal of the DCT circuit 14, the quantization level is set to j = 15, 19, 23, 27. The generated code amount when set can be calculated. The results are G, H,
Suppose it is decided by I and J. This generated code amount G, H, I,
By comparing J with the target code amount F, it is possible to select the refresh block quantization level j = 23 which is the code amount of I.

By thus controlling the code amount of the refresh block and inputting it to the above-mentioned code exchange circuit 45 and index insertion circuit 47 for recording, it is possible to surely perform refresh when high speed reproduction is performed. Become. 13. Bitstream structure The bitstream structure of each block is shown below.

In FIG. 1, the output of the variable length coding circuit 16 is added with the overhead data of the output of the overhead data generating circuit 67, and the result is output to the output terminal 68.

A package medium such as a VCR or a video disc requires a code exchange circuit 45 in order to realize high speed reproduction. However, when transmitting a broadcast wave,
The code exchange is not absolutely necessary.

The code exchange method depends on the number of drum rotations of the VCR, the number of heads, the tape format, the recording code amount of one track, and the special reproduction speed.

Therefore, the bit stream of the broadcast wave is transmitted by using the bit stream of the macro block shown in FIGS. 36 and 39.

The VCR bit stream output from the code exchange circuit 45 is shown in FIGS. 37, 38, and 40.
~ It is transmitted using the bit stream of the (non-) refresh block shown in Fig. 43. 14. Block Layer Bitstream Structure A block is composed of 64 DCT coefficients obtained by DCT-transforming 8 × 8 pixels adjacent to each other in luminance or color difference. 6
The four DCT coefficients are subjected to zigzag scanning in the order shown in FIG. 10, and two-dimensional Huffman coding is performed using a run length of zero coefficient and an amplitude of nonzero coefficient as a pair to form a bit stream. At the end point of the code of one block of DCT,
A Huffman code of EOB is added. 15. Super block layer bit stream structure A super block is composed of 8 adjacent luminance blocks in the horizontal direction 4 and 2 in the vertical direction, and a total of 10 color difference blocks of U and V that are at the same position on the image. It The reverse order is Y ₀ , Y ₁ , Y ₂ , Y
₃ , Y ₄ , Y ₅ , Y ₆ , Y ₇ , U, and V. As the DC component of the luminance signal, a value obtained by calculating the difference between adjacent blocks is sent. 16. Macro (non-) refresh block address As described in Chapter 9, Section 9.1, in order to realize high-speed VCR reproduction, refresh block rearrangement is necessary. This will be described in detail below.

First, the relationship between the position of the macro block and the (non-) refresh block on the screen and the address is defined. 34 and 35 show examples of address setting methods.

As shown in FIG. 33, the macroblock is 1
It consists of one super block, and consists of one refresh block and ten non-refresh blocks. The address of the super block on one screen is set as shown in FIG. 16.1 Macroblock Address As shown in FIG. 34, the macroblock address is assigned the same address value as the address value of the first superblock of the macroblock. 16.2 Refresh block address When set as in section 16.1, since the head of the macro block is the refresh block as shown in FIG. 33, as shown in FIG. The block address values match. 16.3 Non-refresh block address As the address of the non-refresh block, the address value immediately before the non-refresh block in the horizontal direction is used.

That is, macroblocks and (non-)
The same address value is used for the refresh block address. 16.4 Address Value As shown in FIG. 3, this address value is S.S. when the horizontal super block position is x and the vertical super block position is y. B. It is represented by Address = 60x + y.

Here, since DigiCipher uses four processors in the horizontal direction, I indicates this processor.
If D is PID and ID indicating the vertical position is VID, the address value is MBA (Macro Block Address) = (60/11) • PID +60
・ X ₀ ＋ VID RBA (Refresh Block Address) ＝ （60 ・ 11） ・ PID ＋
60 x ₀ + VID NRBA (Non Refresh Block Address) = (60/11)
It is expressed as PID + 60 · x ₀ + VID.

Here, x ₀ is the horizontal position of the macro (non-) refresh block when PID = 0 and VID = 0.

34 and 35 show the case of x ₀ = 0, naturally x ₀ = _{0 to} 43 are used. Further, this x ₀ corresponds to the frame count in the conventional example. 17. Macro (non-) refresh block bitstream structure 17.1 Macroblock bitstream structure FIG. 36 shows a macroblock bitstream structure.
In the bit stream structure shown in FIG. 36, a VCR recording format converter requires a variable length code decoding circuit for a refresh block. In addition, it is necessary to detect all overhead data.

The bit stream of the broadcast wave may be constructed by incorporating only the necessary items for the broadcast wave. In this case, V
The CR format converter only needs to have the circuits necessary for creating the bit stream (FIG. 37, FIG. 38, FIG. 40 to FIG. 43) required for the VCR, and the overhead data detection circuit 81 and the variable length code. Decoding circuit 8
All you need is four.

Regarding the bit stream shown in FIG. 36, items that have been conventionally used will be described first. This content is based on the following two documents, and each exhibiting document number is shown. (a) “DigiCipher Description” Aug. 22 1991 (b) “Channel compatible DigiCipher HDTV System”
April 3.1992 Details about each item in the bitstream.

In FIG. 36, the bitstream structure in the macroblock is composed of overhead data and variable length code.

Processor ID: Since DigiCipher uses four processors, the number of this processor is indicated by 2 bits (b).

Macroblock Quantization Level (MQL):
The quantization level QL is represented by 5 bits, and the larger the value, the coarser the quantization, the macroblock quantization level MQ.
L = 31 indicates a state in which no code is generated.
When QML = 31, as shown in FIG. 36, the overhead data and the variable length code are skipped after the QML, and the process proceeds to the next macroblock.

2-bit correction quantization level: The correction quantization level is set in the direction of coarser quantization than the macroblock quantization level MQL (a). Also, the correction quantization level is 2 bits per superblock.
(b). It is also set for 11 super blocks (a). This corresponds to the corrected quantization level described in Chapter 10, Section 10.2 and Section 10.3.

Corrected quantization level path PQL: When the quantization levels of all super blocks are the same as the macro block quantization level, the 2-bit correction quantization levels are all 0, and in this case, 2-bit correction is performed. No quantization level is set. That is, when PQL = 1, the route to the 2-bit correction quantization level is not passed, and when PQL = 0, the route indicating the 2-bit correction quantization level is passed (b).

Field / frame discrimination: DCT 8 ×
The pixel configuration of 8 pixels specifies whether to use field pixels or frame pixels, and is set for each super block unit (a).

PCM / DPCM discrimination: Superblock is intraframe processing (PCM) or interframe processing (DPC)
M) distinction (a).

Motion vector: Indicates the motion vector of each super block (a).

Next, a new bit stream structure will be described.

Path ID (PSID): When PSID = 0, the path through which the macroblock quantization level exists is taken. When PSID = 1, the processor ID (P
The route shown below is specified by (ID).

When PID = 0, the route in which the high speed reproduction mode (TRK) exists exists.

When PID = 1, the route through which the block ID and the block address exist is taken.

When PID = 2, the path is the path in which the Fill Bits code length and Fill Bits code exist.

Trick quantization level TQL: Only the refresh block can be used during high speed reproduction of the VCR. Moreover, there may be a plurality of refresh blocks in one macroblock. If there are multiple refresh blocks, the next 2
You need points.

First, when there are a plurality of refresh blocks of different frames in one macroblock, 5 refresh blocks are provided for each refresh block.
A bit quantization level is required.

Secondly, the position of the refresh block within the macroblock must be specified.

In order to specify this position, skipping in super block units is required. Therefore, at the time of high-speed playback of the VCR, the trick quantization level TQL is set to pass.

The trick quantization level TQL has a 5-bit absolute quantization level for each super block. Therefore, 11 super blocks contain 55-bit quantization levels.

Also, by setting TQL = 31, it becomes possible to skip variable length codes in units of superblocks.

This makes it possible to arrange the variable length code of the refresh block at an arbitrary position in the macro block.

As shown in FIG. 36, there is a correspondence between this trick quantization level TQL and the variable length code of each super block. TQL ₀ is a super block 0 TQL ₁ is a super block 1: TQL ₁₀ is a super block 10. 3 shows the respective trick quantization levels TQL of

[0250] During high speed reproduction, super blocks 0 to 1
Of 0, the variable length code of the refresh block is arranged only in the super block position where the refresh block is arranged, and in the other super block parts, the trick block quantization level TQL = 31 is set, and the skip of the super block unit is performed. To do.

[0251] The variable length code of the bit stream for recording, normal reproduction, and broadcast wave is the super block 0.
Refresh block 0, super blocks 1-1
0 corresponds to the non-refresh blocks 1 to 10.

High-speed playback mode (TRK): When sending a bit stream of broadcast waves or sending a bit stream during normal playback, set TRK = 0 and set the 2-bit correction quantization level (PQL = 0) or The path of 2-bit correction quantization level unused (PQL = 1) is taken.

In the high speed playback mode of the VCR, TR
K = 1 is set and the path indicating the trick quantization level described above is taken.

Block ID: ID indicating the distinction of macroblock (non-) refresh block.

Block address: Indicates the address which is the absolute position on the screen of the macro (non-) refresh block.

This block address sends the projection position information to the decoder so that the video can be restored instantly even when an error occurs during VCR reproduction or high speed reproduction. This address can be reconstructed by using the (non-) refresh block address in the data multiplex format described in Chapter 23.

When PSID = 1 and PID = 2, the path of Fill bits code length and Fill bits code is passed. Here, the Fill bits will be described. Since the amount of code to be transmitted is constant, when the amount of band-compressed code is smaller than the amount of transmission code, a predetermined code is forcibly inserted up to the amount of transmission code. This code is called a Fill bits code, and this code length is called a Fill bits code length.

Fill Bits code: A predetermined code is forcibly inserted when the generated code amount of the variable length code is small. The code that is forcibly inserted is called Fill Bits. Especially VCR
During high-speed reproduction, only the refresh block is used and the non-refresh block is not used, so that the generated code amount is likely to decrease. Since the transmission code amount is constant, it is necessary to forcibly insert Fill Bits.

Fill Bits Code Amount: By inserting the code length of Fill Bits described above before Fill Bits, Fill Bis
Clarify the ending point of the sign of ts. This makes it possible to clarify the boundary with the macroblock.

Macroblock code length: The sum of the code lengths of the macroblock overhead data and the macroblock variable length code in the macroblock of FIG.

By using the above bit stream as the bit stream of the broadcast wave, it becomes possible for the decoder that receives the broadcast wave to receive the signal on which the special reproduction of the VCR is performed.

By using the above-mentioned bit stream, the VCR format converter can realize special reproduction by a simple process of detecting the overhead data of the macro block and the variable length code of the refresh block and exchanging the code of the refresh block. .

Vertical ID (VID _M ): Not present in the bitstream, but VID _M is defined as follows:
ID indicating the vertical position within one screen, 6 in the vertical direction
Since there are 0 macroblocks, VID _M = 0 to
It becomes 59. 17.2 Refresh block bitstream structure (Fig. 37) Refresh block bitstream structure (Fig. 37)
In the header, overhead data and one refresh block variable length code 0 are entered.

The overhead data is basically the same as in Section 17.1, but the characteristic points will be described below.

Block ID: The block ID has the ID of the refresh block. The block address indicates a refresh block address.

Refresh block code length: Shows the total code length of the variable length code of the overhead data and refresh block.

Overhead data length: Data length of overhead data from the corrected quantization level path PQL to the motion vector.

The variable length codes are as follows.

Refresh block variable length code (refresh block 0) Variable length code of the block to be refreshed out of 11 super blocks in the macroblock. This corresponds to super block 0 in FIG. 17.3 Non-refresh block bitstream structure (FIG. 38) Non-refresh block bitstream structure (FIG. 3)
In 8), overhead data and 10 non-refresh block variable length codes 1 to 10 are entered.

The non-refresh block overhead data is the same as in Section 17.1, but the differences and characteristic points will be described below.

Block ID: The block ID has the ID of the non-refresh block, and the block address shows the non-refresh block address.

Non-refresh block code length: The data length of overhead data and the total code length of the code lengths of 10 non-refresh blocks.

2-bit correction quantization level: Same as the 2-bit correction quantization level in section 17.1.

Overhead data length: The data length of the overhead data from the corrected quantization level path PQL to the motion vector.

The variable length code is as follows.

Non-refresh block variable length code: Includes the variable length codes of non-refresh block 1 to non-refresh block 10. Of the 11 super blocks in the macro block, the variable length codes of 10 non-refreshed super blocks are included. This corresponds to super block 1 to super block 10 in FIG. 18 slice layer, picture layer, G. O. P layer 18.1 Slice layer The slice layer is composed of one or more macro (non-) refresh blocks.

At the head of the slice, there is an address value indicating the position in the image and the distinction between macro slice, refresh slice and non-refresh slice, and it is considered that the data can be utilized even at the time of high speed reproduction or error occurrence. .

The discrimination and address value of this slice are
In the macro and (non-) refresh block bitstream structures shown in FIGS. 36 to 38, the PSID and PID can be set by setting a predetermined value to pass the block ID and the address value. 18.2 Picture Layer A picture, or a picture, consists of at least one or more slices. 18.3 G.I. O. P layer (group of picture layer) The GOP is composed of a plurality of picture layers. DigiCipher
In this case, since there are 44 super blocks in the horizontal direction and the position of the macro block in the horizontal direction is determined by the frame count value (FC), 44 pictures are 1G.
O. Enter the P layer. 19. Macro slice layer, picture layer, G. O. The P layer and the macro slice layer indicate the transmission order of macro blocks when transmitting the signal of the DigiCipher broadcast wave.
(FIG. 39) This macro slice layer is the same as the macro picture layer because processing is performed on one screen. Then, one macroblock address is inserted in one screen. This macroblock address is obtained by passing through the path indicating the macroblock address when the path ID and the processor ID are set to predetermined values in FIG. Since this is set for each frame, it is associated with the frame count value F · C _{M of} the macroblock at a ratio of 1: 1.

The order of sending macro blocks in the macro slice layer is VID _M = 0 to 59 sequentially from the top to the bottom of the screen in units of the processors PID _M = 0 to 3.

That is, to explain using the example of the macroblock address of FIG. 34, after the macroblock address value is first transmitted, the macroblock is transmitted at the following macroblock address. That is, 0, 660, 1320, 19801, 661, 1321, 1981 :::: are transmitted.

In the next frame, the horizontal position x ₀ of the macroblock is shifted by 1, the macroblock address value is transmitted, and then the macroblock is transmitted at the following macroblock address. That is, 60, 720, 1380, 2040 61, 721, 1381, 2041 :::: are sequentially transmitted in this order.

After sequentially shifting the horizontal position x ₀ from ₀ to 43, it returns to x ₀ = 0 again. These 44 images are macro G.I. O. P layer. This is one of the processor has become a period of handling the entire area of one screen, and Zui correspondence with frame count _{F · C M, x 0 =} f (F ·
C _M ).

Since one screen is composed of four processors, refreshing is performed every 11 frames.

During normal reproduction of a recording medium such as a VCR, the macro slice layer, picture layer, G. O.
Output from the recording medium using the P layer bitstream structure. 20. Refresh slice layer, picture layer, G. O.
P layer As described in Section 9.1 Refresh block code replacement in Chapter 9 High-speed playback requirements, in order to realize high-speed playback of a VCR, a predetermined number of refresh blocks are used.
Must be recorded so as to be arranged in the sector on the tape pattern of.

The refresh slice layer shows the structure of this predetermined number of refresh blocks. That is,
The position of the refresh block on the screen, the number of refresh blocks put in the refresh slice, and their arrangement are shown.

With the configuration of this refresh slice,
The specifications for high-speed playback are determined. 40 and 41 show examples of the refresh slice layer.

The refresh picture layer shows a refresh block for one screen. Refresh G. O. The P layer is composed of a 44-frame refresh picture layer. Refreshing one screen is completed every 11 frames, and each processor scans the entire area of one screen every 44 frames.
G.G.R. has 44 frames of _R = 0 to 43 as a cycle. O. A P layer is formed.

The number of refresh blocks in one sector on the tape 26, that is, one refresh slice layer is 1
The average code amount per frame is determined by the number of tracks for recording, the number of drum rotations, the number of heads per scan, and the high speed reproduction speed.

The simplest case will be described below.

In the tape format shown in FIGS. 18 and 23, that is, when one frame is recorded in one track and high-speed reproduction at double speed is realized, one refresh picture layer has two refresh slice layers. Since the number of refresh blocks in one frame is 240,
Since 120 (= 240/2) refresh blocks are inserted in one sector, 1 is set in the refresh slice layer.
Insert 20 refresh blocks. The method of inserting this refresh block is described in Section 20.1 and 20.
There are two types of methods described in Section 2.

If the number of tracks per frame, the number of rotations of the drum, and the high-speed reproduction speed are determined as other specifications, it is 1
A predetermined number of refresh slices may be set in the refresh picture layer.

When the VCR system is determined, the number of refresh blocks in the refresh slice is also uniquely determined. Also, the number of refresh slices in the refresh picture layer is uniquely determined. 20.1 Refresh slice layer structure No1 FIG. 40 shows a first method of arraying refresh blocks in the refresh slice layer.

First, the refresh block address of the refresh block at the beginning of the refresh slice is placed at the beginning of the refresh slice layer.

Since refresh slice 0 is the first refresh slice in the refresh picture layer, this refresh block address matches the macroblock address in the macro slice layer described in Chapter 19.

Subsequently, refresh blocks are arranged.

The arrangement of refresh blocks in the refresh slice is processor PID _R = 0, 1, 2, 3
Are transmitted sequentially, the vertical ID VID _R = 0 to 29 is transmitted. This means that four refresh blocks in the horizontal direction are sequentially transmitted on the screen while being transmitted in the vertical direction from top to bottom.

As a result, 120 refresh blocks on the upper side of the screen are transmitted. Subsequent to the refresh block sent in refresh slice 0, in refresh slice 1, PID _R = 0 to 3 and VID _R = 31 to 59.
Up to.

At the beginning of the refresh slice 1, PI is added.
A refresh block address determined by D _R = 0, VID _R = 30, and F · C _R is inserted.

The decoder can know the initial position by using the refresh block address. Also, PID _R
= 0, 1, 2, 3 is used to know the horizontal position and PID
By counting _R , the vertical position can be known.

Although FIG. 40 shows that there is a refresh slice break at the switching of VID _R , the refresh slice break may be set at the switching of PID _R. 20.2 Refresh slice layer structure No. FIG. 41 shows a second technique for arranging two refresh blocks. This method is a method of sequentially transmitting vertically adjacent refresh blocks per processor.

In this case, PID _R is fixed and VID _R
= 0 to 59, then change PID _R ,
Further, VID _R = 0 to 59 are transmitted in this order.

The second method can send adjacent refresh blocks of the same frame, and is therefore advantageous in terms of image quality when the high speed reproduction speed is high. This is because the adjacent areas of the same frame can be reproduced large during high-speed reproduction.

The decoder can know the vertical position by knowing the initial position using the refresh block address and counting the fixed period PID _R. Furthermore, when the PID _R value is changed, PI
The amount of deviation in the horizontal direction can be known using the value of D _R = 0 to 3. 21. Non-refresh slice layer, picture layer, G.
O. P Layer 21.1 Structure in Non-Refresh Slice Layer The non-refresh slice layer shows the transmission order and the transmission delimiter when transmitting the non-refresh block shown in FIG.

[0304] transmission order of the non-refresh block is always the same as the transmission order of macro-blocks, PID _NR
Repeats 0, 1, 2, 3 in sequence. VID _NR is 0
~ 59 are sequentially transmitted.

That is, in the example of FIG. 42, the non-refresh block addresses 0, 660, 1320, 1980,
1, 661, 1321, 1981, and so on, and in the next frame, the horizontal position x ₀ is shifted by one super block, 60, 720, 1380, 2040,
61, 721, 1381, 2041, ...

By making the sending order of the macroblocks and the sending order of the non-refresh blocks the same, the signal processing during normal reproduction is simplified. In order to satisfy this condition, the refresh slice layers are sequentially sent out as refresh slices 0 to 2. 21.2 Separation of Non-Refresh Slice Layer Next, separation of the non-refresh slice layer will be described.

[0307] One or a plurality of non-refresh slices are included in a non-refresh picture containing one screen of non-refresh blocks. There are two types of delimiters for this non-refresh slice.

First, at the frame switching point, that is, at the non-refresh picture layer delimiter, the non-refresh slice delimiter is inserted.

The second method is to insert a non-refresh slice delimiter in order to realize high-speed VCR reproduction.

Chapter 9 Requirements for High Speed Reproduction As described in Section 9.1 Refresh block code exchange, in order to realize high speed reproduction of the VCR, the refresh slice is set to VC.
It must be located in a sector on the R tape pattern.

In order to realize this arrangement, it is necessary to insert the delimiter of the non-refresh slice layer so that the refresh slice falls within the sector.

The number of refresh blocks in the refresh slice layer is arbitrarily changed depending on the code amount assigned to the non-refresh slice layer.

Further, a non-refresh block address is put in the head portion of the non-refresh slice layer. 22. VCR picture layer G. O. When recording in the P layer VCR, the above-mentioned refresh slice and non-refresh slice are combined and transmitted.

FIG. 43 shows this combination method, in which the code indicated by the solid line is transmitted.

The non-refresh slices are transmitted in the order of non-refresh slices 0, 1 and 2, as described in Chapter 21.

Also during this non-refresh slice,
Insert a refresh slice. That is, assuming that the non-refresh slice is NRS (Non Refresh Slice) and the refresh slice is RS (Refresh Slice), NRS0, RS0, NRS1, RS1, NRS2 are transmitted in this order.

Here, the non-refresh slices are always transmitted in the order of 0, 1, 2, but the refresh slices may be transmitted in the order of NRS0, RS1, NRS1, RS0, NRS2. good.

The order of sending refresh slices is VC
It is determined by the design method of the playback image of R high-speed playback.

The portion indicated by the dotted line in FIG. 43 is VC
The picture layer of each of the refresh slice and the non-refresh slice when the recording code is sent to the R.
O. The relationship of the P layer is shown.

The refresh slices are arranged in consideration of recording in the sector of the VCR, and the non-refresh slices are arranged between the refresh slices, but the transitions of the respective picture layers can be set independently.
The transmission order of each picture layer is F · C _R = 0.
˜43, F · C _NR = 0 to 43 are transmitted in this order. 23. Data multiplex format When the bit stream described in Chapters 13 to 22 is recorded by the A head and the B head through the output terminal 69 of FIG. 1, a signal necessary for VCR is added and recorded.

FIG. 44 shows this VCR data multiplex format.

The figure shows the transmission data of the track 0. The horizontal axis corresponds to the period of one unit described later,
The vertical axis corresponds to the number of units recorded on one track. Here, since the case where the average code amount of one frame is recorded on one track is described, the vertical axis side also corresponds to the average code amount of one frame.

At the right end, examples of the switching points of the video signal and the audio signal and the switching points of the sector are shown.

In the non-refresh block bitstream structure of FIG. 42, VID _NR = v ₁ and VID _NR =
the method of determining the v ₂ is, in the sector S ₀ of the refresh slice 0 is the track T _0, as refresh slice 1 is placed in a sector S ₁ of the track _{T 0 VID NR = v 1,} v
Decide on ₂ .

As described above, after arranging the non-trick block and the code of the trick block, as shown in FIG. 44, the sync signal, the (non-) non-refresh block position, the non-refresh block address, other additional information and error correction. Record by adding a code. 23.1 Unit Sync Since a VCR has jitter due to uneven rotation of the cylinder, track jump during special reproduction, etc., it is necessary to add a unit sync signal at a predetermined cycle. Here, one period of this sync signal is named one unit.

Definition of Terms Unit: A period of sync in the data transmitted to the VCR. During this period, sync, additional information, non-refresh block position code, (N-) R. B. P, non-refresh block address code (N-) R.P. B. P,
And (non-) refresh slice code, error correction code, etc. are included.

[0327] Also, the VCR set in this unit period
We will name the sync signal for use as a unit sync.

Definition of words Unit sync: A VCR sync is set for each unit, and additional information for VCR is recorded after the unit sync.

As additional information, a unit sync number,
Video and audio identification, track number, unit number, etc.

Further, error correction parity is added for VCR error correction. 23.2 (Non-) refresh block ID The (non-) refresh block ID is 23.3 to 2
When the block indicating the (non-) refresh block frame address position described in section 3.5 is a non-refresh block, (N-) R. B. When ID = 0 and refresh block, (N-) R. B. Indicates ID = 1. 23.3 (Non-) refresh block frame The (non-) refresh block frame indicates the frame number of the block indicated by the (non-) refresh block position. 23.4 (Non-) refresh block address (N
-) R. B. A (non-) refresh block address (N-) R.
B. A represents the projection position information of each block.

Since each block is composed of a variable length code, the block switching point is not fixed.
Therefore, the address (N-) R. B. A is shown.

23.5 (Non-) Refresh Block Position (N-) R. B. Since the P variable length code and the inter-frame DPCM processing are used, the starting point of the block is not fixed either. Therefore, this starting point is indicated by the (non-) refresh block position.

When arranging the refresh slices between the non-refresh slices, the refresh block position code is inserted so as to indicate the position of the head block of the refresh block.

There may be a plurality of refresh blocks and non-refresh blocks in the unit. In this case, the position indicated by the refresh block position is
The position of the first (non) refresh block that appears is shown.

Therefore, the head block of the refresh slice is arranged so as to appear first in the unit.

If the recordable code amount is larger than the transmission data code amount, a free area may be set and the head block of the refresh slice may be arranged from the head position in the unit. At the time of high-speed reproduction, the head traces while crossing the track, so that the envelope becomes maximum when the head completely coincides with the track, and otherwise the envelope becomes inevitably small. This indicates that the error rate increases, which means that reproduction may become impossible.

On the other hand, in order to utilize the refresh slice as a reproduction signal, first, the start position of the leading code of the refresh slice must be known.
-) R. B. The P signal must be reproduced.
This (N-) R. B. In order to detect the P signal, the unit sync signal must be detected.

Therefore, by arranging the refresh block from the head position in the unit, it is possible to minimize the effect of reducing the envelope.

Furthermore, when a free area is set and the head block of the (non-) refresh slice is arranged at the head position in the unit, in the code re-swapping in the decoder, only the (non-) refresh block ID is used for refreshing. Since blocks and non-refresh blocks can be allocated to different FIFO memories, there is an advantage that code re-swapping can be easily configured. 23.6 Specific Example FIG. 45 shows a specific example of the (non-) refresh block ID, frame, address, and position index signals.

FIG. 45 (a) is an enlarged view of a unit relating to the image of FIG. In the figure, the (non-) refresh block ID [(N-) R. B.
ID] (non-) refresh block frame [(N-) R.
B. Frame] (Non-) refresh block address [(N-) R.
B. Address] (Non-) Refresh block position [(N-)
R. B. Position]] of the index signal.

Also, the position where the variable length code is inserted is shown,
In order to show the switching position of the block in the unit,
The positions of the code amount are shown above from 0 to 150.

FIG. 45B shows the refresh block R.3 of frame number F ₆ . It shows the value of the index signal to be inserted when B ₀ is the first block in the unit.

R. B. ID = 1 R.I. B. F = 6 R.I. B. A = 0 R. B. P = 50.

FIG. 45C shows the non-refresh block N.N. of frame number F ₁₀ . R. The value of the index signal to be inserted when B ₇₁₀ becomes the first block in the unit is shown.

R. B. ID = 0 R.I. B. F = 10 R.I. B. A = 710 R.A. B. P = 50.

The VCR data multiplex format only attaches additional information such as an index,
There is no requirement for video source coding from this format.

Therefore, the contents of the video information are not deteriorated by this format. 23.7 Additional information As the additional information in FIG. 44, a unit number, a track number, etc. are entered. By inserting these pieces of information, slow reproduction can be realized by rearranging the units according to the unit number during slow reproduction.

Further, this unit number is used to reproduce a specific position of a track during high speed reproduction. That is, servo is applied so that the envelope at the position where the refresh slice is arranged becomes maximum. 24. Code Exchange Circuit FIG. 46 shows the configuration of the code exchange circuit 45 during recording.
Will be described in detail.

A case where a bit stream to be transmitted by a broadcast wave is input to the output terminal 68 will be described. If the processing when the bit stream of the broadcast wave is input becomes possible,
Necessary items for recording only on VCR are included. Therefore, this case will be described.

First, since the bit stream input to the output terminal 68 has the macro block format shown in FIG. 36, this macro block is separated into a refresh block and a non-refresh block. The separated (non-) refresh block is stored in the (non-) refresh block memories 45a and 45b.

In order to perform this separation, the (non-) refresh block memory write control circuit 45c generates a necessary timing signal.

In order to generate this timing signal,
The NMP detection circuit 45d first grasps the start position of the frame, and the overhead data detection circuit 45e detects the path ID.
(PSID), processor ID (PID), macroblock quantization level Q _M , macroblock code length, and other overhead data are detected.

Using these overhead data,
The (non-) refresh block memory write control circuit 45c controls the (non-) refresh block memory 45.
Write timing signals required for a and 45b to the terminal 45
Generate from f, 45g.

The write timing will be described with reference to FIG.

47 (a) and 47 (b) show a bit stream when it is transmitted as a broadcast wave. FIG. 47
(A) is overhead data, and PSID indicates a path in the bitstream. Also, VID, P
The ID is the ID shown in FIG. The VID is not included in the bitstream. Further, when the macroblock quantization level MQL is set to MQL = 31, the skip operation is performed.

In FIG. 47 (b), □ in black indicates a macro (non-) refresh block address, and □ indicates macro block overhead data. Also, L
_R is the refresh block code length, and L _NR is the non-refresh block code length.

Only the bitstreams shown in FIGS. 47C and 47D are extracted from the macroblock bitstream shown in FIG. 47B and stored in the (non) refresh block memories 45a and 45b, respectively.

FIG. 47C shows a signal to be written in the refresh block memory 45a. That is, the macro block address, macro block overhead data, refresh block overhead data, and variable length code are written.

Since the address is inserted at the head of the slice layer, as shown in the refresh slice 1, the refresh block address is inserted at the head of the refresh slice layer. This operation is shown in FIG.
(Non-) refresh block address generation circuit 70
The address is generated at a and output from the terminal 45h.
6 is inserted by the address insertion circuit 45i.

FIG. 47 (d) shows a signal to be written in the (non-) refresh block memory 45b. That is,
Write macroblock address, macroblock overhead data, (non-) refresh block overhead data and variable length code.

Further, as shown in (non-) refresh slice 1, a (non-) refresh block address is inserted at the head of the non-refresh slice. To insert this (non-) refresh block address, the (non-) refresh block address generation circuit 70a and the address insertion circuit 45i shown in FIG. 48 are used.

Next, the memory read (non-) refresh slice combination control circuit 70 will be described.

First, the points in combining the (non-) refresh slices will be described. FIG. 49 shows an envelope at the time of high speed reproduction of the VCR.

FIG. 49 (a) is a diagram showing a part of the tape and track shown in FIG. 23 and the head trace at double speed. The envelope corresponding to this is shown in FIG.
It shows in (b).

In FIG. 49 (b), the portion shown by the solid line shows the envelope shape that can be reproduced by the head, and the portion with a large envelope has a small error rate.

Therefore, the point when arranging the refresh slices between the non-refresh slices is to arrange the refresh slices around the point where the envelope becomes maximum.

Therefore, at the time of recording, processing for arranging refresh slices is performed with a predetermined position on the track as the center. During high speed playback, servo is applied so that the head traces the center value of the refresh slice.

In the memory read (non-) refresh slice combination control circuit 70, first, the refresh slice code amount calculation circuit 70b calculates the refresh slice code amount using the refresh block length L _R input from the terminal 45j.

The refresh slice arrangement position designation ROM 70c stores the recording code amount of one sector and the position where the head traces each track during high speed reproduction.

The (non-) refresh slice / refresh slice connection point determination circuit 70d determines the switching point between the refresh slice and the non-refresh slice using the refresh slice code amount and the refresh slice arrangement position. To make this determination, the non-refresh block code amount calculation circuit 70e calculates the sum of the code amounts of the non-refresh blocks. Using this, the (non-) refresh slice connecting points v ₁ and v ₂ shown in FIG. 42 are determined so that the center point of the refresh slice is located at a predetermined position on the track.

Using this (non-) refresh slice connection point, the (non-) refresh block memory read control circuits 70f and 70g read the respective codes from the (non-) refresh block memories 45a and 45b.

In accordance with this, the switch 45j is switched.

The (non-) refresh block address generation circuit 70a described above generates a (non-) refresh block address using the (non-) refresh slice connection point. Further, this address is inserted into the bit stream by the address inserting circuit 45i. 25. Decoder Basic Configuration The basic configuration of the decoder will be described in detail with reference to FIG.

First, a VCR mode signal such as normal reproduction / high speed reproduction from the user is input to the reproduction speed setting circuit 72 through the terminal 71.

The tape feed control circuit 73 and the track reproduction control circuit 74 control the VCR servo to control the drum rotation phase and the tape feed speed phase. Especially during high-speed reproduction, servo is applied so as to read out the area where the refresh slice is recorded.

As a result, the signal recorded on the tape 26 is read by using the A head and the B head. The read signal is input to the error correction circuit 76 and the unit sync detection circuit 77 after being subjected to reproduction waveform equalization and the like through a switch 75 that switches between the A head and the B head.

The unit sync detection circuit 77 detects the sync signal inserted in each unit. This eliminates the influence of VTR jitter and the like. Each unit is grasped by detecting this sync signal, and the index detection circuit 78 detects the index signal shown in FIG. In the figure, the upper part of the bold line is the index signal. The start point of the (non-) refresh block is grasped by the (non-) refresh block position signal detected by the index detection circuit 78. Also,
The (non-) refresh block ID is used to distinguish between non-refresh or refresh of the (non-) refresh block starting at this starting point.

Further, by detecting the (non-) refresh block frame and the address, the projection position of the (non-) refresh block and the order of the projected frames can be known.

Next, the code length detection circuit 79 inputs the (non-) refresh block position [(N-) R. B. P] is used to detect the start position of the (non-) refresh block, and the (non-) refresh block code length included in the overhead data of the (non-) refresh block is detected.

By using this (non-) refresh block code length, it is possible to clarify the boundaries of the (non-) refresh block, detect the sequential overhead data, and grasp the position of the variable length code.

Note that in FIG. 50, the code length detection circuit 79
Although the overhead data detection circuit 81 is shown as a separate configuration, the code length detection circuit 79 is included in the overhead data detection circuit 81.

FIG. 51 shows the relationship between the index used in each circuit and the overhead data. In each circuit, signal processing is performed using the index marked with a circle and the overhead data.

The code shuffling circuit 82 separates the (non-) refresh slice and the refresh slice from the VCR picture layer bit stream shown in FIGS. 40 to 43 using the (non-) refresh block ID.

The separated (non-) refresh slices are stored in the refresh memory and the non-refresh memory in the code re-swapping circuit 82, respectively.

At the time of normal reproduction, the refresh memory and the non-refresh memory having the same (non-) refresh block address in the code re-interchanging circuit 82 are switched while reading, the non-refresh block and the refresh block are combined, and the macro block The code re-arrangement circuit 82 is configured to output through the terminal 83.

The normal reproduction bit stream of the VCR and the broadcast wave bit stream have the same macroblock structure, and when the broadcast wave bit stream is input, they are input from the terminal 83.

In the case of a broadcast wave bit stream, the overhead data detecting circuit 81 is used to detect and decode the overhead data. Since the operation during normal reproduction is the same as the operation for decoding the broadcast wave, this operation will be described first.

First, the variable length code of the (non-) refresh block of the bit stream of the macro block shown in FIG. 36 at the terminal 83 is input to the variable length code decoding circuit 84. When this variable length code is extracted, the variable length code is extracted from the bit stream by decoding the (non-) refresh block code length in the overhead data and the overhead data. The variable length code decoding circuit 84 sequentially detects the Huffman code by comparing the code with the Huffman table from the head position of the variable length code. Using the detected Huffman code, the number of consecutive zero coefficients (run length) and non-zero coefficient (amplitude) of the quantized DCT coefficient are obtained. Since these coefficients are arranged in the order in which zigzag scanning was performed,
The order of the coefficients is rearranged as required by the inverse DCT circuit 85.

The signal obtained by decoding the variable length code is input to the inverse quantization circuit 86. In the inverse quantization circuit 86, the macroblock quantization level is corrected by the (non-) refresh block correction quantization level, and the quantization level is obtained in units of super blocks.

Next, each of the 64 coefficients per block is first multiplied by a weighting value according to the weighting table.

Next, by multiplying each of the 64 coefficients by a quantization scale value according to the quantization level of the super block unit, inverse quantization is performed and DCT coefficients are obtained. (Here, the case of the second quantization method described in Chapter 8 has been described.) These 64 DCT coefficients are passed through the inverse DCT circuit 85, and the coefficients in the frequency domain are transformed into the time domain. Then, a signal of 64 pixels of 8 pixels in the horizontal direction and 8 pixels in the vertical direction is obtained.

The output of the inverse DCT circuit 85 is added to the adder 87.
To enter.

Further, the signal of the switch 88 is input to the adder 87 and is added to the output signal of the inverse DCT circuit 85. The switch 88 is controlled by an intra-frame / inter-frame switching circuit 89. The output signal of the adder 87 is input to the deblocking circuit 90 and the frame delay circuit 91.

The frame delay circuit 91 is composed of a frame memory, and the output signal of this frame memory is input to the motion compensation circuit 92 and the deblocking circuit 90.

The output signal of the motion compensation circuit 92 is input to the switch 88.

The deblocking circuit 90 uses the signals of the adder 87 and the frame delay circuit 91 to perform band compression signal processing and processing for matching the display order of the scanning lines of the TV to obtain the luminance signal and the color difference signals U, V is output from the output terminals 93 to 95.

The operation of the decoder includes intraframe processing and interframe processing. In switch 88, switch 8
When the switch 8 is off, the intraframe process is performed, and when the switch 88 is on, the interframe process is performed. The intra-frame / inter-frame switching circuit 89 controls ON / OFF of the switch 88.

PCM / DPC in overhead data
The M discrimination signal is input to the intra-frame / inter-frame switching circuit 89 through the terminal 96. Here, PCM is in the frame, D
PCM indicates inter-frame processing. The switch 88 is turned off by PCM and the switch 88 is turned on by DPCM. As described in Chapter 3, intraframe / interframe processing includes image adaptive intraframe processing and refresh (forced intraframe processing).

First, the operation of the intraframe processing will be described.

During the intra-frame processing, the output signal of the inverse DCT circuit 85 is input to the frame delay circuit 91 and the deblocking circuit 90, and the luminance signal Y and the color difference signals U and V are output.

Next, the operation of the interframe processing will be described.

In this case, the prediction signal of one frame before stored in the frame delay circuit 91 is read out and input to the motion compensation circuit 92.

Also, the motion vector of the overhead data is input to the motion compensation circuit 92 from the terminal 96, and the position of the prediction signal on the screen is shifted. The prediction signal corresponding to the position on the screen of the output signal of the inverse DCT circuit 85 is
It is output from the motion compensation circuit 92, passed through the switch 88, and input to the adder 87. In the adder 87, the inverse DCT circuit 8
The output of 5 and the prediction signal are added and input to the frame delay circuit 91 and the deblocking circuit 90. Then, the luminance signal Y and the color difference signals U and V are separated and output from the terminals 93 to 95.

The write processing to the variable length code decoding circuit 84, the inverse quantization circuit 86, the inverse DCT circuit 85, and the frame delay circuit 91 in the normal reproduction of the broadcast wave and the recording medium described above is always performed on the basis of the macro block. I will do it.

That is, the processing of these circuits per processor is based on the sequential processing of 11 super blocks in the macro block, and the macro blocks are sequentially processed on the screen from top to bottom. 26. High Speed Reproduction Next, the operation during high speed reproduction will be described in detail.

First, the code re-interchanging circuit 82 reads only the refresh memory in which the refresh slice is stored from the bit stream.

Since this refresh slice contains a refresh block address, a frame ID and a processor ID, the overhead data detecting circuit 81 can detect this overhead data to grasp the projected position. Further, the projected position can be grasped by detecting the refresh block address in the index signal of FIG. 44 described in Chapter 25.

This makes it possible to determine the write memory address corresponding to the video position when writing to the frame memory in the frame delay circuit 91.

At the time of high speed reproduction, only the refresh block is valid as the projection data, and the non-refresh block data is not valid. Therefore, only the refresh block is changed to the variable length code decoding circuit 84 and the inverse quantization circuit 8
6, write processing to the inverse DCT circuit 85 and the frame delay circuit 91 is performed.

Since the refresh block is always the intra-frame processing, the intra-frame / inter-frame switching circuit 89 specifies the intra-frame processing. That is, the switch 88 is always off.

There is only one refresh block in the macro block. Therefore, within one screen, there is only a method of sending refresh blocks every 11 super blocks in the horizontal direction or continuously sending refresh blocks in the vertical direction. This is different from the pixel delivery order according to the scan line. Therefore, during high speed reproduction, the data of the refresh block is sequentially written in the frame memory of the frame delay circuit 91. After that, the data in the frame memory of the frame delay circuit 91 is read in the pixel transmission order according to the scanning line to obtain a high-speed reproduced image. 27. Code Re-Swapping Circuit FIG. 52 is a diagram showing a configuration of the code re-swapping circuit 82. A signal obtained by error-correcting the reproduced bit stream from the VCR is input to the terminal 97.

This bit stream structure has the bit stream structure shown in FIGS. 37, 38 and 40 to 43. Therefore, first, the switch 82a separates the refresh slice and the non-refresh slice. The switch 82a is switched by inputting a (non-) refresh block ID and a (non-) refresh block position signal, which are indexes of the VCR data multiplex format shown in FIG. 44, from a terminal 98.

As a result, the refresh slice is stored in the refresh block memory 82b and the non-refresh slice is stored in the non-refresh block memory 82c.

Next, during normal reproduction, the switch 82d is used to read the signals from the refresh block memory 82b and the non-refresh block memory 82c using the refresh block memory read circuit 82e and the non-refresh block memory read circuit 82f.

At this time, reading is performed so that the refresh block address shown in FIG. 35 and the non-refresh block address match.

As a result, during normal reproduction, the terminal 83
As shown in the example of FIG. 34, the signal is output in the variable length code configuration of the macroblock.

The non-refresh block memory read circuit 82f calculates the address of each non-refresh block from the non-refresh block address of the refresh slice layer and the processor ID. A macro block is constructed using this address. Further, the code is read from the non-refresh block memory 82c using each non-refresh block code length.

The refresh block memory read circuit 82e calculates the address of the refresh block from the refresh block address of the refresh slice layer and the processor ID. There are two types of refresh slice configuration methods shown in FIGS. 40 and 41. In either of these methods, the refresh block memory read circuit 82e generates an address so that the output of the refresh block memory 82b can form a bitstream of a macro block. That is, the refresh block memory read circuit 82e
Can also replace refresh blocks.

When performing this read, the refresh block memory read circuit 82e processes using the refresh block code length.

During high speed reproduction, the switches 82a and 82d are the refresh block memory 82.
Only b is selected and only the refresh block is transmitted from the terminal 83.

When output to the decoder for receiving the broadcast wave data, the bit stream structure shown in FIG. 36 is basically transmitted.

Therefore, first, the macroblock address is sent to the decoder using the terminal 96. Starting from this macroblock address, the refresh block is sent out based on the macroblock configuration shown in FIG.

At the time of high speed reproduction, when constructing a one-frame screen, two or more refresh blocks may be reproduced within a macro block. In this case, the variable length code of the refresh block is arranged at the position of the super block in the macro block of FIG. 36, which corresponds to the position on the screen. In addition, the trick quantization levels TQL _{0 to} TQ ₀ corresponding to the position where the refresh block exists.
Set QL ₁₀ . The trick quantization level of the refresh block to be skipped may be set to TQL = 31. In the above-mentioned configuration, the switch 99 is used for separation into four processors.

FIG. 53 shows another embodiment of the code rearrangement circuit 82. This configuration is a circuit configuration suitable for the refresh slice layer shown in FIG.

In FIG. 41, refresh blocks in the refresh slice layer are arranged such that refresh blocks adjacent in the vertical direction are continuously arranged. Therefore, the refresh block memory 82b in the code re-placement circuit 82
Each processor has refresh block memories 82b1 to 82b4 therein. Each memory stores a refresh block corresponding to each processor. At the time of reading in the normal reproduction, the non-refresh block is combined with the switches 82g to 82j to form a macro block.

During high speed reproduction, the switch 82a selects only the refresh block and writes it in the refresh block memory 82b. Also, the switches 82g to 82
j reads only the refresh block memory 82b.

When there are two or more refresh blocks in the macroblock, there are two methods to send to the decoder.

The first method rearranges the refresh block in the macro block according to the mafro block address, sets the portion where no refresh block exists in the trick quantization level TQL = 31, and skips it in the decoder. Is a way to do.

In this case, in the code re-placement circuit 82,
When reading the refresh block memory 82b, the refresh block memory read circuit 82e rearranges the refresh blocks.

In the second method, the refresh block is inserted at the head position in the macroblock, and the remaining superblocks are all set to the trick quantization level TQL = 31 and skipped. After satisfying this condition, the position of the refresh block is specified by sending the macro block address. When there are two or more refresh blocks in the macroblock, a plurality of macroblock addresses are designated. In this case, the super block address is designated repeatedly in one frame period. However, since there is a skip, if the skip is detected before the address setting, there is no problem with the duplicate address designation. . 28. Frame Delay Circuit The frame delay circuit 91 has a memory write address generation circuit 91a as shown in FIG.

In the case of DigiCipher, the processing is performed by four processors and there are four macroblocks in the horizontal direction. Therefore, one macroblock is processed in the horizontal direction for each processor.

Therefore, per processor, macroblocks are processed from top to bottom in units of 11 superblocks in the macroblock.

A circuit for performing processing by these four processors is a variable length code decoding circuit 84, an inverse quantization circuit 86, an inverse D.
A CT circuit 85, an adder 87, a motion compensation circuit 92, an intra-frame / inter-frame switching circuit 89 and a switch 88, and a write address generation circuit 91a in a frame delay circuit 91.

The codes are distributed to the four processors by using the processor ID (PID) included in the macroblock overhead data.

Since the operations of these four processors are the same, the operation of one processor will be described.

The bit stream during normal reproduction is shown in FIG.
6. Since the macroblock bitstream shown in FIG. 39 is used, the projection start position is determined using the macroblock address at the beginning of the macropicture layer, that is, the macro slice layer, and then the processor ID is used. The addresses for normal reproduction are sequentially generated.

FIG. 55 is a diagram showing the operation of the write address generating circuit 91a during normal reproduction.

First, the macro block address at the head of the macro slice layer is set to the overhead data detection circuit 8
1 and the write address generation circuit 9 from the terminal 96.
Input to 1a.

FIG. 55 shows an example in the case of the processor 1.

First, the M. B. A =
Read 0. This M. B. A = 0 indicates the projection position of the super block at the head of the macro block of processor 0.

Since the projection position of the super block at the head of the macro block of the processor PID is expressed by the following expression, when the processor PID = 1, the head super block address of the macro block is 660 as shown in the following expression.
Becomes S. B. A = M. B. A + 660 × PID = 0 + 660 × 1 = 660 During normal reproduction, first, as indicated by an arrow in FIG. B. A = 66
11 super blocks from 0, 720, ..., 1260 are processed, and one macro block is processed in the vertical direction. That is, S. B. After A = 1260, S. B. A = 6
611, 721, ..., 1261 are processed.

At the time of high-speed reproduction, only the block processed in the frame is valid, so the write address generation circuit 91
Only the data of the refresh block is written in a.

Also, at the time of high speed reproduction, the code replacement circuit 82 outputs only the refresh block from the terminal 83. Variable length code decoding circuit 84, inverse quantization circuit 8
6. The inverse DCT circuit 85 processes only this refresh block and inputs only the refresh block from the terminal 100 to the frame memories 91d to 91f.

During high speed reproduction, only the bit stream of the refresh slice layer of FIGS. 40 and 41 is used. Since the refresh slice layer bitstream includes the refresh block address (RBA), which is the projection position at the beginning of the refresh slice, at the beginning,
This R. B. Using A and the processor ID (PID),
Know the initial position of high-speed playback signal processing of each processor.

Description will be made using the example of FIG.

From terminal 96, refresh block address R. B. A is the macroblock address M.A. B. Write address generation circuit 9 as A
Input to 1a. The refresh slice of FIG. 40 and FIG.
The correspondence of the refresh block G _n of the track pattern No. 3 is set as follows, and the trace x _{0 for} double speed reproduction is set.
The case of performing is described. Refresh slice 0: G _n (0) Refresh slice 1: G _n (1) In this case, the refresh block address is the R. B. A = 0 and R. of refresh slice 1. B. A = 90 is reproduced. This, R. B.
A = 0, R.I. B. A = 90 indicates the projection position of the refresh block at the head of the processor 0.

Since the projection position of the head super block of the refresh block of the processor PID is expressed by the following equation, when the processor PID = 1, the head super block address of the refresh block is S. B. In the case of A = 660 and refresh slice 1, S.S. B. A = 750. S. B. A ₀ = R. B. A + 660 × PID = 0 + 660 × 1 = 660 S.A. B. A ₁ = R. B. A + 660 × PID = 90 + 660 × 1 = 750. B. The macroblock initial address consisting of A is input to the write address generation circuit 91a from the terminal 96. The write address generation circuit 91a operates using this macroblock initial address as an initial value.

Frame memories 91d and 91 for high speed reproduction
The operation of the write address generating circuit for writing e and 91f is 2
There are two types by the operation of the code re-placement circuit 82 described in Chapter 7.

The first method is a method when the refresh block is rearranged in the macro block by the code rearrangement circuit 82. In this case, the processing may be the same as the write address generation processing during normal reproduction.

That is, as shown in FIG. 55, the macroblock is processed with the basic structure. At this time, the variable length code of the refresh block of the super block to be refreshed exists in the macro block, and the skip signal exists in the trick quantization level of the overhead data in the super block that is not refreshed.

That is, in the bit stream from the VCR to the decoder shown in FIG. 36, the trick quantization level TQL is set only where the refresh block exists, and TQL is set where the refresh block does not exist.
= 31 is set to skip. So this TQL
Therefore, write the refresh block.

The second method is a case in which the refresh block in the macro block is not rearranged by the code rearrangement circuit 82.

In this case, in the bit stream (FIG. 36) when the code is sent from the VCR to the decoder, the variable length code of the refresh block exists in the super block 0, and the variable length code is present in the super block 1 to the super block 10. not exist.

Therefore, the trick quantization level TQL
₀ represents a variable length code of the refresh block, and trick quantization levels TQL _{1 to} TQL ₁₀ are 31 representing skip.

This macroblock bitstream structure can be easily realized only by setting the trick quantization level in the bitstream of the refresh block shown in FIG. Therefore, it is easy to convert the bit stream to the decoder during high-speed reproduction.

The operation of the write address generating circuit 91a during high speed reproduction will be described with reference to FIG. A write address generation circuit 91a in the frame delay circuit 91 of the decoder
First confirms that all the trick quantization levels TQL _{1 to} TQL ₁₀ are in the skip state in the macroblock bitstream of FIG. 36. As a result, as indicated by the dotted line in the frame of FIG. 56, super blocks 1 to 10 in the macro block recognize that they are skips. Skip means frame memory 91
Since writing to d, 91e, and 91f is not performed, no address is generated in the skip portion. That is, as a result, the address is generated only in the portion where the refresh block exists, so that the address is generated in the vertical direction. FIG. 56 shows the case of DigiCipher.

In the case of DigiCipher, the refresh block is arranged in the vertical direction inevitably for each processor. Therefore, at the time of high speed reproduction, the write address generating circuit 9
1a consequently generates a super block address in the vertical direction. That is, S. B. A ₀ : 660, 661, ..., 687, 68
8,689 S.M. B. A ₁ : 750,751, ..., 777,77
Superblock addresses are generated in the order of 8,779.

Next, the read address generating circuit 91g
The luminance signal Y and the color signals U and V are read according to the scanning line order of the TV.

The frame delay circuit 91 and the memory write / read address generation circuits 91a and 91g also function as the deblocking circuit 90.

When the frame memory write / read described above is performed, the read address is set in the scanning line order in the horizontal direction, and the write is performed in the vertical direction. Therefore, the write and read settings must be made in the same chip memory. It may happen when you do it. Further, there may be a case where it is necessary to set two addresses in the same chip memory.

In a generally popular memory, the read / write control signal R / W is controlled by 1 bit. Further, it is impossible to set a plurality of addresses with one memory element.

Therefore, as shown in FIG. 54, sub memories 91i, 91j, 91k are used. Reference numeral 91i is a sub memory for luminance signals, and 91j and 91k are sub memories for color signals U and V.

Since it is necessary to send data to the TV monitor in scanning line order, the read address generating circuit 91
The read address of g is always generated along the scanning line order. When the read address and the write address must be set simultaneously in the same chip memory in the frame memories 91d, 91e, and 91f, writing is performed after the reading is completed.

Specifically, it is as follows. First, temporary data is stored in the sub memories 91i, 91j, 91k. The sub memories 91i, 91j, 91k are memories corresponding to the luminance signal Y and the color signals U, V, respectively.

Control of write / read addresses of the sub memories 91i, 91j and 91k is performed by the sub memory write / read control circuit 911.

The input signals of the sub memories 91i, 91j, 91k are the same signals as those of the frame memories 91d, 91e, 91f, and the adder circuit 87 is added to the signal subjected to the inverse DCT.
The signal passed through is input.

The output signals of the sub memories 91i, 91j and 91k pass through the terminal 91m and the switch 91h,
Input to the frame memories 91d, 91e, 91f. At this time, the timing of writing from the sub memories 91i, 91j, 91k to the frame memories 91d, 91e, 91f is such that after the reading of the memory of one element of the frame memories 91d, 91e, 91f is completed, the writing of the memory to that element is completed. Do.

The switch 91h normally selects the signal of the terminal 100, and the sub memories 91i, 91j, 91k are selected.
The terminal 91m is selected only when data is transferred from the frame memory 91d to the frame memories 91e to 91f. 29. Track reproduction control circuit Since the refresh slice was recorded around a predetermined position of the track during recording, the tape feed and the drum rotation phase are controlled so as to reproduce this predetermined position during high speed reproduction. There are various methods for performing this control as follows.

1. The position to be traced by the head during high speed reproduction is recorded on the linear track.

2. A signal for identifying the track is recorded on the helical track. The identification signal includes a pilot signal and the like.

3. The track number and unit number are recorded on the helical track, and servo is applied so that the envelope of the unit number to be read at the time of high-speed reproduction becomes maximum.

The third method will be described in detail.

First, a unit number and a track number are read as additional information arranged after the unit sync of the VCR transmission data of FIG. 44, and read from the terminal 101 of FIG. Refresh slice arrangement position designation R in FIG. 48
With the OM70c, centering on a predetermined position on the track,
Recording a refresh slice. The predetermined position is determined by the track number and the unit number. On the other hand, during high speed reproduction, the RF signal reproduced from the head is input to the envelope detection circuit 103 from the terminal 102.

In the envelope detection circuit 103, FIG.
The envelope shape at the time of high-speed reproduction shown in (b) is grasped. The track reproduction control circuit 74 controls the rotational phase of the drum and the tape feed so that the envelope of the track number and the unit number where the center position of the refresh slice exists is maximized.

The present invention is not limited to the above-mentioned embodiments, but can be variously modified and implemented without departing from the scope of the invention.

[0476]

As described above in detail, according to the present invention,
It is possible to provide an extremely good band-compressed signal processing device that can easily obtain a good reproduced image during high-speed reproduction.

[Brief description of drawings]

FIG. 1 is a block diagram showing an embodiment of a band compression signal processing device according to the present invention.

FIG. 2 is a diagram showing a pixel configuration of the embodiment.

FIG. 3 is a diagram shown for explaining a super block address of the embodiment.

FIG. 4 is a diagram shown for explaining refreshing of the embodiment.

FIG. 5 is a diagram shown for explaining refreshing of the embodiment.

FIG. 6 is a block configuration diagram showing an intra-frame / inter-frame determination circuit of the same embodiment.

FIG. 7 is a diagram showing characteristics during intra-frame / inter-frame determination of the same embodiment.

FIG. 8 is a diagram shown for explaining forced refresh of the embodiment.

FIG. 9 is a diagram for explaining forced refresh per processor in the embodiment.

FIG. 10 is a diagram showing a scan order when performing zigzag scanning of DCT coefficients.

FIG. 11 is a diagram showing an example of a quantization table.

FIG. 12 is a diagram showing an example of a weighting table.

FIG. 13 is a diagram showing an example of converting the weighting table into the number of bits.

FIG. 14 is a diagram showing the number of generated bits according to a quantization table.

FIG. 15 is a diagram showing the number of generated bits according to a quantization table.

FIG. 16 is a timing chart shown for explaining the operation of the embodiment.

FIG. 17 is a diagram showing a relationship between refresh blocks having frame numbers F ₅ and F ₆ and non-refresh blocks in the embodiment.

FIG. 18 is a diagram showing a track pattern in the example.

FIG. 19 is a diagram showing a head trace locus during double-speed reproduction in the example.

FIG. 20 is a diagram showing a refreshable refresh block of frames 1 to 8 in the embodiment.

FIG. 21 is a diagram showing a reproducible refresh block of frames 9 to 11 and a refresh block in which 11 frames are accumulated in the embodiment.

FIG. 22 is a diagram showing frame numbers F _n and F _{n + 1} in the same embodiment.
FIG. 6 is a diagram showing the relationship between refresh blocks and non-refresh blocks of FIG.

FIG. 23 is a diagram showing a head trace locus during double-speed reproduction in the example.

FIG. 24 is a diagram showing a configuration of a rate buffer.

FIG. 25 is a diagram showing the operation of the rate buffer on the encoder side.

FIG. 26 is a diagram showing the operation of the rate buffer on the decoder side.

FIG. 27 is a diagram showing increase / decrease in buffer occupancy and quantization level.

FIG. 28 is a block diagram showing the details of a quantization level setting circuit of the embodiment.

FIG. 29 is a diagram showing a generated code amount when variable length coding is performed.

FIG. 30 is a diagram showing the relationship between DCT coefficient energy and corrected quantization level.

FIG. 31 is a diagram shown for explaining the operation of controlling the code amount of a refresh block.

FIG. 32 is a diagram showing an example of quantization levels of a macro block and a refresh block.

FIG. 33 is a diagram showing macroblocks and (non-) refresh blocks.

FIG. 34 is a diagram shown for explaining a macroblock address.

FIG. 35 is a diagram shown for explaining a (non-) refresh block address.

FIG. 36 is a diagram shown for explaining a bitstream structure of a macroblock.

FIG. 37 is a diagram shown for explaining a bitstream structure of a refresh block.

FIG. 38 is a diagram shown for explaining a bitstream structure of a non-refresh block.

[Fig. 39] A macro slice layer, a picture layer, G. O. P
The figure which shows the structure of a layer.

[Fig. 40] A refresh slice layer, a picture layer, G.
O. The figure which shows the structure of P layer No1.

[Fig. 41] A refresh slice layer, a picture layer, G.
O. The figure which shows the structure of P layer No2.

FIG. 42 is a non-refresh slice layer, a picture layer,
G. O. The figure which shows the structure of P layer.

FIG. 43 is a diagram showing the structure of a picture layer of a VCR.

FIG. 44 is a diagram showing the structure of VCR transmission data.

FIG. 45 is a diagram showing an example of a structure of transmission data of a VCR.

FIG. 46 is a block configuration diagram showing details of a code exchange circuit.

FIG. 47 is a diagram showing (non-) refresh block memory write control timing.

FIG. 48 is a block diagram showing a memory read (non-) refresh slice combination control circuit.

FIG. 49 is a diagram shown for explaining an envelope during high-speed playback of a VCR.

FIG. 50 is a block diagram showing an embodiment of the decoder side of the present invention.

FIG. 51 is a diagram showing a relationship between an index, overhead data, and each circuit.

FIG. 52 is a block configuration diagram showing details of the code re-placement circuit.

FIG. 53 is a block diagram showing another example of the code re-swapping circuit.

FIG. 54 is a block diagram showing details of a frame delay circuit.

FIG. 55 is a diagram shown for explaining the operation of the frame delay circuit during normal reproduction.

FIG. 56 is a diagram shown for explaining the operation of the frame delay circuit during high-speed reproduction.

FIG. 57 is a block diagram showing a conventional band compression system.

FIG. 58 is a diagram showing a format of a signal transmitted from the conventional system.

FIG. 59 is a diagram showing refreshable refresh blocks of frames 1 to 8 during normal reproduction in the conventional system.

FIG. 60 is a diagram showing refreshable blocks that can be reproduced in frames 9 to 11 and refresh blocks that have accumulated 11 frames during normal reproduction in the conventional system.

FIG. 61 is a diagram showing a track pattern in the conventional system.

FIG. 62 is a diagram showing a head trace locus during double-speed reproduction in the conventional system.

FIG. 63 is a diagram showing refresh blocks capable of reproducing frames 1 to 8 during double speed reproduction in the conventional system.

FIG. 64 is a diagram showing refreshable blocks that can be played back from frames 9 to 11 and refresh blocks that have accumulated 11 frames during double-speed playback in the conventional system.

[Explanation of symbols]

11 ... Input terminal, 12 ... Subtraction circuit, 13 ... Motion evaluation circuit, 14 ... DCT circuit, 15 ... Quantization circuit, 16 ... Variable length coding circuit, 17 ... FIFO circuit, 18 ... Output terminal,
19 ... Inverse quantization circuit, 20 ... Inverse DCT circuit, 21 ... Addition circuit, 22 ... Frame delay circuit, 23 ... Motion compensation circuit,
24, 25 ... Switch, 26 ... Magnetic tape, 27-29
... video input terminal, 30 ... blocking circuit, 31 ... intra-frame / interval determining circuit, 32, 33 ... input terminals, 34, 35
... output terminal, 36 ... energy comparison circuit, 37 ... subtraction circuit, 38 ... addition circuit, 39 ... periodic refresh timing generation circuit, 40 ... synchronization signal detection circuit, 41 ... output terminal, 42 ... track formation signal generation circuit, 43 ... rotary drum, 44 ... track formation control circuit, 45 ... sign exchange circuit, 46 ... track, 47 ... index insertion circuit,
48 ... Index generating circuit, 49 ... Multiplexer,
50 ... ECC circuit, 51 ... Unit sync insertion circuit, 5
2 ... Modulation circuit, 53 ... Quantization level setting circuit, 54 ... Super block code amount calculation circuit, 55 ... Macro block code amount calculation circuit, 56 ... Transmission code amount ROM, 57 ... Rate buffer code amount calculation circuit, 58 ... Macro Block quantization level setting circuit, 59 ... Refresh block quantization level setting circuit, 60 ... Non-refresh block quantization level setting circuit, 61, 62 ... Input terminal, 63 ... DCT
Coefficient energy calculation circuit, 64 ... Adder, 65 ... Refresh block code amount calculation circuit, 66 ... Switch, 67
... overhead data generation circuit, 68, 69 ... output terminal, 70 ... memory read (non-) refresh slice combination control circuit, 71 ... terminal, 72 ... reproduction speed setting circuit, 73 ... tape feed control circuit, 74 ... track reproduction control Circuit, 75 ... Switch, 76 ... Error correction circuit, 77
... unit sync detection circuit, 78 ... index detection circuit, 79 ... code length detection circuit, 80 ... terminal, 81 ... overhead data detection circuit, 82 ... code replacement circuit,
83 ... Terminal, 84 ... Variable length code decoding circuit, 85 ... Inverse DC
T circuit, 86 ... Inverse quantization circuit, 87 ... Adder, 88 ... Switch, 89 ... In-frame / inter-frame switching circuit, 90 ... Deblocking circuit, 91 ... Frame delay circuit, 92 ... Motion compensation circuit, 93-95 ... output terminals, 96 to 98 ... terminals,
99 ... Switch, 100-102 ... Terminal, 103 ... Envelope detection circuit.

Claims (1)

[Claims] 1. A frame in which a number (a is a positive integer) of image regions is formed in a video signal of one screen, and the video signal is subjected to intraframe coding processing using information in the frame. An intra-processed signal and an inter-frame processed signal that has been subjected to inter-frame encoded processing using difference information between frames are created, and after the intra-frame encoded processing, the inter-frame encoded processing is applied, and this signal A band compression unit that adaptively repeats the processing method according to the motion evaluation of the input video signal, and f frames (f is an integer of f ≧ 2) as a cycle, and b units of the a regions are set for each frame. Refresh encoding processing means for periodically performing the intraframe encoding processing on a signal in an image area, means for recording / reproducing a band-compressed signal subjected to the band compression means, and a head for high-speed reproduction by the recording / reproducing means. Is training And a band-compressed signal recording / reproducing device which arranges the signal subjected to the refresh encoding processing around a specific position where the envelope is maximized.