JP3854688B2 - Image processing apparatus, image processing method, and computer-readable recording medium - Google Patents

Description

[0001]
BACKGROUND OF THE INVENTION
The present invention relates to an image processing apparatus, an image processing method, and a computer-readable recording medium used in the image processing apparatus that are suitable for use in playback of a digital recording / playback apparatus including a camcorder, a video cassette recorder, and the like.
[0002]
[Prior art]
FIG. 7 shows the relationship between the video area information of each track and the image of one frame in a conventional digital VTR in which one frame of image data is recorded on n tracks. FIG. 8 shows a search reproduction method in such a conventional digital VTR.
As shown in FIG. 8A during normal reproduction, the inclination of the head that scans the recording track is as shown in FIG. 8B during search reproduction, and the scanning direction changes. For this reason, the head does not scan the entire recording track, and scans a portion of each recording track.
[0003]
FIG. 9 shows a conventional digital recording / reproducing apparatus. First, the recording system will be described. In FIG. 9, 401 is a video signal input terminal, 402 is an A / D converter that performs analog-to-digital conversion, and 403 is a digitized video signal in a data sequence of N × M (N, M: integer) block units. Blocking circuit for transforming 404, orthogonal transform circuit for performing orthogonal transform such as DCT (Discrete Cosine Transform) on block unit data and outputting orthogonal transform coefficients, 405 orthogonal transform to reduce the amount of data of orthogonal transform coefficients Quantization circuit for quantizing coefficients, 406 is a variable-length coding circuit that quantizes quantized data and then converts it to fixed-length data, and 407 is a fixed correction code used for error correction during reproduction Correction code adding circuit for adding to long data, 408 is a modulation circuit for converting correction code added fixed length data to data suitable for recording by NRZ modulation or the like 409 is a recording and reproducing unit for recording and reproducing modulation data.
[0004]
Next, the operation of this recording system will be described.
The video signal input from the input terminal 401 is converted by the A / D converter 402 into a digital video data string indicating pixel unit information. Next, the digital video data sequence is converted into a block data sequence (in this case, 8 × 8 pixel unit), which is a unit to be orthogonally converted by the orthogonal conversion circuit 404 by the blocking circuit 403, and orthogonally converted by the orthogonal conversion circuit 404. Converted to conversion factor. This orthogonal transform coefficient is composed of one DC coefficient indicating a DC component in the block data string and a plurality of AC coefficients indicating AC components.
[0005]
Next, the orthogonal transform coefficients in block units are quantized by the quantization circuit 405, and are sequentially output from DC coefficients to higher order AC coefficients. The variable-length coding circuit 406 performs variable-length coding to reduce the data amount by changing the bit width of the quantized block-unit orthogonal transform coefficient, and determines block-unit variable-length coded data in units of multiple blocks. The predetermined data amount is suppressed and converted into a fixed-length data string. Each fixed-length data string is added with a correction code by a correction code adding circuit 407, modulated by a modulation circuit 408, and recorded on a recording medium (here, a magnetic tape) by a recording / reproducing unit 409.
[0006]
FIG. 10 shows orthogonal transform coefficients output from the orthogonal transform circuit 404. The orthogonal transform coefficient has one DC coefficient and 63 AC coefficients. The AC coefficient is composed of an ACL coefficient and an ACH coefficient as will be described later.
FIG. 11 shows track configuration data. Here, as shown in FIGS. 11A and 11B, a plurality of orthogonal transform coefficient blocks grouped by one sync code is called a sync block, and a block of a fixed length unit consisting of a plurality of sync blocks is called a fixed length block. To. In one orthogonal transform coefficient block, as shown in FIG. 11A, the DC and AC coefficients quantized and variable-length coded by the quantization circuit 405 and the variable-length coding circuit 406 have been predetermined. Will be placed within the amount of data. When it falls within the predetermined data amount, the AC coefficient becomes an ACL coefficient, and when it exceeds the predetermined data amount, it is stored together with the ACL coefficient as an ACH coefficient in another orthogonal transform coefficient block within the fixed-length block. At this time, the ACH coefficients are distributed and arranged in the fixed-length block as shown in the figure. Therefore, when the amount of fixed-length block data is exceeded, the ACH coefficient is lost. As shown in FIG. 11 (c), the fixed-length block is divided into sync blocks and recorded across a plurality of recording tracks.
[0007]
Next, the reproduction system of FIG. 9 will be described.
In FIG. 9, 702 is an equivalent circuit, 703 is an error correction circuit, 704 is a variable length decoding circuit, 705 is an inverse quantization circuit, 706 is an inverse orthogonal transform circuit, 707 is an inverse block circuit, and 708 is a D / A converter. , 709 are video signal output terminals.
[0008]
Next, the operation of this reproduction system will be described.
The recorded compressed data reproduced by the recording / reproducing unit 409 is subjected to reproduction equalization by the equivalent circuit 702 and then subjected to error correction processing in the error correction circuit 703. The output of the error correction circuit 703 is subjected to variable length decoding processing, inverse quantization processing, and inverse orthogonal transformation processing by a variable length decoding circuit 704, an inverse quantization circuit 705, and an inverse orthogonal transformation circuit 706, and M × N pixel It becomes block unit digital image data. This image data is converted into analog video data by an inverse block circuit 707 and a D / A converter 708 and output from an output terminal 709. Here, as described in the recording system, since the fixed-length block extends over a plurality of recording tracks, the variable-length decoding process performed by the variable-length decoding circuit 704 is divided into recording tracks. Executed after all fixed length blocks have been played.
[0009]
At the time of search reproduction, as described above, the partial data is only reproduced within each recording track. If all the data in the divided fixed-length block, that is, the sync block is reproduced in the partial data, it is possible to decode the DC and ACL coefficients of the orthogonal transform coefficient block. However, the ACH coefficient includes all the data in the fixed-length block. Since it cannot be decoded unless it is reproduced, the ACH coefficient cannot be decoded during search reproduction.
[0010]
[Problems to be solved by the invention]
As described above, in the conventional digital recording / reproducing apparatus, even when the same still image is recorded in a plurality of frames, the ACH coefficient is not decoded at the time of search reproduction, and thus the high-order orthogonal transform coefficient is lacking. Since the image is an image and lacks a high frequency component, there is a problem that the image quality is remarkably deteriorated.
[0011]
The present invention solves the above-described problem, and an object thereof is to prevent a high frequency component from being lost during search reproduction.
[0012]
[Means for Solving the Problems]
The image processing apparatus of the present invention inputs an image signal and corrects an error, and outputs an error correction means for outputting a no error signal when the processed image signal has no error, and an image signal error-corrected by the error correction means. Accumulating means for accumulating; detecting means for detecting that the image signal is a still image; determining means for determining whether or not all of the image signals in one screen are no error; and detecting the image signal by the detecting means Output means for reading out and outputting a no-error image signal stored in the storage means when it is detected that the image is a still image and all of one screen is determined to be no error by the determination means. And
[0013]
The computer-readable storage medium of the present invention is error-corrected by inputting an image signal to correct an error and outputting a no-error signal when there is no error in the processed image signal and the error correcting procedure. An accumulation procedure for accumulating the image signal in the accumulation means, a detection procedure for detecting that the image signal is a still image, a determination procedure for determining whether or not all of the image signals in one screen are no errors, An output procedure for reading out and outputting a no-error image signal stored in the storage means when it is detected by the detection procedure that the image signal is a still image and all of one screen is determined to be no error by the determination procedure; A program for causing a computer to execute is recorded.
The image processing method according to the present invention includes an error correction step of inputting an image signal to correct an error and outputting a no error signal when the processed image signal has no error, and an image signal error-corrected by the error correction step. An accumulating step for accumulating in the accumulating means; a detecting step for detecting that the image signal is a still image; a determining step for determining whether or not all of the image signals in one screen are no error; and the detecting step When the image signal is detected to be a still image, and the determination step determines that no error has occurred in one screen, the output step includes reading and outputting the no-error image signal stored in the storage means. It is characterized by that.
[0014]
DETAILED DESCRIPTION OF THE INVENTION
Embodiments of the present invention will be described below.
FIG. 1 shows a digital recording / reproducing apparatus according to a first embodiment. In the recording system of FIG. 1, 101 is a video signal input terminal, 102 is an A / D converter, 103 is a blocking circuit, 104 is an orthogonal transformation circuit, 105 is a quantization circuit, 106 is a variable length coding circuit, and 107 is a correction. Reference numeral 108 denotes a modulation circuit, 109 denotes a recording / reproducing unit, and 110 denotes a moving image / still image mode signal input terminal.
[0015]
In the reproduction system, 111 is an equivalent circuit, 112 is an error correction circuit, 113 is a memory, 114 is a selector, 115 is a still image detection / no error timing generation circuit, 116 is a variable length decoding circuit, 117 is an inverse quantization circuit, 118 Is an inverse orthogonal transform circuit, 119 is a deblocking circuit, 120 is a D / A converter, and 121 is a video signal output terminal.
[0016]
Reference numeral 122 denotes a microcomputer (microcomputer) that controls the recording system and the reproduction system in accordance with a program, and 123 denotes a memory as a recording medium that records the program according to the present invention. The processing shown in the flowchart of FIG. ing. As the memory 123, a semiconductor memory, a magneto-optical disk, an optical disk, a magnetic medium, or the like can be used.
[0017]
Next, the operation will be described with reference to the flowchart of FIG.
At the time of recording, if there is a recording instruction, the analog video signal input from the video signal input terminal 101 is converted into a digital video signal by the A / D converter 102, and an image of one frame is converted to M × by the blocking circuit 103. The block is divided into N (M, N: integer) pixel units. The orthogonal transform circuit 104 performs orthogonal transform such as discrete cosine transform (DCT) on the input digital video signal in units of blocks, and outputs orthogonal transform coefficients in units of blocks (steps S1 and S2). The orthogonal transform coefficient is quantized in the quantization circuit 105, and the quantized orthogonal transform coefficient is output (step S3). The variable length encoding circuit 106 converts the input quantized orthogonal transform coefficient into a variable length code (step S4).
[0018]
The correction code addition circuit 107 adds a moving image / still image mode signal to the input variable length code in accordance with the moving image / still image mode signal input from the moving image / still image mode signal input terminal 110, and corrects the moving image mode. A code addition process or a still image mode correction code addition process is performed (step S5). The correction code added data is input to the modulation circuit 108 and modulated into data suitable for recording such as NRZ modulation, and then input to the recording / reproducing unit 109 and recorded on a recording medium such as a magnetic tape (step S6). .
[0019]
FIG. 3 is an explanatory diagram of a correction code addition data string output from the correction code addition circuit 107. In the moving image mode, as shown in FIG. 3A, correction codes are added to the sync block and fixed-length block unit signals in the frame corresponding to the input video signal, and correction code added data corresponding to the input frame as needed. Is output. In the still image mode, correction code added data for S frames (S: integer) is repeatedly output as shown in FIG.
[0020]
Returning to FIG. 2, at the time of reproduction, when there is an instruction for reproduction, the recording data reproduced from the recording / reproducing unit 109 is subjected to reproduction equalization by the equivalent circuit 111 and then subjected to error correction processing in the error correction circuit 112. Performed (steps S7 and S8). Data in which no error has occurred in sync block units as a result of error correction processing is stored in the memory 113. At this time, a no error block signal indicating the presence or absence of an error is input to the still image detection / no error timing signal generation circuit 115. The still image detection / no error timing signal generation circuit 115 also receives recording data including whether or not the data being reproduced is a still image (step S9). Next, it is checked whether the input sync block is a still image and no error sync block. If so, the read output of the memory 113 is input to the variable length decoding circuit 116. The selector 114 is controlled so that the output of the error correction circuit 112 is input to the variable length decoding circuit 116 (steps S10 and S11).
[0021]
The output data of the selector 114 is subjected to variable length decoding processing, inverse quantization processing, and inverse orthogonal transformation processing by a variable length decoding circuit 116, an inverse quantization circuit 117, and an inverse orthogonal transformation circuit 118. It becomes block unit digital image data, is converted into analog video data by the inverse blocking circuit 119 and the D / A converter 120, and is output from the output terminal 121 (steps S12, S13, S14).
[0022]
FIG. 4 is a diagram for explaining the operation during still image search reproduction. As shown in FIG. 4A, at the time of search reproduction, only a part of one recording track is reproduced. However, if there is no error in the sync block in the search reproduced part, the data is stored in the memory 113. FIG. 4B is a track image in the memory 113. The sync block in which no error has occurred from each track during the S frame search reproduction period is stored in the memory 113 as shown in FIG. In step S 10 in FIG. 2, it is determined whether or not n sync blocks, which are fixed-length blocks, are accumulated in the memory 113, and when they are accumulated, the still image detection / no error timing signal generation circuit 115 outputs the memory 113. The selector 114 is controlled to select.
[0023]
When the selector 114 selects the output of the error correction circuit 112, all sync blocks in the fixed length block have not been searched and reproduced yet, and the variable length decoding circuit 116 decodes the DC and ACL coefficients. When the selector 114 selects the output of the memory 113, all sync blocks have already been searched and reproduced, and all of the DC, ACL, and ACH coefficients can be decoded.
[0024]
The output of the still image detection / no error timing signal generation circuit 115 is reset when moving image search reproduction is performed or when it is changed to a still image, and the output of the error correction circuit 112 is selected.
[0025]
FIG. 5 shows a detailed configuration of the still image detection / no error timing signal generation circuit 115. In FIG. 5, 1001 is a recording data input terminal, 1002 is a still image detection circuit, 1003 is a delay adjustment circuit, 1004 is a no error block signal input terminal, 1005 is a position information detection circuit, 1006 is a fixed length block number detection circuit, and 1007 is A write address generation circuit, 1008 is a read address generation circuit, 1009 is a reset circuit, 1010 is a no error flag memory, 1011 is a delay circuit, 1012 is a no error block determination circuit, 1013 is an output signal generation circuit, and 1014 is an output terminal.
[0026]
The still image detection circuit 1002 receives the recording data that is the output of the equivalent circuit 111 from the recording data input terminal 1001, and is recorded outside the still image information or the video compression data area included in the video compression data area in the recording data. Still image information is taken out, it is determined that the reproduction signal is a moving image or a still image, and a signal for identifying the still image is output when the still image is reproduced. The output of the still image detection circuit 1002 is input to the delay adjustment circuit 1003, and the timing is adjusted with the output of the no error block determination circuit 1012.
[0027]
On the other hand, the no error block signal that is the output of the error correction circuit 112 input from the no error block signal input terminal 1004 is input to the position information detection circuit 1005, and the position information on the screen of the no error block, during the same still image period. The still image number that is the same number is output. Position information, which is one of the outputs of the position information detection circuit 1005, is input to the fixed length block number detection circuit 1006, and the fixed length block number detection circuit 1006 detects the number of the fixed length block including the no error block. This position information is also input to the write address generation circuit 1007, which generates a write address corresponding to the position on the screen of the no error flag memory 1010, and the position on the screen of the no error flag memory 1010. A no error flag is set at the address corresponding to.
[0028]
The fixed-length block number including the no-error block, which is the output of the fixed-length block number detection circuit 1006, is input to the read address generation circuit 1008 and read in the n no-error flag memories 1010 included in the corresponding fixed-length block. Generate an address. The still image number, which is one of the outputs of the position information detection circuit 1005, is input to the reset circuit 1009. When the still image number changes and the reproduction still image changes, a signal for resetting all the flags in the no error flag memory 1010 is output. To do.
[0029]
The no error flag memory 1010 sequentially reads all no error flags in the same fixed length block in accordance with the read address output from the read address generation circuit 1008, and inputs them to the delay circuit 1011. In the no error block determination circuit 1012, the same fixed length block Whether or not all data in the fixed-length block is accumulated in the memory 113 as no error is determined from all the no error flags. The output signal generation circuit 1013 receives the still image identification signal output from the delay adjustment circuit 1003 and the output from the no error block determination circuit 1012, generates a signal for controlling the selector 114, and outputs it from the output terminal 1014.
[0030]
FIG. 6 shows a digital recording / reproducing apparatus according to the second embodiment. FIG. 6 shows only the reproduction system, and parts corresponding to those in FIG. The recording system is configured in the same manner as in FIG. Reference numeral 124 denotes a memory having two banks, 125 denotes a digital interface circuit, and 126 denotes an output terminal.
[0031]
Next, the operation during reproduction will be described.
In the first bank of the memory 124, error correction processing is performed in the error correction circuit 112, and no error data subjected to error correction is updated and stored. The still image detection / no error timing signal generation circuit 115 receives the recording data output from the equivalent circuit 111 and the no error block signal output from the error correction circuit 112, and when all the playback still images become no error blocks, or the playback still image When the error block is minimized including the error block immediately before the image changes, a still image detection / no error timing signal is output to the digital interface circuit 125.
[0032]
The digital interface circuit 125 repeatedly reads out the compressed video data from the first bank of the memory 124 according to the still image detection / no error timing signal, and outputs it from the output terminal 126. While the digital interface circuit 125 continues to repeatedly read from the first bank of the memory 124, the output of the error correction circuit 112 is accumulated in the second bank of the memory 124, and the first and second banks alternately alternate in the error correction circuit 112. The digital interface circuit 125 is accessed.
[0033]
【The invention's effect】
As described above, according to the present invention, it is detected that the image signal is a still image, and when the no-error signal is already obtained and the no-error image signal is accumulated, the image signal accumulated in the accumulation means is obtained. Since the data is read out, the image quality can be improved.
[Brief description of the drawings]
FIG. 1 is a block diagram showing a digital recording / reproducing apparatus according to a first embodiment of the present invention.
FIG. 2 is a flowchart showing the operation of the digital recording / reproducing apparatus according to the first embodiment of the present invention.
FIG. 3 is a configuration diagram showing a correction code-added data string.
FIG. 4 is a configuration diagram showing a search reproduction operation.
FIG. 5 is a block diagram showing a still image detection / no error timing signal generation circuit;
FIG. 6 is a block diagram showing a digital recording / reproducing apparatus according to a second embodiment of the present invention.
FIG. 7 is a block diagram showing the image positional relationship of tracks.
FIG. 8 is a configuration diagram showing head scanning during reproduction.
FIG. 9 is a block diagram showing a conventional digital recording / reproducing apparatus.
FIG. 10 is a configuration diagram illustrating orthogonal transform coefficients.
FIG. 11 is a configuration diagram showing track configuration data.
[Explanation of symbols]
109 Recording / Reproducing Unit 112 Error Correction Circuit 113 Memory 114 Selector 115 Still Image Detection / No Error Timing Signal Generation Circuit 116 Variable Length Decoding Circuit 117 Inverse Quantization Circuit 118 Inverse Orthogonal Transform Circuit

Claims (9)

Error correction means for inputting an image signal to correct an error and outputting a no error signal when there is no error in the processed image signal;
Storage means for storing the image signal error-corrected by the error correction means;
Detecting means for detecting that the image signal is a still image;
A determination means for determining whether or not all of the image signal in one screen is a no error;
An output means for reading out and outputting a no-error image signal stored in the storage means when it is detected by the detection means that the image signal is a still image, and the judgment means determines that there is no error in one screen. An image processing apparatus comprising: The image signal is a signal reproduced from a recording medium,
Play back the part where the same still image part of the recording medium is recorded for multiple screens,
The output means reads and outputs a no-error image signal stored in the storage means when the determination means determines that all of the same still image portion in one screen is no error. The image processing apparatus described.   3. The image processing apparatus according to claim 1, further comprising decoding means for decoding a no-error image signal output by the output means. An error correction procedure for inputting an image signal to correct an error and outputting a no error signal when there is no error in the processed image signal;
An accumulation procedure for accumulating the image signal corrected by the error correction procedure in an accumulation means;
A detection procedure for detecting that the image signal is a still image;
A determination procedure for determining whether or not all of the image signal in one screen is a no error;
An output procedure for reading out and outputting a no-error image signal stored in the storage means when it is detected by the detection procedure that the image signal is a still image and all of one screen is determined to be no error by the determination procedure; A computer-readable recording medium on which a program for causing a computer to execute is recorded. The image signal is a signal reproduced from a recording medium,
Play back the part where the same still image part of the recording medium is recorded for multiple screens,
5. The output procedure reads out and outputs a no-error image signal stored in the storage means when all of the same still image portion in one screen is determined to be no error according to the determination procedure. The computer-readable recording medium as described.   6. The computer-readable recording medium according to claim 4 or 5, wherein a computer executes a decoding procedure for decoding a no-error image signal output by the output procedure. An error correction step of inputting an image signal to correct an error and outputting a no error signal when there is no error in the processed image signal;
An accumulation step of accumulating the image signal corrected by the error correction step in an accumulation unit;
A detection step of detecting that the image signal is a still image;
A determination step of determining whether or not all of the image signal in one screen is a no error;
An output step of reading out and outputting a no-error image signal stored in the storage means when the detection step detects that the image signal is a still image and the determination step determines that there is no error in one screen. An image processing method comprising: The image signal is a signal reproduced from a recording medium,
Play back the part where the same still image part of the recording medium is recorded for multiple screens,
The output step reads out and outputs a no-error image signal stored in the storage means by the storage step when it is determined by the determination step that all the same still image portions in one screen are no error. Item 8. The image processing method according to Item 7.   9. The image processing method according to claim 7, further comprising a decoding step of decoding the no-error image signal output by the output step.

Images