JPH1141557A - Image processing unit and computer-readable recording medium - Google Patents

Abstract

PROBLEM TO BE SOLVED: To prevent the loss of high frequency components in the case that fixed length coded image data are stored and searched and reproduced. SOLUTION: Image data orthogonally converted, quantized and variable- length-coded are recorded by a recording reproducing section 109 and in the case of searching and reproducing the data, errors of the reproduced image data are corrected and no-error data are stored in a memory 113. A still image detection no-error timing signal generating circuit 115 switches a selector 114 to the position of the memory 113 when data of a plurality of images on a plurality of tracks are still image data and there is no error. The data read from the memory 113 are subject to variable length decoding, inverse quantization and inverse orthogonal transform to be decoded.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an image processing apparatus suitable for use in reproducing a digital recording / reproducing apparatus including a camcorder, a video cassette recorder, and the like, and a computer-readable recording medium used in the image processing apparatus. .

[0002]

2. Description of the Related Art FIG. 7 shows a conventional digital VTR in which one frame of image data is recorded on n tracks.
3 shows the relationship between the video area information of each track and the image of one frame. FIG. 8 shows a search reproduction method in such a conventional digital VTR. During normal reproduction, the tilt of the head scanning the recording track as shown in FIG. 8A becomes as shown in FIG. 8B during search reproduction, and the scanning direction changes. For this reason, the head does not scan the entire area of the recording track, but scans a part of each recording track.

FIG. 9 shows a conventional digital recording / reproducing apparatus. First, the recording system will be described. In FIG. 9, 4
01 is a video signal input terminal, 402 is an A / D converter that performs analog-to-digital conversion, and 403 is a block that converts a digitized video signal into a data sequence in N × M (N, M: integer) block units. A circuit 404, an orthogonal transform circuit for performing orthogonal transform such as DCT (discrete cosine transform) on the block unit data and outputting orthogonal transform coefficients, and 405, quantization of orthogonal transform coefficients to reduce the data amount of the orthogonal transform coefficients 406 is a variable-length coding circuit that performs variable-length coding on quantized data and converts it to fixed-length data, and 407 is a correction that adds a correction code used for error correction during reproduction to the fixed-length data. A code addition circuit 408 converts a fixed-length data with a correction code added thereto into data suitable for recording by NRZ modulation or the like.
Is a recording / reproducing unit for recording / reproducing modulated data.

Next, the operation of the recording system will be described. The video signal input from the input terminal 401 is A /
The data is converted by the D converter 402 into a digital video data string indicating information in pixel units. Next, the digital video data string is converted by the blocking circuit 403 into a block data string (here, a unit of 8 × 8 pixels), which is a unit to be orthogonally transformed by the orthogonal transformation circuit 404, and orthogonally transformed by the orthogonal transformation circuit 404. It is converted to a conversion coefficient. This orthogonal transform coefficient is 1 indicating a DC component in the block data sequence.
One DC coefficient and a plurality of AC coefficients indicating an AC component.

Next, the orthogonal transform coefficients in block units are quantized by a quantization circuit 405, and are sequentially output from DC coefficients to higher-order AC coefficients. The variable-length coding circuit 406 performs variable-length coding on the quantized orthogonal transform coefficients in block units to reduce the data amount by changing the bit width, and determines block-unit variable-length coded data in multiple block units. Is reduced to a predetermined data amount, and converted into a fixed-length data string. Each fixed-length data string is added with a correction code by a correction code addition circuit 407, and the modulation circuit 408
And recorded on a recording medium (here, a magnetic tape) by the recording / reproducing unit 409.

FIG. 10 shows orthogonal transform coefficients output from the orthogonal transform circuit 404. The orthogonal transform coefficient has one DC coefficient and 63 AC coefficients. The AC coefficient includes an ACL coefficient and an ACH coefficient, as described later. FIG. 11 shows track configuration data. Here, as shown in FIGS. 11A and 11B, a plurality of orthogonal transform coefficient blocks combined by one sync code are referred to as a sync block, and a fixed length unit block including a plurality of sync blocks is referred to as a fixed length block. To In one orthogonal transform coefficient block, FIG.
As shown in (a), the DC and AC coefficients quantized and variable-length coded by the quantization circuit 405 and the variable-length coding circuit 406 are arranged within a predetermined data amount. . The AC coefficient becomes an ACL coefficient when the data is within the predetermined data amount, and the AC coefficient is added to another orthogonal transform coefficient block in the fixed-length block when the data exceeds the predetermined data amount.
It is stored together with the ACL coefficient as the H coefficient. Then A
CH coefficients are distributed and arranged in fixed-length blocks as shown in the figure. Therefore, when the fixed-length block data amount is exceeded, the ACH coefficient is lost. As shown in FIG. 11C, the fixed-length block is divided into sync block units and is recorded over a plurality of recording tracks.

Next, the reproduction system shown in FIG. 9 will be described. 9, 702 is an equivalent circuit, 703 is an error correction circuit, 704 is a variable length decoding circuit, 705 is an inverse quantization circuit, 706 is an inverse orthogonal transform circuit, 706 is an inverse blocking circuit, 707 is a D / A converter. , 709 are video signal output terminals.

Next, the operation of the reproducing system will be described. The recorded compressed data reproduced by the recording / reproducing unit 409 is subjected to reproduction equalization by an equivalent circuit 702 and then subjected to error correction processing in an error correction circuit 703. The output of the error correction circuit 703 is subjected to variable length decoding processing, inverse quantization processing, and inverse orthogonal transformation processing by a variable length decoding circuit 704, an inverse quantization circuit 705, and an inverse orthogonal transformation circuit 706.
It becomes digital image data in block units of × N pixels.
This image data is converted into analog video data by a deblocking circuit 707 and a D / A converter 708,
Output from the output terminal 709. Here, as described in the recording system, since the fixed-length block extends over a plurality of recording tracks, the variable-length decoding process performed by the variable-length decoding circuit 704 is divided into each recording track. Executed after all fixed-length blocks have been reproduced.

At the time of search reproduction, only partial data of one recording track is reproduced as described above. If the divided fixed length block in the partial data, that is, all the data in the sync block is reproduced, the D of the orthogonal transform coefficient block
C and ACL coefficients can be decoded, but ACH coefficients cannot be decoded unless all data in the fixed-length block is reproduced, so that ACH coefficients cannot be decoded during search reproduction.

[0010]

As described above, in the conventional digital recording / reproducing apparatus, even when the same still image is recorded in a plurality of frames, the ACH coefficients are not decoded, so Since the image becomes an image lacking the orthogonal transform coefficient and an image lacking high frequency components,
There is a problem that image quality is significantly deteriorated.

An object of the present invention is to solve the above-mentioned problem and to prevent a high frequency component from being lost during search reproduction.

[0012]

In the image processing apparatus according to the present invention, an error correcting means for correcting an error in a fixed-length coded image signal and outputting a no-error signal when there is no error; Storage means for storing the image signal, a detection means for detecting that the image signal is a still image, and a storage means for detecting that the image signal is a still image and obtaining the no-error signal. And a selecting means for selecting the read output of.

In the computer-readable recording medium according to the present invention, a procedure for correcting an error in a fixed-length coded image signal and outputting a no-error signal when there is no error, and storing the error-corrected image signal Means for storing the image signal as a still image, and reading the output of the storage means when the image signal is detected as a still image and the no error signal is obtained. Select a procedure and record the program to perform.

[0014]

Embodiments of the present invention will be described below. FIG. 1 shows a digital recording / reproducing apparatus according to a first embodiment. In the recording system of FIG. 1, 101 is a video signal input terminal, 102 is an A / D converter,
3 is a blocking circuit, 104 is an orthogonal transformation circuit, 105 is a quantization circuit, 106 is a variable length coding circuit, 107 is a correction code addition circuit, 108 is a modulation circuit, 109 is a recording / reproducing unit, and 110 is a moving image / still image. Mode signal input terminal.

In the reproducing system, reference numeral 111 denotes an equivalent circuit;
2 is an error correction circuit, 113 is a memory, 114 is a selector, 115 is a still image detection / no error timing generation circuit, 116 is a variable length decoding circuit, 117 is an inverse quantization circuit, 118 is an inverse orthogonal transform circuit, and 119 is an inverse orthogonal transform circuit. A blocking circuit, 120 is a D / A converter, and 121 is a video signal output terminal.

Reference numeral 122 denotes a microcomputer (microcomputer) for controlling the recording system and the reproduction system according to the program, and 123 a memory as a recording medium on which the program according to the present invention is recorded. Is recorded. As the memory 123, a semiconductor memory, a magneto-optical disk, an optical disk, a magnetic medium, or the like can be used.

Next, the operation will be described with reference to the flowchart of FIG. At the time of recording, when a recording instruction is given, the analog video signal input from the video signal input terminal 101 is converted into a digital video signal by the A / D converter 102, and a blocking circuit 103.
Divides an image of one frame into blocks of M × N (M, N: integer) pixels. The orthogonal transformation circuit 104
The input block-based digital video signal is subjected to orthogonal transform such as discrete cosine transform (DCT), and orthogonal transform coefficients are output in block units (steps S1 and S1).
2). The orthogonal transform coefficient is quantized by the quantization circuit 105, and a quantized orthogonal transform coefficient is output (step S3). The variable length coding circuit 106 converts the input quantized orthogonal transform coefficients into variable length codes (Step S4).

The correction code adding circuit 107 adds a moving image / still image mode signal to the input variable length code in accordance with the moving image / still image mode signal input from the moving image / still image mode input terminal 110, A moving image mode correction code addition process or a still image mode correction code addition process is performed (step S5). The correction code-added data is transmitted to the modulation circuit 1
08 and modulated into data suitable for recording such as NRZ modulation, and then input to the recording / reproducing unit 109 and recorded on a recording medium such as a magnetic tape (step S6).

FIG. 3 is an explanatory diagram of a correction code addition data string output from the correction code addition circuit 107. In the moving image mode, as shown in FIG. 3A, a correction code is added to a signal in a unit of a fixed-length block or a sync block in a hood corresponding to an input video signal, and correction code-added data is optionally added according to an input frame. Is output. In the still image mode, FIG.
As shown in (b), S-frame (S: integer) correction code-added data is repeatedly output.

Returning to FIG. 2, at the time of reproduction, if there is a reproduction instruction, the recorded data reproduced from the recording / reproducing unit 109 is reproduced by the equivalent circuit 111, and then the error is corrected by the error correction circuit 112. Correction processing is performed (steps S7, S8). Data in which no error has occurred in sync block units due to the error correction processing is accumulated in the memory 113. At this time, a no-error block signal indicating the presence or absence of an error is input to the still image detection / no-error timing signal generation circuit 115. The still image detection / no error timing signal generation circuit 115 also receives recording data including whether or not the reproduced data is a still image (step S9). Next, it is checked whether or not the input sync block is a still image and a no-error sync block. If so, the read output of the memory 113 is input to the variable length decoding circuit 116. The output of the error correction circuit 112 is the variable length decoding circuit 11
Then, the selector 114 is controlled so as to be input to No. 6 (steps S10 and S11).

The output data of the selector 114 is subjected to variable length decoding, inverse quantization, and inverse orthogonal transformation by a variable length decoding circuit 116, an inverse quantization circuit 117, and an inverse orthogonal transformation circuit 118. It becomes digital image data in block units of N pixels, and the inverse blocking circuit 119, D / A
The data is converted into analog video data by the converter 120 and output from the output terminal 121 (step S12,
S13, S14).

FIG. 4 is a diagram for explaining the operation during still image search reproduction. As shown in FIG. 4A, only a part of one recording track is reproduced during search reproduction, but if no error occurs in a sync block in the search reproduced part, it is stored in the memory 113. FIG. 4B shows a track image in the memory 113. A sync block in which no error has occurred from each track during the search reproduction period of the S frame is accumulated in the memory 113 as shown in FIG. In step S10 of FIG. 2, n becomes a fixed-length block.
It is determined whether or not the sync blocks have been stored in the memory 113. When the sync blocks are stored, the still image detection / no error timing signal generation circuit 115 controls the selector 114 to select the output of the memory 113.

When the selector 114 selects the output of the error correction circuit 112, all the sync blocks in the fixed length block are not searched and reproduced, and the variable length decoding circuit 1
Reference numeral 16 decodes DC and ACL coefficients. When the selector 114 selects the output of the memory 113, all the sync blocks are searched and reproduced, and all of the DC, ACL, and ACH coefficients can be decoded.

The output of the still image detection / no error timing signal generation circuit 115 is reset when a moving image is searched for or reproduced, or when the image is changed to a still image, and the output of the error correction circuit 112 is selected.

FIG. 5 shows a detailed configuration of the still image detection / no error timing signal generation circuit 115. In FIG. 5, reference numeral 1001 denotes a print data input terminal;
Is a still image detection circuit, 1003 is a delay adjustment circuit, 1004
Is a no error block signal input terminal, 1005 is a position information detection circuit, 1006 is a fixed length block number detection circuit,
1007 is a write address generation circuit, 1008 is a read address generation circuit, 1009 is a reset circuit, 1010 is a no error flag memory, 1011 is a delay circuit, 1012
Is a no error block determination circuit, 1013 is an output signal generation circuit, and 1014 is an output terminal.

The still image detection circuit 1002 inputs the recording data output from the equivalent circuit 111 from the recording data input terminal 1001, and outputs the still image information included in the video compression data area in the recording data or outside the video compression data area. The still image information recorded in the still image is extracted, the reproduction signal is determined to be a moving image or a still image, and a signal for identifying the still image is output at the time of reproducing the still image. The output of the still image detection circuit 1002 is input to the delay adjustment circuit 1003, and the timing is adjusted with the output of the no error block determination circuit 1012.

On the other hand, no error block signal input terminal 1
A no-error block signal output from the error correction circuit 112 input from the position information detection circuit
, And the position information on the screen of the no error block,
The still image number which is the same number during the period of the same still image is output. Position information, which is one of the outputs of the position information detection circuit 1005, is input to a fixed-length block number detection circuit 1006, and the fixed-length block number detection circuit 1006 detects the number of a fixed-length block including a no-error block. Also, this position information is stored in the write address generation circuit 100.
7, the write address generation circuit 1007 generates a write address corresponding to the position on the screen of the no error flag memory 1010, and sets a no error flag at the address corresponding to the position on the screen of the no error flag memory 1010.

The fixed-length block number including the no-error block, which is the output of the fixed-length block number detection circuit 1006, is input to a read address generation circuit 1008.
A read address in the n no-error flag memory 1010 included in the corresponding fixed-length block is generated. The still image number, which is one of the outputs of the position information detection circuit 1005, is input to the reset circuit 1009, and when the still image number changes and the reproduced still image changes, the no-error flag memory 10
A signal for resetting all the flags in 10 is output.

The no-error flag memory 1010 sequentially reads out all the no-error flags in the same fixed-length block in accordance with the read address output from the read address generation circuit 1008, inputs the same to the delay circuit 1011 and outputs the same to the no-error block determination circuit 1012. From all the no-error flags in the fixed-length block, it is determined whether or not all data in the fixed-length block has been stored in the memory 113 as a no-error. Output signal generation circuit 101
In 3, a still image identification signal output from the delay adjustment circuit 1003 and an output from the no error block determination circuit 1012 are input, a signal for controlling the selector 114 is generated, and output from the output terminal 1014.

FIG. 6 shows a digital recording / reproducing apparatus according to the second embodiment. FIG. 6 shows only the reproduction system.
Parts corresponding to those in FIG. 1 are denoted by the same reference numerals and description thereof is omitted. Note that the recording system is configured in the same manner as in FIG. 124
Is a memory having two banks, 125 is a digital interface circuit, and 126 is an output terminal.

Next, the operation at the time of reproduction will be described. The first bank of the memory 124 updates and accumulates no-error data that has been subjected to error correction processing in the error correction circuit 112 and has been subjected to error correction. The still image detection / no error timing signal generation circuit 115 includes an equivalent circuit 111
And the no-error block signal output from the error correction circuit 112 is input. When the reproduced still images are all no-error blocks, or include the error block immediately before the reproduced still image changes, the error blocks are minimized. When the digital interface circuit 1
25, a still image detection / no error timing signal is output.

Digital interface circuit 125
, Repeatedly reads out the video compression data from the first bank of the memory 124 in response to the still image detection / no error timing signal, and outputs it from the output terminal 126. While the digital interface circuit 125 keeps repeatedly reading from the first bank of the memory 124, the error correction circuit 1
The output of 12 is stored in the second bank of the memory 124, and the first and second banks are alternately accessed by the error correction circuit 112 and the digital interface circuit 125.

[0033]

As described above, according to the present invention,
The ACH coefficient can be decoded even at the time of search reproduction of the digital recording / reproducing apparatus, and an image including a high frequency component can be reproduced, so that the image quality can be improved.
Further, as described in the second embodiment, a digital interface output with high image quality can be obtained when the playback device performs search playback, so that the dubbing time of a still image can be reduced.

[Brief description of the drawings]

FIG. 1 is a block diagram showing a digital recording / reproducing apparatus according to a first embodiment of the present invention.

FIG. 2 is a flowchart showing an operation of the digital recording / reproducing apparatus according to the first embodiment of the present invention.

FIG. 3 is a configuration diagram showing a correction code addition data string.

FIG. 4 is a configuration diagram showing a search reproduction operation.

FIG. 5 is a block diagram illustrating a still image detection / no error timing signal generation circuit.

FIG. 6 is a block diagram showing a digital recording / reproducing apparatus according to a second embodiment of the present invention.

FIG. 7 is a configuration diagram showing an image positional relationship between tracks.

FIG. 8 is a configuration diagram showing head scanning during reproduction.

FIG. 9 is a block diagram showing a conventional digital recording / reproducing apparatus.

FIG. 10 is a configuration diagram showing orthogonal transform coefficients.

FIG. 11 is a configuration diagram showing configuration data of a track.

[Explanation of symbols]

109 Recording / playback unit 112 Error correction circuit 113 Memory 114 Selector 115 Still image detection / no error timing signal generation circuit 116 Variable length decoding circuit 117 Inverse quantization circuit 118 Inverse orthogonal transformation circuit

Claims (6)

[Claims] 1. An error correction means for correcting an error in a fixed-length coded image signal and outputting a no-error signal when there is no error, a storage means for storing the error-corrected image signal, and the image signal A detection means for detecting that the image signal is a still image, and a selection means for selecting the readout output of the accumulation means when the image signal is detected as a still image and the no error signal is obtained. Processing equipment. 2. The image signal is a signal reproduced from a recording medium. At the time of search reproduction, the same still image portion of the recording medium is repeatedly reproduced, and the fixed-length code for a plurality of screens recorded on a plurality of tracks. 2. The image processing apparatus according to claim 1, wherein the selection unit selects the readout output of the storage unit when all data in the conversion processing unit has no error. 3. The image processing apparatus according to claim 1, further comprising decoding means for decoding the signal selected by said selection means. 4. A procedure for correcting an error in a fixed-length coded image signal and outputting a no-error signal when there is no error, a procedure for storing the error-corrected image signal in storage means, For detecting that the image signal is a still image, and for selecting the readout output of the storage means when the image signal is detected as a still image and the no error signal is obtained. A computer-readable recording medium on which is recorded. 5. The image signal is a signal reproduced from a recording medium. During search reproduction, the same still image portion of the recording medium is repeatedly reproduced, and the fixed length of a plurality of screens recorded on a plurality of tracks is used. 5. The computer-readable recording medium according to claim 4, wherein a read output of said storage means is selected when there is no error in all data of the encoding processing unit. 6. The computer-readable recording medium according to claim 4, wherein said step of decoding said selected signal is executed.