JPH07321866A - Demodulator - Google Patents

Abstract

PURPOSE:To provide the demodulator which can efficiently demonstrate the equalizing ability of a decision feedback type equalizer and can perform a clock pull-in operation in a short time at the same degree as conventional even when an extracted clock component is reduced by a notch frequency caused by phasing. CONSTITUTION:A/D converters 10 and 11 convert demodulated base band signals to digital signals based on input clock signals. A frame synchronization detector 26 detects frame synchronization based on the output data of a decision feedback type equalizer 13. A clock synchronizing circuit 25 extracts clock signal components from the demodulated base band signals and when inputting a signal at the time of detecting the frame synchronization with the frame synchronization detector 26, a clock signal phase-locked with the extracted clock component is generated but when inputting a signal at the time of detecting no frame synchronization, a clock signal at the frequency corresponding to the extracted clock signal component is generated.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a demodulator, and more particularly to a demodulator having a decision feedback equalizer used in a digital radio communication system.

[0002]

2. Description of the Related Art In a digital radio communication system, when the amplitude or phase of each frequency of a received signal fluctuates due to frequency selective fading generated in a propagation path, in order to remove or reduce the influence by the receiving device, it is a conventional practice. It is known to use a decision feedback equalizer (for example, Japanese Patent Laid-Open No. 4-181802).

FIG. 3 shows a block diagram of an example of a conventional demodulation device in which the decision feedback equalizer and a demodulator are combined. In FIG. 3, the circuit provided on the input side of the decision feedback equalizer 13 is a demodulator, and this demodulator itself is already known in the literature or the like (for example, "Digital Microwave Communication", p. 111-p. 114, supervised by Moriji Kuwahara, Planning Center Co., Ltd.).

To explain the operation of this conventional demodulation device, an intermediate frequency (IF) band digital modulated wave (eg, QPSK, QAM) input to the input terminal IN is described.
Is divided into two by the distributor 1, one of which is input to the multiplier 2 and multiplied by the reproduced carrier from the reproduced carrier generator 4, and the other is input to the multiplier 3 and reproduced from the reproduced carrier generator 4. Is multiplied by the reproduced carrier whose phase is shifted by 90 ° by the π / 2 phase shifter 5.

The output signals of the multipliers 2 and 3 are demodulated baseband signals a and b by removing unnecessary high frequency components by the low-pass filters 6 and 7, respectively, and are amplified to appropriate amplitudes by the amplifiers 8 and 9. The demodulated baseband signals extracted from the amplifiers 8 and 9 are clock synchronization circuits (C
A clock component is extracted by an LK synchronization circuit) 12 and is further converted into a sampling clock synchronized with this clock component, while being supplied to A / D converters 10 and 11.

The A / D converters 10 and 11 sample the input demodulated baseband signal based on the sampling clocks CLKP and CLKQ from the CLK synchronizing circuit 12,
Output a digital signal. This digital signal is supplied to the decision feedback equalizer 13, where the waveform distortion due to fading is equalized and demodulated data DATAP, DATA.
It is output as Q.

FIG. 4 shows a block diagram of an example of the CLK synchronizing circuit 12 described above. In the figure, input terminals PIN,
The output demodulated baseband signals of the amplifiers 8 and 9 are respectively supplied to the non-linear circuits 14a and 14b via QIN, and the non-linear characteristics are given to the post-band filters 1 respectively.
The clock component is extracted by passing through 5.
This clock component is amplified by the amplifier 16 and input to the phase comparator 17 and the detection circuit 21, respectively.

The phase comparator 17 compares the phase of the extracted clock component with the output signal of the voltage controlled oscillator (VCO) 19 and inputs a phase error signal of a level corresponding to the phase difference between them to one input of the switcher 18. Input to the terminal. The switching device 18 receives the output signal of the level comparator 23, which will be described later, from the phase comparator 1
One of the output phase error signal of 7 and the free-run control voltage from the free-run control voltage generator 20 is selected to select the VCO.
It is input to 19 as a control voltage.

On the other hand, the above-mentioned detection circuit 21 level-detects the above-mentioned extracted clock component, and inputs the detection signal thus obtained to the level comparator 23. The level comparator 23 compares the level of this detection signal with a predetermined threshold value from the threshold value generator 22, and outputs a high level signal when the detection signal is at a high level above this threshold value. When it is less than the threshold value, a low level signal is output.

When the input signal of the demodulator is at a normal level, the output detection signal of the detection circuit 21 is at a level higher than the above threshold value. At this time, therefore, the level comparator 23 outputs a high level signal. The switch 1
8 is controlled to select the output phase error signal of the phase comparator 17. The output oscillation frequency of the VCO 19 is variably controlled according to the input phase error signal. Therefore, when the input signal of the demodulator is at a normal level, the phase comparator 1
7, a sampling clock that is phase-synchronized with the extracted clock component is taken out from the VCO 19 by a feedback loop composed of the switch 18 and the VCO 19, and the A / D converters 10 and 11 shown in FIG. 3 are output via the output terminals CLKP and CLKQ. Is output to.

On the other hand, when the input signal of the demodulator is extremely small and has almost no noise, or when there is no signal, the output detection signal level of the detection circuit 21 becomes less than the output threshold value of the threshold value generator 22. At this time, the level comparator 23 outputs a low level signal to cause the switch 18 to select the output free-run control voltage of the free-run control voltage generation circuit 20. That is, when the input signal of the demodulator is no input or noise, it means that there is no input or the waveform cannot be demodulated and the necessary clock component cannot be extracted. 20
The output free-run control voltage is selected and input to the VCO 19 as a control voltage.

As a result, the VCO 19 oscillates and outputs a signal having a frequency corresponding to the frequency of the clock component to be extracted, and outputs the sampling clock to the A / D converters 10 and 11 shown in FIG. 3 via the output terminals CLKP and CLKQ. Output as. If a normal modulated wave is input to the demodulator from this state, the output signal of the level comparator 23 described above becomes a high level, so that the switch 18 selects the output phase error signal of the phase comparator 17. To VCO
The output oscillation frequency of 19 is variably controlled by this phase error signal.

As a result, synchronous pull-in is performed to the clock frequency of the input modulated wave, and the output signal of the VCO 19 at this time is used as the sampling clock in the A / D converter 1.
Supplying 0 and 11 enables normal demodulation. Here, the free run control voltage generating circuit 20
The output free-run control voltage of the
Since the output phase error signal is substantially equal to the output phase error signal, the synchronous pull-in can be performed in a short time when the switch 18 switches and selects the free-run control voltage from the phase error signal to the above phase error signal. become.

[0014]

[0007] However, in the above conventional apparatus, when ± notch frequency from the carrier frequency _{f 0/2 [Hz] (} f 0 is the clock frequency) occurring away by fading, The level of the clock component extracted from the demodulated baseband signal is lowered, and as a result, in the phase comparator 17, the output signal of the amplifier 16 and the VCO
Even when the phase comparison operation with the output signal of 19 is possible, the output detection signal level of the detection circuit 21 becomes less than the threshold value from the threshold value generator 22, and the demodulator input signal is not input. Or, it is determined as noise, and the switch 18 selects the output free-run control voltage of the free-run control voltage generation circuit 20, causing a malfunction, resulting in loss of clock synchronization. Therefore, in this case, there is a problem in that fading cannot be equalized due to the above-mentioned malfunction, although there is a margin for equalization by the decision feedback equalizer 13.

The above malfunction can be solved by setting the predetermined threshold level lower than usual. However, in this case, the output detection signal level of the detection circuit 21 does not become lower than the threshold value even when the input signal of the demodulator is no input or noise. Therefore, even in such a case, the VCO 19 has the free-run control voltage. The output free-run control voltage of the generation circuit 20 is not supplied,
There is a problem that the synchronization pull-in of the clock is delayed due to noise or the sneak of the output signal of the VCO 19 to the input of the phase comparator 17.

The present invention has been made in view of the above points,
Even if the notch frequency due to fading lowers the extracted clock component, a demodulator that can fully demonstrate the equalization ability of the decision feedback equalizer and can perform the clock pull-in operation in the same short time as the conventional one. The purpose is to provide.

[0017]

In order to achieve the above-mentioned object, the present invention is a demodulation means for separately multiplying an input digital modulated wave with two reproduced carrier waves each having a phase difference of 90 ° to obtain a demodulated baseband signal. And A / D conversion means for converting the demodulated baseband signal extracted from the demodulation means into a digital signal based on the input clock signal,
Frame synchronization for inputting the output digital signal of the A / D conversion means and equalizing the waveform distortion due to fading and receiving the output data of the decision feedback equalizer as an input signal and detecting frame synchronization A clock signal component is extracted from the detector and the demodulated baseband signal, and when a signal for frame synchronization detection is input from the frame synchronization detector, a clock signal that is phase-synchronized with the extracted clock signal component is generated. Further, when the signal at the time of non-detection of frame synchronization is input, the clock synchronization circuit generates a clock signal having a frequency corresponding to the extracted clock signal component.

Further, the clock synchronization circuit includes an extraction circuit for extracting a clock signal component from the demodulated baseband signal output from the demodulation means, a detection circuit for detecting the level of the extracted clock signal component, and an output detection signal of the detection circuit. Level comparison means for comparing levels with a predetermined threshold value to output a signal having a different logic value at least during normal demodulation and when no signal is input, a voltage controlled oscillator for outputting a clock signal, and a voltage controlled oscillator Of an output clock signal and an extracted clock signal component to generate and output a phase error signal, a fixed voltage generating circuit for generating a fixed voltage, an output signal of the level comparing means and a frame synchronization detector. A logic circuit that receives an output signal and performs a predetermined logical operation and outputs the result, and a phase error signal and a fixed voltage It is possible to adopt a configuration in which a switch that selects one of them is supplied as a control voltage to the voltage controlled oscillator and a clock that is phase-synchronized with the extracted clock signal component when the signal for frame synchronization detection is input from the frame synchronization detector. It is preferable and desirable to generate a signal and generate a clock signal having a frequency corresponding to the extracted clock signal component when the frame synchronization detector receives a signal when the frame synchronization is not detected.

[0019]

According to the present invention, the clock synchronization circuit generates a clock signal phase-synchronized with the extracted clock signal component when the signal for frame synchronization detection is input from the frame synchronization detector, and the frame synchronization detector does not detect the frame synchronization. When the time signal is input, a clock signal with a frequency equivalent to the extracted clock signal component is generated,
Even if the level of the extracted clock signal component decreases due to fading, if the frame synchronization detector can achieve frame synchronization, it is determined that the data is demodulated normally, and the clock signal phase-synchronized with the extracted clock signal component Can be generated. That is, as long as the data is normally demodulated, the clock signal synchronized with the extracted clock signal component can be generated by the clock synchronization circuit.

[0020]

EXAMPLES Next, examples of the present invention will be described. 1 is a block diagram of an embodiment of the present invention, and FIG. 2 is a block diagram of a clock synchronization circuit in the block diagram of FIG. Figure 1
Further, in FIG. 2, the same components as those in FIGS. 3 and 4 are designated by the same reference numerals, and the description thereof will be omitted. As shown in FIG. 1, this embodiment is provided with a frame synchronization detector 26 for detecting whether the output data of the decision feedback equalizer 13 is normally demodulated, and a clock synchronization circuit having a frame synchronization information input terminal FIN. The feature is that 25 is provided.

As shown in FIG. 2, the clock synchronization circuit 25 has a 2-input OR circuit 28 as a logic circuit, as compared with the conventional clock synchronization circuit 12 of FIG. The logical sum circuit 28 is configured to take the logical sum of the frame synchronization information from the input terminal FIN and the output comparison result of the level comparator 23 and supply the obtained output to the switch 18 as a switching control signal.

The distributor 1 to the amplifiers 8 and 9 shown in FIG.
The circuit portion up to the above constitutes the demodulation means, and the two A / D converters 10 and 11 constitute the A / D conversion means. Furthermore, the nonlinear circuits 14a and 14 of FIG.
b, the bandpass filter 15 and the amplifier 16 compose the extraction circuit, and the threshold value generator 22 and the level comparator 23 compose the level comparison means.

Next, the operation of this embodiment will be described.
The frame synchronization detector 26 shown in FIG. 1 receives the output data of the decision feedback equalizer 13 as an input signal, and the demodulator operates normally. As a result, the decision feedback equalizer 1
When the output data of 3 is normally obtained, a high-level detection signal (frame synchronization information) after establishing frame synchronization
Is output. On the other hand, when the output data of the decision feedback equalizer 13 is not normally obtained, such as when there is no signal input to the input terminal IN (no signal), the frame synchronization detector 26 cannot detect the frame synchronization and the low level is detected. The detection signal (frame synchronization information) of is output.

Therefore, assuming that there is no signal input, low-level frame synchronization information is taken out from the frame synchronization detector 26 and the 2-input logic is input through the input terminal FIN of the clock synchronization circuit 25 shown in FIG. It is input to one input terminal of the summing circuit 28. At this time, as described with reference to FIG. 4, the low-level comparison result is taken out from the level comparator 23 of FIG. 2 and input to the other input terminal of the OR circuit 28.

Therefore, at the time of no signal input, a low-level signal is taken out from the OR circuit 28 and supplied to the switch 18, so that the switch 18 outputs the free-run control voltage of the free-run control voltage generation circuit 20. Select VCO1
9 is applied as a control voltage. As a result, as described with reference to FIG. 4, the VCO 19 outputs a signal corresponding to the clock frequency for speeding up the clock pull-in operation and supplies it to the phase comparator 17, and at the same time, the two output terminals CLK.
Output to P and CLKQ respectively.

In this state, assuming that a signal of a normal level is input to the input terminal IN, the detection circuit 21
Since the output detection signal of is higher than the output threshold of the threshold generator 22, the level comparator 23
Since a high level signal is output from the OR circuit 2,
The output signal of 8 becomes high level. As a result, the switch 18 selects the output phase error signal of the phase comparator 17,
It is applied as a control voltage to CO 19.

As a result, since the output oscillation frequency of the VCO 19 is variably controlled according to the input phase error signal as described with reference to FIG. 4, the phase comparator 17 shown in FIG.
A sampling clock phase-locked with the extracted clock component is taken out from the VCO 19 by a loop of a feedback loop composed of the switch 18 and the VCO 19, and is output to the output terminals CLKP and CLKQ, and from this, the A / D converter 10 shown in FIG. And 11 are output.

As a result, in the case of normal demodulation,
The output frame synchronization information of the frame synchronization detector 26 shown in FIG. 1 changes from the low level until then to the high level. Therefore, during normal demodulation, both 2-input signals of the 2-input OR circuit 28 are at high level, and the output signal is also at high level.

[0029] In this state, when ± notch frequency from the carrier frequency _{f 0/2 [Hz] (} f 0 is the clock frequency) occurring away by fading, a clock component extracted from the demodulated baseband signal Of the detection circuit 2 in the phase comparator 17 as a result.
Even if the output detection signal level of 1 becomes less than the threshold value from the threshold value generator 22 and the demodulator input signal is judged to be no input or noise as in the conventional case, the amplifier 16 in the present embodiment. Of the output signal of the VCO 19 and the output signal of the VCO 19 are possible, and when the equalization operation of the decision feedback equalizer 13 has a margin, the frame synchronization detector 26 continuously outputs the high level frame synchronization information. To be done.

Therefore, in the case of the present embodiment, even if the output signal of the level comparator 23 becomes low level, the output frame synchronization detection information of the frame synchronization detector 26 is at high level, so that logic The output signal of the summing circuit 28 is at a high level, and as a result, the switch 18 continues to select the output phase error signal of the phase comparator 17 to select VCO1.
8 is input, the clock synchronization state can be continuously maintained.

In this embodiment, the switch 18 selects the output free-run control voltage of the free-run control voltage generation circuit 20 and outputs the control voltage to the VCO 19 when the synchronization is lost due to no signal. , And outputs a signal corresponding to the clock frequency, it is possible to obtain characteristics equivalent to those of the conventional clock pull-in operation.

The present invention is not limited to the above embodiment, and for example, the detection circuit 21 in the clock synchronization circuit 25 outputs the input demodulation baseband signals of the two input terminals PIN and QIN to the non-linear circuits 14a and 14a, respectively. 14b
Although the level of the sum signal of the signals obtained through the above is detected, the level of only one of the input demodulated baseband signals of the two input terminals PIN and QIN may be detected. Further, depending on the logic of the output of the level comparator 23 and the logic of the output of the frame synchronization detector 26, it goes without saying that the logical sum circuit 28 may be replaced with a logical circuit having another configuration.

[0033]

As described above, according to the present invention,
When the frame synchronization detector determines that the data is normally demodulated, a clock signal phase-synchronized with the extracted clock signal component is generated, so that the notch frequency is ± f ₀ from the carrier frequency due to fading.
Since it occurs at a distance of ½ [Hz] (f ₀ is a clock frequency), even when the level of the clock component extracted from the demodulated baseband signal is lowered, it is determined that the data is normally demodulated. A clock signal phase-locked with the extracted clock signal component is output, and as a result, loss of synchronization can be prevented and waveform distortion due to fading can be equalized by the decision feedback equalizer.

Further, when the signal is not normally demodulated such as when no signal is input, the clock synchronizing circuit can generate almost the same frequency as the extracted clock signal component, so that the same clock pull-in characteristic as the conventional one should be secured. You can

[Brief description of drawings]

FIG. 1 is a block diagram of an embodiment of the present invention.

2 is a block diagram of a clock synchronization circuit in FIG. 1. FIG.

FIG. 3 is a block diagram of a conventional example.

4 is a block diagram of a clock synchronization circuit in FIG.

[Explanation of symbols]

 1 Distributor 2, 3 Multiplier 4 Regenerated carrier wave generator 5 90 ° phase shifter 10, 11 A / D converter 13 Decision feedback equalizer 14a, 14b Non-linear circuit 17 Phase comparator 18 Switcher 19 Voltage controlled oscillator (VCO) 20 Free-run control voltage generation circuit 21 Detection circuit 22 Threshold value generator 23 Level comparator 25 Clock synchronization circuit 26 Frame synchronization detector 28 2-input OR circuit

─────────────────────────────────────────────────── ─── Continuation of the front page (51) Int.Cl. ⁶ Identification code Internal reference number FI Technical indication H04L 27/01

Claims (2)

[Claims] 1. A demodulation means for separately multiplying an input digital modulated wave by two reproduced carrier waves each having a phase difference of 90 °, and a demodulation baseband signal extracted by the demodulation means. A / D conversion means for converting into a digital signal based on an input clock signal, a decision feedback equalizer for equalizing waveform distortion due to fading, to which the output digital signal of the A / D conversion means is inputted, and the decision A frame synchronization detector that receives output data of a feedback equalizer as an input signal and detects frame synchronization, and a clock signal component is extracted from the demodulated baseband signal. When input, a clock signal phase-locked with the extracted clock signal component is generated and output to the A / D conversion means, And a clock synchronization circuit for generating a clock signal having a frequency corresponding to the extracted clock signal component and outputting it to the A / D conversion means when a signal when the frame synchronization is not detected is input from the home sync detector. Characteristic demodulator. 2. The clock synchronization circuit includes an extraction circuit for extracting a clock signal component from the demodulated baseband signal output from the demodulation means, a detection circuit for detecting the level of the clock signal component from the extraction circuit, and the detection circuit. Level comparison means for comparing the output detection signal of the circuit with a predetermined threshold value to output a signal having a different logical value at least during normal demodulation and when no signal is input, and voltage control for outputting a clock signal. An oscillator, a phase comparator for phase-comparing an output clock signal of the voltage-controlled oscillator and a clock signal component from the extraction circuit to generate and output a phase error signal, and when supplied as a control voltage to the voltage-controlled oscillator A fixed voltage that causes the voltage controlled oscillator to oscillate and output a signal having a frequency substantially equal to the clock signal component from the extraction circuit. A voltage generation circuit, a logic circuit which receives the output signal of the level comparison means and the output signal of the frame synchronization detector, performs a predetermined logical operation, and outputs the logic circuit, and an output signal of the logic circuit from the phase comparator. Of the phase error signal and a fixed voltage from the fixed voltage generation circuit, and a switch for supplying the voltage controlled oscillator as a control voltage, and a signal at the time of frame synchronization detection from the frame synchronization detector. The switching device selects the phase error signal when input, and the switching device selects the fixed voltage when a signal when the frame synchronization is not detected is input from the frame synchronization detector. The demodulator according to Item 1.