JPH0731624Y2 - Delay circuit - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention will be described in the following order.

A Industrial field B Outline of the device C Conventional technology (Figs. 8 to 11) D Problems to be solved by the device (Figs. 8 to 11) E Means for solving problems (FIGS. 1 and 4) F Action (FIGS. 1 and 4) G Embodiment (FIGS. 1 to 7) H Effect of the invention A Industrial field of application The present invention relates to a delay circuit, for example, It is suitable for application to a magnetic disk device.

Overview The invention in B devised, the first charging and discharging the capacitor C _A is connected between the collector of the first transistor Q ₄ and the emitter, and a first emitter and a first transistor Q ₄ of the charge and discharge the capacitor C _A
The first constant current circuit Q _{5 to} Q ₈ , 22, 20,
A first charging / discharging circuit formed by connecting R _EXT , a second transistor Q ₁₀ having a base connected to the first connection point, and a third transistor Q ₁₀ having a base connected to the reference voltage V _R. First of differential amplifier circuit configuration formed with transistor Q ₁₁
The second charge / discharge capacitor C _B is connected between the collector of the fourth transistor Q ₂₀ whose base is connected to the collector of the second transistor Q ₁₀ and the emitter, and the fourth transistor Q 10. _A second constant current circuit at the second connection point between the ₂₀ emitter and the second charging / discharging capacitor C _B.
A second charge / discharge circuit formed by connecting Q _{5 to} Q ₈ , 22, 20, and R _EXT , a fifth transistor Q ₂₁ whose base is connected to a second connection point, and a base being a reference An input pulse signal supplied to the base of the first transistor Q ₄ and a second voltage comparison circuit having a differential amplifier circuit configuration formed by a sixth transistor Q ₂₂ connected to the voltage V _R. Delay the fall of _SWD using the discharge time of the first charge / discharge capacitor C _A , while delaying the rise of the input pulse signal _SWD using the discharge time of the second charge / discharge capacitor C _B By doing so, the rising and falling edges of the input pulse signal can be accurately delayed, and thus a highly accurate delay time can be obtained with a simple configuration.

C. Related Art Conventionally, in this type of delay circuit, there is a delay circuit configured to obtain a desired delay time by using a time constant circuit of capacitors and resistors or two mono-multi circuits (Japanese Patent Publication No. Sho 57-690). Issue).

That is, as shown in FIG. 8, in the delay circuit 1 using the time constant circuit of the capacitor and the resistance, the signal level of the output signal decreases as the delay time increases, so that the delay circuit of the same configuration having a short delay time is used. D ₁ , D ₂ , D ₃ , ...
, D _n are connected in series to obtain a delay circuit 1 having a long delay time as a whole.

Therefore, as shown in FIG. 9, in the delay circuit D ₁ of the first stage, the time constant circuit of the resistor R ₁ and the capacitor C ₁ receives the input pulse signal S _P1 (FIG. 9 (A)) and compares them. Through the circuit COM ₁ the reference voltage V ₁ and the terminal voltage V of the capacitor C ₁
Comparison output S _D1 with _C1 (Fig. 9 (B)) (Fig. 9 (C))
Thus, the pulse signal S _D1 delayed by the minute delay time τ _D1 is output to the subsequent delay circuit D ₂ .

Similarly, the delay circuit D ₂ receives the pulse signal S _D1 at the time constant circuit of the resistor R ₂ and the capacitor C ₂ , and outputs the comparison output between the reference power supply V ₂ and the terminal voltage of the capacitor C ₂ via the comparison circuit COM _2. Pulse signal delayed by a minute delay time τ _D2
S _D2 (FIG. 9 (D)) is output to the subsequent delay circuit D ₃ .

Thus, in the delay circuit 1, the pulse signals S _D1 and S ₁ whose delay time is increased with respect to the input pulse signal S _P1 are sequentially _added .
_{, D D2} , S _D3 , ..., S _Dn (FIG. 9 (E)) are obtained, and as a result, the output pulse signal S _Dn having the delay time τ _D is obtained as a whole.

On the other hand, as shown in FIGS. 10 and 11, in the delay circuit 5 using the two mono-multi circuits 3 and 4,
The input pulse signal S _P1 (FIG. 11 (A)) is given to the first mono-multi circuit 3 and also given to the second mono-multi circuit 4 via the inverting amplifier circuit 6.

The mono-multi circuits 3 and 4 respectively delay signals S ₀₃ and T ₃ whose signal level falls after a predetermined time T _DA and T _DB elapses after the signal level rises due to the timing of the rising edge of the input pulse signal. _S04 (FIGS. 11 (B) and (C)) is formed.

The AND circuit 7 receives the inverted output signal S _{I03 of} the first mono-multi circuit 3 (FIG. 11 (D)) and the output signal S ₀₄ of the second mono-multi circuit 4, and thereby the inverted output signal S _I03 . After the signal level rises at the rising of the signal level,
An output pulse signal S _D0 (FIG. 11 (E)) having a delay time τ _D in which the signal level falls at the falling edge of the output signal S ₀₄ is obtained.

D Problem to be solved by the invention However, in this type of delay circuit, there are problems that the entire configuration becomes complicated and it is difficult to obtain a highly accurate delay time.

That is, in the delay circuit 1 using the time constant circuit of the capacitor and the resistor, the delay delay circuit short same configuration of the time _{D 1, D 2, D 3} , ......, the configuration of the entire amount that connected in series D _n complex become.

Further, in the delay circuit 1, the delay time cannot be adjusted. Therefore, if the time constant circuit varies, the accuracy of the delay time deteriorates accordingly.

On the other hand, in the delay circuit 5 using the mono-multi circuits 3 and 4, since the two mono-multi circuits 3 and 4 are used, the entire configuration becomes complicated.

Furthermore, if the delay time further varies between the two mono-multi circuits 3 and 4, the accuracy of the delay time deteriorates accordingly.

The present invention has been made in consideration of the above points, and it is an object of the present invention to propose a delay circuit having a simple configuration and capable of obtaining a highly accurate delay time.

E Means for Solving the Problems In order to solve the above problems, in the present invention, the first charging / discharging capacitor C _A is connected between the collector and the emitter of the first transistor Q ₄ and the first transistor Q ₄ is connected. The first constant current circuit Q _{5 to} Q ₈ , 22, 20, R _EXT formed by connecting the first connection point between the emitter of Q ₄ and the first charging / discharging capacitor C _A Charge / discharge circuit and base is first
A first voltage comparison circuit having a differential amplifier circuit configuration formed by a second transistor Q ₁₀ connected to the connection point of and a third transistor Q ₁₁ whose base is connected to the reference voltage V _R , The second charge / discharge capacitor C _B is connected between the collector and the emitter of the fourth transistor Q ₂₀ whose base is connected to the collector of the second transistor Q ₁₀ , and the emitter and the second of the fourth transistor Q ₂₀ are connected. Charge / discharge capacitor C _B
The second constant current circuit to a second connection point between Q ₅ ~Q _8, 22,20,
A second charge / discharge circuit formed by connecting R _EXT , a fifth transistor Q ₂₁ having a base connected to the second connection point, and a sixth transistor Q ₂₁ having a base connected to the reference voltage V _R. The second of the differential amplifier circuit configuration formed with the transistor Q ₂₂
Of the input pulse signal _SWD supplied to the base of the first transistor Q ₄
While the discharge time of the charging / discharging capacitor C _A is used to delay, the rising time of the input pulse signal _SWD is delayed using the discharging time of the second charging / discharging capacitor C _B.

F action The delay of the input pulse signal _SWD supplied to the base of the first transistor Q ₄ is delayed by using the discharge time of the first charge / discharge capacitor C _A , while the second charge / discharge capacitor C _B is delayed. Since the rising time of the input pulse signal _SWD is delayed by using the discharge time of, the rising and falling edges of the input pulse signal _SWD can be accurately delayed.

G Embodiment Hereinafter, an embodiment of the present invention will be described in detail with reference to the drawings.

In Figure 2, 10 as a whole shows a signal processing circuit of the magnetic disk apparatus, for demodulating a recorded signal from a reproduction signal S _PB obtained through the magnetic head.

That is, as shown in FIG. 3, in the signal processing circuit 10, the reproduction signal S _PB (FIG. 3 (A)) in which the signal level rises to the positive side and the negative side at a predetermined timing is provided to the differentiating circuit 11 and the window circuit 12. Give to.

As a result, after the signal level rises or falls from 0 level via the differentiating circuit 11, a predetermined time T _{D is} delayed from the time t1 when the signal level of the reproduction signal S _PB rises or falls to the maximum value or the minimum value. Then, the differential signal S _DV in which the signal level is inverted across the 0 level (FIG. 3 (B))
Is output.

On the other hand, the window circuit 12 has a comparison circuit, and the reproduction signal S _PB and the predetermined reference voltages V ₁ and V 2 are _supplied via the comparison circuit.
By obtaining a _second comparison result, the reproduction signal S and the rising or falling Sagariru signal level from the predetermined signal level V ₁ or V ₂ of the _PB, window signal S _WD whose signal level rises
(FIG. 3 (C)) is output.

Delay circuit 13 receives the window signal S _WD, the window signal S _WD to be delayed by the delay time T _D generated by the differential circuit 11 outputs, thereby window signal S timing of the differential signal S _DV timing _WD To match.

That is, as shown in FIG. 4, the delay circuit 13, the whole is an integrated circuit, each of the transistors Q ₁ and Q ₂ providing an inverted signal S _IWD of the window signal S _WD and the window signal S _WD.

Transistors Q ₁ and Q ₂ connect a constant current source composed of a reference power source 20 of voltage V _B , a transistor Q ₃ and a resistor R _E1 to an emitter so as to form a buffer circuit having a differential amplifier circuit configuration as a whole. Has been done.

As shown in FIG. 5, the transistor Q ₄ is a transistor
Connected to the output resistor R _C1 of Q _2, thereby via the buffer circuit of the transistors Q ₁ and Q ₂ in the transistor Q _4, adapted window signal S _WD (FIG. 5 (A)) is input ing.

Further, the transistor Q ₄ connects the charge / discharge capacitor C _A to the emitter and the collector and connects the collector to the power line.
It is designed to be connected to V _CC , which allows window signal S
_When the signal level of _WD rises, it is turned on, and the inter-terminal voltage V _CA of the charge / discharge capacitor C _A is switched to the base-emitter voltage V _BE of the transistor Q ₄ .

Accordance connexion, the signal level rises period of the window signal S _WD is, the voltage of the power supply lines at the V _CC, the voltage of the formula _{V A = V CC -V BE ......} (1), the transistor Q ₄ emitter The voltage V _A rises.

Further, the transistor Q ₄ is adapted to connect the emitter to the transistor Q ₅ , and the transistor Q ₅ is adapted to connect the base and the emitter in common with the transistors Q ₆ and Q ₇ to the reference power supply 22 and the transistor Q ₈ , respectively. ing.

Transistor Q ₈ has a common reference voltage source 20 with transistor Q _3.
The base is connected to the external resistor R
_EXT is connected to the emitter, thereby constituting a constant current source as a whole, and by adjusting the resistance value of the external resistor R _EXT , the current value of the constant current source can be adjusted. .

That is, in the transistor Q ₈ , the voltage between the base and the emitter of the transistor Q ₈ is V _BE, and the following equation (the same reference numeral as the resistance is used to represent the resistance value), Current I _EXT drives transistors Q ₅ , Q ₆ and Q ₇ .

Since the base voltages of the transistors Q ₅ , Q ₆ and Q ₇ are held at the reference voltage, the currents I _A , I _B and I _C flowing through the transistors Q ₅ , Q ₆ and Q ₇ are equal to each other. Held in a value, The current I _A flows out from the transistor Q ₄ and the charge / discharge capacitor C _A.

Accordance connexion, after under standing the signal level of the window signal S _WD is ivy, a time of the fall at the t = 0, the following equation _{ΔQ = C A · ΔV CA =} I A · t ...... (4) The charge accumulated in the charging / discharging capacitor C _A changes by the charge ΔQ, and the emitter voltage V _A of the transistor Q ₄ becomes
From the expressions (1) and (4), the following expression Changes to the voltage of.

Thus, in the emitter voltage V _A of the transistor Q ₄ (FIG. 5 (B)), the signal level of the window signal S _WD rises, after One rising to the voltage V _CC -V _BE, of the window signal S _WD When the signal level falls, it gradually falls to the voltage represented by the equation (5).

In contrast, the transistor Q ₁₀ constitute a differential amplifier circuit together with the transistor Q _11, reference power source 20 to the emitters, as well as connecting a constant current source formed by transistors Q ₁₂ and resistors R _E2, base transistor Emitter voltage of Q ₄ V _A
It is designed to receive.

Further, the base of the transistor Q ₁₁ is connected to the collector of the transistor Q ₇ and also to the emitter of the transistor Q ₁₅ , so that the base voltage of the transistor Q ₁₁ is maintained at the voltage determined by the base voltage of the transistor Q _15. It is designed to be.

That is, the base of the transistor Q ₁₅ is the reference power source 20,
Is connected to a constant current source formed by transistors Q ₁₈ and resistors R _B5, adapted to be connected to the power supply line V _CC via the resistor R _B6, thereby the resistance R _B6, the following equation Current I _D of The base voltage of the transistor Q ₁₅ is held at the voltage V _B6 of.

Therefore, at the base voltage V _R of the transistor Q ₁₁ ,
Let V _BE be the voltage across the base emitter of the transistor Q ₁₅ , and Held at the voltage of.

Furthermore, in the differential amplifier circuit of the transistors Q ₁₀ and Q ₁₁ , a collector resistor R _C4 is provided on the transistor Q ₁₀ side, which allows the emitter voltage of the transistor Q _{4 to be} reduced.
V _A is a period which rises than the base voltage V _R of the transistor Q _11, the collector voltage V _C4 of the transistor Q ₁₀ (5
The figure (C)) is designed to fall.

Therefore, in the collector voltage V _C4 , when the voltage level of the window signal _SWD falls after the voltage level falls at the timing when the window signal _SWD signal level rises, the emitter voltage V _A of the transistor Q ₄ changes. Transistor Q
_The voltage rises with a delay of t _A until it falls below the base voltage V _{R of 11} , and this causes the window signal _SWD to rise.
The fall timing of is delayed by time t _A.

That is, the emitter voltage V _A of the transistor Q ₄ gradually decreases at the voltage expressed by the formula (5), while the base voltage V _R of the transistor Q ₁₁ is maintained at the voltage expressed by the formula (8). From the fact that And solve for time t, Is obtained, and by substituting equation (3) into this, the following equation Delay time can be obtained.

Here, in the equation (11), it can be seen that the delay time t _A is determined by the charging / discharging capacitor C _A , the external resistance R _EXT, and the resistances R _B5 and R _B6 .

Therefore, the desired delay time can be obtained with high accuracy by adjusting the resistance value of the external resistor R _EXT as necessary.

Thus, as shown in FIG. 1, the transistors Q ₅ and Q ₈ in this embodiment, the external resistor R _EXT and the reference power source 20 and 22
Inter-terminal voltage of the charge and discharge the capacitor C is connected with _A the charging and discharging capacitor C _A to emitter of the transistor Q ₄ V
_A discharge current source 25 for lowering _CA is constructed.

On the other hand, the transistor Q ₄ gives a charging current to the charging / discharging capacitor C _A at the rising timing of the window signal _SWD , so that the charging / discharging capacitor C _A , the transistors Q ₅ , Q ₈ ,
Q ₁₀ , Q ₁₁ and Q ₁₂ , resistors R _E2 , R _EXT and R _C4 , reference power supply 20
And 22, a first transistor circuit for delaying the fall timing of the window signal _SWD by a time t _A
Make up 26.

Further transistors Q ₇ , Q ₁₀ , Q ₁₁ , Q ₁₂ , Q ₁₅ and Q ₁₈ ,
The resistors R _B5 , R _B6 and R _C4 and the reference power supplies 20 and 22 generate a window signal whose falling timing is delayed by the time t _A ,
An inverting amplifier circuit 27 for outputting to the subsequent transistor Q ₂₀ is constructed.

Transistor Q ₂₀ is similar to transistor Q _{4 in} that it includes transistors Q ₆ and Q _{8 as well as} an external resistor along with charge / discharge capacitor C _B.
A constant current circuit 29 of current I _B composed of R _EXT and the reference power supplies 20 and 22 is connected to the emitter, which causes the transistor Q ₂₀
The emitter voltage V _B (Fig. 5 (D)) of the transistor Q
After the collector voltage V _C4 of the ₁₀ was launched at the timing of rises, the collector voltage V _C4 of the transistor Q ₁₀ is to move down gradually Standing rises.

In contrast, transistors Q ₂₁ and Q ₂₂ are
Similar to Q ₁₀ and Q _11, it has a constant current source composed of a transistor Q ₂₃ , a resistor R _E3 , and a reference power source 20, and constitutes a differential amplifier circuit as a whole.

Furthermore, at the base, like the transistors Q ₁₀ and Q ₁₁ ,
They are designed to receive the emitter voltage V _B of the transistor Q ₂₀ and the emitter voltage V _R of the transistor Q ₁₅ , respectively.
An output signal of opposite polarity is output via _C7 and R _CB .

Therefore, while an output signal whose falling edge is delayed with respect to the window signal _SWD is obtained through the transistor Q ₁₀ , the inverted signal of the output signal is input to the transistor circuit of the same circuit configuration, through Q _21, can be obtained with respect to the window signal S _WD, the output signal rise is delayed by a predetermined time T _B S _DL (FIG. 3 (C)) and Figure 5 the (E)).

Thus, in this embodiment, transistors Q ₇ and
Q ₈ , external resistance R _EXT and reference power supplies 20 and 22 are transistors
The emitter of Q ₂₀ is connected with the charge-discharge capacitor C _B to constitute the discharge current source 29 (FIG. 1) which lowers the terminal voltage V _CB of the charge and discharge capacitor C _B.

On the other hand, the transistor Q _{20 supplies} the charging current to the charging / discharging capacitor C _B at the timing of the fall of the window signal _SWD , and the charging / discharging capacitor C _B , the transistors Q ₆ , Q ₈ and
A second transistor that delays the falling timing of the window signal _SWD by the time t _B together with Q ₂₁ , Q ₂₂ and Q ₂₃ , the resistors R _E3 , R _EXT , R _C7 and R _C8 , and the reference power supplies 20 and 22. It constitutes the circuit 30 (FIG. 1).

Furthermore, transistors Q ₇ , Q ₁₅ , Q ₁₈ , Q ₂₁ , Q ₂₂ and Q ₂₃ ,
The resistors R _B5 , R _B6 , R _C7 and R _C8 and the reference power supplies 20 and 22 have a rising timing with respect to the window signal _{SWD at} time t _B.
A transistor 30 and an inverting amplifier circuit 31 (FIG. 1) for outputting an output signal delayed by only the above are constituted.

By the way, in this embodiment, by forming the whole as an integrated circuit, it is possible to reduce the variation between the transistors and the capacitance variation between the charge / discharge capacitors C _A and C _B.

Further, the current I _EXT determined by the external resistance R _EXT is divided into three equal parts by the transistors Q ₅ , Q ₆ and Q ₇ , as shown in the equation (3), and the charge / discharge capacitors C _A and C _B are driven with the same current value. By doing so, the emitter voltage V _B of the transistor Q ₂₀ can be reduced at a voltage reduction rate equal to the emitter voltage V _A of the transistor Q ₄ .

Therefore, after delaying the rising of the window signal _SWD by the time t _{A and then} delaying the falling by the time t _B , the times t _A and t _B can be matched with high accuracy,
Thus, the delay time t _D can be set to a value equal to the delay time of the differentiating circuit 11 only by adjusting the resistance value of the external resistor R _EXT .

The delay circuit 13 outputs the output signal S _DL as the gate signal of the latch circuit 40 (FIG. 2).

On the other hand, the comparison circuit 41 outputs the comparison output signal whose signal level is inverted at the timing when the differential signal _SDV crosses the 0 level.
Outputs S _COM (Fig. 3 (E)) to the latch circuit 40.

Actually, the rising and falling of the signal level of the reproduction signal S _RF are obtained at the timing when the magnetic head scans the magnetization reversal region on the magnetic disk.

Therefore, when the comparison circuit 41 detects the timing at which the differential signal _SDV crosses the 0 level, it is delayed by the delay time t _D of the differential circuit 11 and the signal level changes according to the recording data on the magnetic disk. The inverted comparison signal S _COM is obtained, which allows the recording signal to be demodulated.

In However practice differential signal S _DV, during the period in which the reproduced signal S _RF signal level is a 0 level, resulting a period T ₀ the signal level is held at 0 level, thereby during the period T ₀ There is a problem that the error pulse P _E occurs in the comparison output signal S _COM .

Therefore, in the latch circuit 40, the comparison output signal S _COM is latched by the output signal S _DL to obtain the output signal S _OUT (FIG. 3 (F)) in which the mixing of the error pulse P _E is prevented in advance. This makes it possible to effectively avoid an error in the magnetic disk device with a simple structure as a whole.

By the way, as shown in FIG.
After delaying the rise of the S _WD, in the case of delaying the falling window signal S _WD (FIG. 6 (A))
When the period T _L during which the signal level of V falls becomes shorter than the delay time T _D , the emitter voltage V _A of the transistor Q ₄ (Fig. 6 (B)) does not fall below the base voltage V _R of the transistor Q ₁₁ , and As a result, the base voltage V _C4 (FIG. 6 (C)) of the transistor Q ₂₀ continues to fall and the output signal S _DL (FIG. 6 (D)) remains held at the logic “H” level. become.

However, as shown in FIG. 7, in the magnetic disk device, when the reproduction signal _SPB (FIG. 7 (A)) has a short cycle, the window signal _SWD (FIG. 7 (B)) The period T _L during which the signal level falls becomes shorter than the delay time, and in this case, a substantially sinusoidal differential signal S _DV (FIG. 7 (C)) is obtained.

Therefore, in this case, in the comparison circuit 41, the comparison output signal S _COM (FIG. 7 (D)) having no error pulse is obtained, and the output signal S _DL (FIG. 7 (E) held at the logic “H” level is obtained. )) To drive the latch circuit 40, the same output signal S _{DL as when} the logic level of the output signal S _DL is inverted.
_OUT (Fig. 7 (F)) is obtained.

Thus, in this embodiment, the output signal S _DL whose signal level is inverted is obtained from the delay circuit 12 only when the error pulse P _E is generated and the latch operation is required.

In the above configuration, the reproduction signal obtained from the magnetic head
The S _PB is converted into a differential signal S _DV by the differentiating circuit 11, and is delayed by the time T _{D at} this time.

Further reproduced signal S _PB is the comparison result in the window circuit 12 is obtained, thereby window signal S _WD whose signal level rises at the rise and fall of the reproduced signal S _PB are obtained.

Window signal S _WD is, the delay circuit 1 with the inverted signal S _IWD
2 is output to the transistor Q ₄ via the buffer circuit.
Given to.

As a result, the charging / discharging capacitor C _A is driven, and the fall of the window signal _SWD is passed through the transistor Q ₁₀ at time T _A
Delayed output signal was (V _C4) is obtained, the fall of the output signal (V _C4) (i.e. corresponding to the falling edge of the window signal S _WD) is, time in the subsequent transistor circuit
It is delayed by T _B , and thus the delay time T _D (T _D
= T _A = T _B ) Output signal S delayed from window signal _SWD
DL is obtained.

On the other hand, the differential signal S _DV is input to the comparison circuit 41,
As a result, the comparison output signal S _COM whose signal level is inverted when the differential signal S _DV crosses 0 level is obtained.

The comparison output signal S _COM is latched in the latch circuit 40 during the period in which the logic level of the output signal S _DL falls to the logic “L”, whereby the error pulse P _E is removed.

According to the above configuration, the discharge time of the charging / discharging capacitor connected to the emitter is used to delay the rising of the window signal _SWD , and subsequently to delay the rising, thereby simplifying the overall operation. It is possible to obtain a highly accurate delay time with the configuration, and thus it is possible to prevent an error from occurring with a simple configuration.

In the above embodiment, the case where the rising edge is delayed after delaying the falling edge of the window signal _SWD has been described, but the present invention is not limited to this, and conversely after delaying the rising edge. , The fall may be delayed.

Further, in the above-mentioned embodiment, the case where the discharging current source is connected to the charging / discharging capacitor and the charging current is given by the transistors Q ₄ and Q ₂₀ has been described. A current source may be connected and a transistor may be used to supply the discharge current.

Furthermore, in the above-described embodiment, the case where the inverting amplifier circuit is inserted between the first and second transistor circuits has been described, but the present invention is not limited to this, and for example, the first and second transistor circuits may be provided, respectively. It may be configured by NPN type and PNP type transistor circuits, and the inverting amplifier circuit may be omitted.

Further, in the above-mentioned embodiments, the case where the present invention is applied to the magnetic disk device has been described, but the present invention is not limited to this and can be widely applied to various electronic circuits.

As described above, according to the present invention, the first charge / discharge capacitor is connected between the collector and the emitter of the first transistor, and the emitter and the first charge / discharge capacitor of the first transistor are connected to each other. A first charge / discharge circuit formed by connecting a first constant current circuit to the first connection point, a second transistor having a base connected to the first connection point, and a base connected to a reference voltage. A first voltage comparison circuit having a differential amplifier circuit configuration formed by a connected third transistor, and a fourth voltage comparison circuit whose base is connected to the collector of the second transistor.
A second charging / discharging capacitor is connected between the collector and the emitter of the transistor, and a second connection point is formed between the emitter of the fourth transistor and the second charging / discharging capacitor.
A second charge / discharge circuit formed by connecting the constant current circuit, a fifth transistor having a base connected to the second connection point, and a sixth transistor having a base connected to a reference voltage. And a second voltage comparison circuit having a differential amplifier circuit configuration, which forms a delay circuit, and delays the fall of the input pulse signal supplied to the base of the first transistor to the discharge time of the first charge / discharge capacitor. By using the discharge time of the second charging / discharging capacitor to delay the rising edge of the input pulse signal, the rising edge and the falling edge of the input pulse signal can be accurately delayed. Therefore, it is possible to realize a delay circuit that can obtain a highly accurate delay time with a simple configuration.

BRIEF DESCRIPTION OF THE DRAWINGS FIG. 1 is a block diagram showing a schematic configuration of a delay circuit according to an embodiment of the present invention, FIG. 2 is a block diagram showing a signal processing circuit of a magnetic disk device, and FIG. 3 its operation. FIG. 4 is a signal waveform diagram for explaining, FIG. 4 is a connection diagram showing a concrete configuration of the delay circuit, FIGS. 5 to 7 are signal waveform diagrams for explaining the operation thereof, and FIG. 8 is a conventional delay circuit. Block diagram, FIG. 9 is a signal waveform diagram for explaining the operation, FIG. 10 is a block diagram showing another conventional delay circuit, and FIG. 11 is a signal waveform diagram for explaining the operation. 1,5,13 ...... delay circuit, 11 ...... differentiating circuit, 12 ...... window circuit, 25, 29 ...... discharge current source, 27, 31 ...... inverting amplifier circuit, C _A, C _B ...... discharge capacitor .

Claims (1)

[Scope of utility model registration request] 1. A first charging / discharging capacitor is connected between the collector and the emitter of the first transistor, and the first charging / discharging capacitor is connected.
First charging / discharging circuit formed by connecting a first constant current circuit to a first connection point between the emitter of the transistor and the first charging / discharging capacitor, and a base having the first connection. A first voltage comparison circuit having a differential amplifier circuit configuration including a second transistor connected to the point and a third transistor having a base connected to a reference voltage; and a collector of the second transistor. A second transistor is connected between the collector and the emitter of the fourth transistor whose base is connected.
And a second constant current circuit connected to the second connection point between the emitter of the fourth transistor and the second charge / discharge capacitor. A second voltage of a differential amplifier circuit configuration formed by a charge / discharge circuit, a fifth transistor whose base is connected to the second connection point, and a sixth transistor whose base is connected to a reference voltage. A comparator circuit for delaying the fall of the input pulse signal supplied to the base of the first transistor using the discharge time of the first charge / discharge capacitor, while A delay circuit characterized by delaying the rising edge of the input pulse signal by utilizing discharge time.