JPH07307710A - Communication method and device eliminating influence of cyclic fluctuation of power source voltage - Google Patents

Abstract

PURPOSE:To prevent the degradation of communication quality by eliminating the influence of the fluctuation of the power source voltage of a transmitter in an arbitrary period in a receiver even if a transmission signal level fluctuates by the influence. CONSTITUTION:A time division 62 is performed for communication data in the period according to the period of the fluctuation of power source voltage on a transmission side, a speed conversion to a high speed side is performed for the communication data within each division section in the section and the plural same communication data is multiplexed 63 with synchronizing signals and the data is transmitted 64. In a reception side, the level fluctuation of a reception signal is detected 65, the division section on the transmission side is extracted 66 based on the cycle of the level fluctuation and the synchronizing signal in the reception signal, communication data which is little affected by the level fluctuation of the same plural communication data within each division is extracted 65 and time series communication data on an original transmission side is obtained 67 based on the extraction. For instance, even when the level of the transmission signal of radio equipment such as the rotor modulation in the digital radio equipment for mounting on a helicopter periodically fluctuates by the fluctuation of power source voltage, communication quality is not degraded.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a communication method and apparatus capable of eliminating the influence of periodic fluctuations in power supply voltage level.

[0002]

2. Description of the Related Art FIGS. 6A and 6B are block diagrams of a transmitting side and a receiving side of a conventional digital radio apparatus. On the transmission side, an analog voice signal input from the microphone 70 is amplified by a voice amplifier 71, converted into a digital voice signal by an ADM (adaptive digital modulation) encoder 72, modulated by a modulator 73, and transmitted by a transmitter 74. To be transmitted as a radio wave. On the receiving side, the radio wave input from the antenna is received by the receiving unit 77, demodulated by the demodulating unit 78, and A
The DM decoding unit 79 converts the digital audio signal into an analog audio signal, the audio amplifying unit 80 amplifies the analog audio signal, and then outputs the audio from the speaker 81.

In such a radio, when the voltage level of the power supply used for the radio changes periodically, the transmitted signal may be affected by the change in the power supply voltage.
For example, a digital radio mounted on a helicopter
The power supply voltage level decreases in the rotation cycle of the rotor that rotates the propeller, and the transmission unit power decreases accordingly. Therefore, the transmission signal level also decreases in the same cycle.

FIG. 6 (c) conceptually shows the transmission signal affected by the rotation of the rotor of the helicopter. The signal level of the transmitted signal decreases at the rotor rotation cycle T _R ,
A kind of amplitude modulation is applied. This is called rotor modulation. When this signal is received by the receiving side and demodulated by the demodulation unit 78 to be returned to the baseband signal, a bit error is likely to occur in the portion where the signal level is lowered. As a result, the voice is not faithfully reproduced and the call quality deteriorates.

In the prior art, as a measure against rotor modulation, as shown in FIG.
5 and an AGC (automatic gain control) unit 76 are provided, the rotor rotation cycle is detected, and AGC is applied to the transmission unit 74 in accordance with the cycle, thereby suppressing the rotor modulation on the transmission signal.

[0006] Further, in the radio equipment mounted on the helicopter, the electric power of the receiving section is periodically reduced due to the influence of the rotation of the rotor of the radio equipment itself, and the received signal is affected, so that as shown in Fig. 6 (b). The rotor rotation period detector 82 and the AGC are also provided on the receiving side.
The section 83 is provided to suppress the periodic deterioration of the receiving characteristic of the receiving section 77.

[0007]

However, with the above-mentioned method of the prior art, it is not possible to completely prevent the periodic decrease of the transmission signal level in the digital radio apparatus on the transmission side, and the deterioration of the speech quality due to rotor modulation. The problem of still remains.

The present invention has been made in view of the above problems, and an object of the present invention is to provide a communication method which does not deteriorate the call quality regardless of the presence or absence of periodic fluctuation of the signal level due to a cause such as rotor modulation. It is to realize a communication device.

[0009]

FIG. 1 is a diagram illustrating the principle of the present invention. When making a call or data communication between communication devices, these communication data are time series. When transmitting and receiving time-series communication data, if the communication data undergoes level fluctuations due to periodic fluctuations in the power supply voltage, the communication data can be protected by the following communication method.

That is, on the transmitting side, time-series communication data is time-divided in a cycle according to the fluctuation cycle of the power supply voltage, and in each divided section, the communication data in that section is speed-converted to the high-speed side and the section concerned is divided. A plurality of same communication data are multiplexed together with a synchronization signal and transmitted.

On the receiving side, the level fluctuation of the received signal is detected, the divided section on the transmitting side is extracted based on the period of the level fluctuation and the synchronizing signal in the received signal, and a plurality of divided sections within each divided section are extracted. The communication data that is less affected by the level fluctuation is extracted from the same communication data of 1 and the time-series communication data on the original transmitting side is obtained based on the extracted communication data.

The configurations of the transmitter and the receiver using this communication method will be described below. The transmitter of FIG. 1 (1) includes a fluctuation cycle acquisition unit 61 that acquires information on a fluctuation cycle of a power supply voltage, and a fluctuation cycle acquisition unit 6 that acquires time-series communication data.
1. Time division means 62 for time division in a cycle corresponding to the fluctuation cycle acquired in 1. and speed conversion of communication data in each divided section to high speed side to multiplex a plurality of same communication data with a synchronization signal in the section. And a transmitting means 64 for transmitting the signal multiplexed by the multiplexing means 63.

In FIG. 1A, the multiplexing means 63 is arranged after the time division means 62, but the multiplexing means 6
A method of arranging the time division means 62 after 3 is also possible.

The receiving apparatus shown in FIG. 1B has a level fluctuation cycle detecting means 65 for detecting a cycle of level fluctuations of a received signal.
And a division section extraction unit 66 for extracting a division section that is time-divided on the transmission side based on the level fluctuation cycle detected by the level fluctuation cycle detection unit 65 and the synchronization signal in the received signal,
Of the plurality of identical communication data within each divided section extracted by the dividing means extracting means 66, the communication data that is less affected by the level fluctuation and the restoring means 6 that performs speed conversion to the original speed are extracted.
7 and 7.

The restoring means 67 shown in FIG. 1C has a separating means 671 for separating a plurality of identical communication data in each divided section extracted by the divided section extracting means 66 and a plurality of separated identical communication data, respectively. The speed conversion means 672 for converting the speed to the original speed and a plurality of separated and speed-converted same communication data are compared in a cycle corresponding to the level fluctuation cycle detected by the level fluctuation cycle detection means 65, and the level fluctuation It is composed of the determination selecting unit 673 which determines the communication data having a small influence and selects the communication data. In FIG. 1 (3), the judgment selecting means 673 is arranged after the speed converting means 672, but the speed converting means 672 may be arranged after the judgment selecting means 673.

The transmitter having the configuration shown in FIG. 1 (1) is applied to a wireless transmitter mounted on a helicopter that is connected to a power source of a helicopter to operate, and the fluctuation period acquisition means 61 supplies the rotor rotation period of the helicopter to the power source. It can be configured to be acquired as the fluctuation cycle of the voltage.

[0017]

The operation of the transmitter shown in FIG. 1A will be described. The fluctuation cycle acquisition means 61 acquires information on the fluctuation cycle of the power supply voltage and notifies the time division means 62 of it. The time division means 62 time-divisions the input time-series communication data in a cycle according to the fluctuation cycle acquired by the fluctuation cycle acquisition means 61, and outputs each divided section to the multiplexing means 63. The multiplexing means 63 speed-converts the communication data in the divided section to the high speed side, multiplexes a plurality of the same communication data in the section together with a synchronization signal, and outputs the multiplexed signal to the transmitting means 64. The transmitting means 64 transmits the multiplexed signal to the receiving device. This transmission signal undergoes level fluctuation in the same cycle due to the effect of cyclic fluctuation of the power supply voltage.

The operation of the receiver shown in FIG. 1 (2) will be described. The received signal is input to the level fluctuation period detecting means 65 and the division section extracting means 66. The level fluctuation cycle detecting means 65 detects the cycle of the level fluctuation of the received signal and notifies the divided section extracting means 66 and the restoring means 67 of the cycle. The division section extraction unit 66 extracts the division section that is time-divided on the transmission side from the reception signal based on the level fluctuation cycle detection unit 65 and the synchronization signal in the reception signal, and outputs the extracted division section to the restoration unit 67. The restoring unit 67 extracts communication data that is less affected by level fluctuations among the plurality of identical communication data in each divided section, converts the communication data to the original speed, and outputs the original speed.

The operation of the restoring means 67 shown in FIG. 1C will be described. The division section extracted by the division section extraction unit 66 is input to the separation unit 671, and the fluctuation cycle detected by the level fluctuation cycle detection unit 65 is input to the determination selection unit 673. The separating means 671 separates a plurality of the same communication data in each divided section and outputs them to the speed converting means 672.
The speed conversion means 672 speed-converts each of the plurality of separated identical communication data to the original speed, and then the judgment selection means 673.
Output to. The determination selection unit 673 compares the plurality of separated and speed-converted same communication data at a cycle corresponding to the level fluctuation cycle detected by the level fluctuation cycle detection unit 65, and judges the communication data that is less affected by the level fluctuation. Then, the communication data is selected and output.

In the above case, the judgment selecting means 673
The speed conversion means 672 may be performed after the above.

[0021]

Embodiments of the present invention will be described below with reference to the drawings. FIG. 2 shows a block diagram of a digital radio transmitter mounted on a helicopter according to an embodiment of the present invention. This transmitter is composed of an input unit, a rotor rotation period acquisition unit, a time division unit, a duplication unit, and an output unit.

The input unit is composed of the microphone 1, the voice amplifier 2, the ADM encoding unit 3 and the 8 kHz output unit 4, the rotor rotation period acquisition unit is composed of the switching signal output unit 6, and the time division unit is the switching unit 7. The duplexer is composed of a speed conversion clock generation unit 5, a synchronous code generation circuit 8, a synchronous code addition circuit 9, a switching unit 10, 11, 13, 18, 19, 20 and an inverting circuit 12 and a speed conversion circuit 14, 15. And delay circuit 16,
17 and. The output unit is a modulator 21 and a transmitter 22.
Composed of and.

In the input section, the microphone 1 inputs the voice signal, the voice amplifying section 2 amplifies the voice signal, and the ADM
The encoding unit 3 is 8 kHz supplied from the 8 kHz output unit 4.
Voice signal from analog signal to speed 8 using the clock of
Convert to a digital signal of kbps. The 8 kHz output unit 4 also supplies the speed conversion clock on the low speed side to the speed conversion circuits 14 and 15 of the duplexing unit.

In the rotor rotation cycle acquisition unit, the switching signal output unit 6 outputs a switching clock to each switching unit. In the time division unit, the switching unit 7 time-divisions the ADM-coded digital signal at the input unit.

In the duplexing unit, the speed conversion clock generation unit 5 generates the speed conversion clock on the high speed side to be supplied to the speed conversion circuits 14 and 15, the synchronous code generation circuit 8 generates a synchronous code, and the synchronous code addition circuit 9 The switching units 10 and 11 and the inverting circuit 12 add a synchronization code to each divided section of the digital signal, and the switching unit 13 switches the speed conversion clocks to the speed conversion circuits 14 and 15, and the speed conversion circuits 14 and 1
5 speeds up each divided section of the digital signal, delay circuits 16 and 17 delay each speeded up divided section, and switching units 18 and 19 connect the divided section before delay and the divided section after delay to switch the divided sections. The unit 20 concatenates the signals output by the switching unit 18 and the switching unit 19 and returns them to one series, and outputs the signals to the output unit.

In the output section, the modulation section 21 modulates the digital signal input from the duplexing section, and the transmission section 22.
Transmits the modulated signal as a radio wave.

The operation of each part of the transmitter of this embodiment will be described in detail below with reference to the block diagram of FIG. 2 and the time chart of FIG. However, since the input section and the output section are not different from those of the conventional technique, detailed description thereof will be omitted.

The rotor rotation acquisition unit will be described. The switching signal output unit 6 receives an external rotor rotation frequency (for convenience, 2
XHz). The switching signal output unit 6 generates the switching clock (c) of XHz and the switching clock (d) of 2XHz by using the rotor rotation frequency of 2XHz. X
The switching clock (c) of Hz is used by the switching unit 7 of the time division unit.
And the synchronizing code generating circuit 8 of the duplexing unit, the switching unit 10, the switching unit 11, the switching unit 13, and the switching unit 20, respectively.
However, the switching clock (c) output to the switching unit 11 is inverted by the inverting circuit 12 so that the operations of the switching unit 10 and the switching unit 11 are in opposite phases. The switching clock (d) of 2XHz is output to the switching unit 18 and the switching unit 19 of the multiplexing unit.

Next, the time division unit will be described. The switching unit 7 receives the digital signal (b) at a speed of 8 kbps and the switching clock (c) at XHz from the ADM encoding unit 3. The switching unit 7 alternately switches to the terminal side and the terminal side every half cycle of the switching clock (c),
A in the digital signal (b) is input to the terminal of the switching unit 10,
, Are output to the terminals of the switching unit 11 as B, D, ... In the digital signal (b), whereby the digital signal (b) is time-divided at a cycle of 2 XHz.

Next, the duplication section will be described. The speed conversion clock generator 5 is externally connected to the rotor rotation frequency 2XH.
z is given. The speed conversion clock generation unit 5 uses the rotor rotation frequency of 2 XHz and the 8 kHz clock supplied from the input unit 8 kHz output unit 4 to generate a frequency (8 kHz x
A speed conversion clock of 2 + α) Hz is generated and output to the synchronous code generation circuit 8 of the duplexing unit and the switching unit 13. Here, α is a value determined by the number of bits of the synchronization code added to the communication data.

The synchronous code generating circuit 8 has (8k × 2 + α)
The speed conversion clock of Hz and the switching clock (c) of XHz are input. The synchronization code generation circuit 8 generates an α′-bit synchronization code synchronized with the speed conversion clock of (8k × 2 + α) Hz every half cycle of the switching clock (c), and outputs it to the synchronization code addition circuit 9. To do. Since α corresponds to the number of bits per second of the synchronization code, the relationship between α and α'is α / α '= 2X. The sync code adding circuit 9 switches this sync code to the switching unit 1.
It is output to the terminal of 0 and the terminal of the switching unit 11.

The switching unit 10 alternately switches to the terminal side and the terminal side every half cycle of the switching clock (c), so that the synchronization input from the terminal is added to the end of the digital signal (b) of 8 kbps in speed input from the terminal. A code is added and the signal is output to the speed conversion circuit 14 as a signal (e). Similarly, the switching unit 11 alternately switches between the terminal side and the terminal side every half cycle of the switching clock (i), so that the synchronization code input from the terminal is added to the end of the digital signal (b) having a speed of 8 kbps input from the terminal. Is added and is output to the speed conversion circuit 15 as a signal (j). In this case, on the switching unit 11 side, since the switching clock (i) is the switching clock (c) inverted by the inverting circuit 12, when the switching unit 10 switches to the terminal side, the switching unit 11 switches to the terminal side. Switching unit 10
When is switched to the terminal side, the switching unit 11 is switched to the terminal side. That is, the switching units 10 and 11 have terminals,
The timing of switching to is opposite to each other.

8 kHz is applied to the terminals of the switching unit 13 and the terminal '.
The speed conversion clock of z is input, and the speed conversion clock of (8 kHz × 2 + α) Hz is input to the terminal and the terminal ′ of the switching unit 13. In response to the XHz switching clock (c), the switching unit 13 alternately switches between terminals and between terminals' and ', but when switching to the terminal side, it switches to the terminal' side and then to the terminal side. When switching, it switches to the terminal 'side.

The speed conversion circuit 14 is 8k from the switching unit 13.
While the speed conversion clock of Hz is supplied, a signal (e) having a speed of 8 kbps is input into the circuit in synchronization with the clock, and after the input of one division section is completed, the data of the division section stored in the circuit is stored. , (8k × 2 + α) Hz supplied next
Output in synchronization with the speed conversion clock of. As a result, the digital signal (e) having a speed of 8 kbps is transmitted at a speed of
+ Α) bps signal (f) is converted. Since the sync code added to the end of each divided section of the signal (e) is generated in advance at a speed of (8k × 2 + α) bps, the speed conversion circuit 14 uses a clock of (8k × 2 + α) Hz. It is input and is also output at the clock of (8k × 2 + α) Hz. That is, the sync code portion only passes through the speed conversion circuit 14 and is not converted in speed.

The speeded-up signal (f) is output to the terminal of the switching section 18 and the delay circuit 16. The delay circuit 16 delays the signal (f) by a half cycle of the switching clock (d) of 2XHz, and outputs it as a signal (g) to the terminal of the switching unit 18. The switching unit 18 alternately switches to the terminal side and the terminal side every half cycle of the switching clock (d) of 2 XHz, so that the signal (g) is connected immediately after the signal (f) and the signal is duplicated. It outputs to the terminal of the switching part 20 as (h).

The process from the speed conversion circuit 15 to the switching unit 20 is the same as the process from the speed conversion circuit 14 to the switching unit 20 described above, and the digital signal (j) having a speed of 8 kbps is (8k × 2 + α). A signal (k) that has been speeded up to bps and a signal (l) that is obtained by delaying the signal (k) by a half cycle of 2 XHz are connected, and a signal that has been duplicated (m)
To the terminal of the switching unit 20.

The switching unit 20 alternately switches to the terminal side and the terminal side every half cycle of the XHz switching clock (c) to connect the signal (h) and the signal (m) back to one series, It is output to the output unit as a signal (n).

Next, the conversion process of the audio signal in the transmitter of this embodiment will be described with reference to the time chart of FIG. In the input section, voice amplified analog signal (a)
Is ADM encoded and converted into a digital signal (b) having a speed of 8 kbps.

In the rotor rotation period acquisition section, a switching clock (c) of XHz and a switching clock (d) of 2XHz are generated based on the rotor rotation frequency 2XHz given from the outside. The time division unit extracts the sections A, C, ... Of the digital signal (b) while the switching clock (c) is at the high level, and the switching clock (c) is at the low level. During this period, sections B, D, ... Of the digital signal (b) are extracted.

In the duplexer, first, when the switching clock (c) falls, a synchronization code is added to the end of each section A, C, ... When the clock (i) falls, each section B, D,
The two series of signals (e) and (j) are generated by adding a synchronization code to the end of.

Next, the voice signal portion of the signal (e) is set to 8 kb.
The signal (f) is generated by increasing the speed from ps to (8k × 2 + α) bps, and the voice signal portion of the signal (j) is 8kbp.
s to (8k × 2 + α) bps and signal (k)
To generate. Note that the sync code portions of the signals (e) and (j) are generated in advance at a speed of (8k × 2 + α) bps, and therefore the speed is not increased here.

Further, the signals (f) and (k) are delayed by a half cycle of the switching clock (d) to generate the signals (g) and (l) on a path different from the original signal. And switching unit 1
In FIG. 8, the signal (f) is merged into the same path when the switching clock (d) is high level and the signal (g) is merged into the same path when the switching clock (d) is low level, so that two identical sections (A and A ′, C
And C ′, ...) Generate a continuous signal (h). Similarly, in the switching unit 19, when the switching clock (d) is at the high level, the signal (k) is merged into the same path when the switching clock (d) is at the low level, so that the same two sections ( A signal (m) in which B and B ', D and D', ...) are continuous.
To generate.

Finally, when the switching clock (c) is at the high level, the signal (h) is merged into the same path when the switching clock (c) is at the low level, and the signal (m) is merged into the same path (A and A). A ', B and B', C and C ', D and D', ...)
Generate a continuous signal (n).

This signal (n) is output from the transmitter as a radio wave, but at that time, the level of the transmitted signal decreases in the rotor rotation cycle. However, since the signal is duplicated, only one of the two consecutive same sections is subjected to this level reduction.

FIG. 4 is a block diagram of a digital radio receiver mounted on a helicopter according to an embodiment of the present invention. This receiver is roughly composed of an input unit, a level fluctuation period detection unit, a divided section extraction unit, a restoration unit, and an output unit. The function of the restoration unit is composed of a separation unit, a speed conversion unit, and a judgment selection unit.

The input section is composed of a rotor rotation cycle detecting section 31, an AGC section 32, a receiving section 33 and a demodulating section 34. The level fluctuation cycle detection unit is composed of a level detection circuit 351, a cycle detection circuit 352, and a protection circuit 353. The division section extraction unit is composed of the switching unit 38. In the restoration unit, the separation unit is composed of the switching units 39 and 40, the speed conversion unit is composed of the switching unit 41 and the speed conversion circuits 42 to 45,
The determination / selection unit includes the switching units 46, 47, 51 and the level extraction unit 4.
8 and 49 and a level comparator 50. The output unit is composed of an ADM decoding unit 52, a voice amplifier 53, and a speaker 54. In addition, a synchronous reproduction circuit 36 and a signal generation circuit 37 are provided as circuits for supplying control signals to the above respective parts.

In the input section, the receiving section 33 receives the radio wave, the demodulating section demodulates the received signal and returns it to the baseband signal, and the own rotor rotation cycle detecting section 31 detects the rotor rotating cycle of the own machine. The AGG unit 32 applies AGC to the receiving unit 33 according to the detected rotor cycle of the own device.

The synchronous reproduction circuit 36 reproduces the synchronization by detecting the synchronous code in the demodulated received signal, and the signal generation circuit 37 supplies the switching clock to each switching unit and the speed conversion clock to the speed conversion circuit. To generate.

In the level fluctuation cycle detection section, the level detection circuit 351 detects a decrease in the signal level of the reception signal before demodulation input from the reception section 33, and the cycle detection circuit 352.
Detects a cycle in which the signal level of the received signal decreases, and the protection circuit 353 prevents the cycle detected by the cycle detection circuit 353 from being disturbed. In the division section extraction unit, the switching unit 38
Extracts a time-divided section on the transmitter side from the received signal.

In the separation section of the restoration section, the switching sections 39 and 4
0 separates the duplicated communication data in each divided section. In the speed conversion unit of the restoration unit, the switching unit 41 switches the speed conversion clocks supplied to the speed conversion circuits 42 to 45, and the speed conversion circuits 42 to 45 reduce the speed of each separated communication data to the original speed. Convert to. In the determination / selection unit of the restoration unit, the switching units 46 and 47 connect the slowed down communication data to restore the two-series digital audio signal, and the level extraction units 48 and 49 restore the two-series digital audio signal. Of the divided sections, the level comparator 50 compares the extracted signal levels of the divided sections, and the switching unit 51 selects one of the compared divided sections that has a smaller decrease in signal level. Output to the output section.

In the output section, the ADM decoding section 52 converts the restored digital audio signal into an analog audio signal, and the audio amplifier 53 amplifies the analog audio signal and outputs it from the speaker 54.

The operation of each part of the receiver of this embodiment will be described in detail below with reference to the block diagram of FIG. 4 and the time chart of FIG. However, since the input section and the output section are not different from those of the conventional technique, detailed description thereof will be omitted.

First, the level fluctuation cycle detector will be described. When the signal level of the received signal input from the receiving unit 33 falls below a certain threshold, the level detection circuit 351 detects a low level occurrence by the logarithmic amplifier and notifies the cycle detection circuit 352 of it. The cycle detection circuit 352 measures the low level generation cycle with a counter. This cycle is the cycle of rotor modulation on the transmitter side.

In the protection circuit 353, if noise is mixed in the received signal, the cycle of rotor modulation detected by the cycle detection circuit 353 is disturbed, so that the cycle detection circuit 353 can detect noise generated at irregular timings. This is a circuit to protect it from being detected as a modulation cycle. When the cycle detection circuit 352 detects the cycle of rotor modulation, the cycle detection circuit 352 outputs a timing signal synchronized with the timing to the synchronous reproduction circuit 36 and the level extraction sections 48 and 49 of the restoration section.

Next, the synchronous reproducing circuit 36 and the signal generating circuit 37.
Will be described. The sync reproduction circuit 36 inputs the reception signal demodulated by the demodulation unit 34 and the timing signal from the cycle detection circuit 352, detects a synchronization code in the reception signal, and outputs 2
The XHz synchronization signal is reproduced, the phase of the timing signal and the phase of the synchronization signal are compared, and if a phase correlation is recognized, this synchronization signal is output to the signal generation circuit 37.

The signal generation circuit 37 receives the input 2XHz
A switching clock (b) for XHz, a switching clock (c) for 2XHz, and a switching clock (d) for XHz whose phase is delayed from the switching clock (b) by 1/4 cycle based on the synchronization signal of An XHz switching clock (e) whose phase is delayed by 1/4 cycle from the switching clock (d) is generated, and further a speed conversion clock of 8 kHz and (8k × 2 + α) kHz is generated. The switching clock (b) is sent to the switching unit 38 of the division section extraction unit, the switching clock (c) is sent to the switching units 39 and 40 of the restoration unit, and the switching clock (d) is sent to the switching units 41 and 46 of the restoration unit. , The switching clock (e) is output to the switching units 41 and 47 of the restoration unit, respectively. Further, the speed conversion clocks of 8 kHz and (8 k × 2 + α) kHz are output to the switching unit 41.

Next, the divided section extraction unit will be described. The switching unit 38 alternately switches to the terminal side and the terminal side every half cycle of the XHz switching clock (b),
Speed (8k × 2 + α) bps input from demodulation unit 34
The signal (f) is output from the terminal to the switching unit 39 and the signal (g) is output from the terminal to the switching unit 40 while dividing the digital signal (a). As a result, a continuous division section including two identical data is extracted from the digital signal (a) and separated into two series of signals (f) and (g), which are output to the switching unit 39 and the switching unit 40, respectively. It

Next, the separation unit of the restoration unit will be described. The switching unit 39 divides the signal (f) by alternately switching between the terminal side and the terminal side every half cycle of the switching clock (c) of 2XHx, and the signal (h) from the terminal to the speed conversion circuit 42. , To output the signal (j) to the speed conversion circuit 43. Similarly, the switching unit 40 is 2XHx
While the signal (g) is divided by alternately switching to the terminal side and the terminal side every half cycle of the switching clock (c) of (1), the signal (1) from the terminal to the speed conversion circuit 44,
The signal (n) is output from the terminal to the speed conversion circuit 45.
As a result, two consecutive identical data in each divided section of the signal (f) and the signal (g) are separated, and the first half data in each divided section of the signal (f) is sent to the speed conversion circuit 42 and the latter half. The data is output to the speed conversion circuit 43, the first half data in each divided section of the signal (g) is output to the speed conversion circuit 44, and the second half data is output to the speed conversion circuit 45.

Next, the speed conversion section of the restoration section will be described. The switching unit 41 has 8 kHz and (8 kHz × 2 +
The α) Hz speed conversion clock, the XHz switching clock (d), and the XHz switching clock (e) are input.
The switching unit 41 responds to the timing generated by the combination of the switching clocks (d) and (e) whose phases are deviated by ¼ cycle, and outputs eight signals to each of the speed conversion circuits 42 to 45.
The speed conversion clocks of kHz and (8 kHz × 2 + α) Hz are alternately output.

The speed conversion circuits 42 to 45 are (8 kHz ×
The speed (8k) is synchronized with the speed conversion clock of 2 + α) Hz.
Hz × 2 + α) bps signals (h), (j), (l),
By inputting (n) into the circuit and then outputting them in synchronization with the speed conversion clock of 8 kHz, the signals (i), (k), which are slowed down to the original speed of 8 kbps,
(M) and (o) are generated. At that time, the signal (h),
The sync code included in (j), (l), and (n) is discarded. The signals (i), (k), (m), and (o) are the terminals of the switching unit 46, the terminals of the switching unit 47, and the switching unit 4, respectively.
6 and the terminal of the switching unit 47.

Next, the judgment selecting section will be described. The switching unit 46 alternately switches to the terminal side and the terminal side every half cycle of the switching clock (d) of XHz and merges the signal (i) and the signal (m) into the same path, thereby dividing into two series. The output signal is returned to one series of signals (p) and is output to the terminals of the level extraction unit 48 and the switching unit 51. As a result of the above processing, a signal (p) is obtained by extracting the first half data of two consecutive same communication data in each divided section of the received signal (a), restoring the original speed, and concatenating the extracted data.
Is.

Similarly, the switching unit 47 alternately switches between the terminal side and the terminal side every half cycle of the XHz switching clock (e) to merge the signal (k) and the signal (o) into the same path. Thus, the signal that has been divided into two series is returned to the signal (q) of one series and is output to the terminals of the level extraction unit 49 and the switching unit 51. As a result of the above processing, the signal (q) is obtained by extracting the latter half data of two consecutive same communication data in each divided section of the received signal (a), restoring the original speed, and concatenating the extracted data. is there.

The level extraction section 48 extracts the signal level of the input signal (p) in response to the timing signal from the cycle detection circuit 352 of the level fluctuation cycle detection section, and outputs it to the level comparator 50. To do. Similarly, the level extraction section 49 responds to the timing signal from the cycle detection circuit 352 of the level fluctuation cycle detection section in response to the input signal (q).
The signal level of the signal is extracted and output to the level comparator 50.

The level comparator 50 compares the signal levels of the signal (p) and the signal (q), and when the signal level of the signal (p) is higher, switches the switching unit 51 to the terminal side and vice versa. When the signal level of (q) is higher, the switching unit 51
A switching clock for switching to the terminal side is output to the switching unit 51. Thereby, the signal (p) and the signal (q)
The signal having the smaller level decrease is selected for each divided section and output to the output unit.

Next, the conversion process of the audio signal in the receiver of this embodiment will be described with reference to the time chart of FIG. In the input section, the received signal is (8k × 2 + α) bps
Demodulate to a digital signal (a) at the speed of.

Level fluctuation period detector, synchronous reproduction circuit 3
6 and the signal generation circuit 37, based on the signal level of the reception signal before demodulation and the synchronization code included in the demodulated digital signal (a), the switching clock (b) for XHz and the switching clock for 2XHz. (C), XHz switching clock (d) whose phase is delayed by 1/4 cycle from the switching clock (b), and XHz switching whose phase is delayed by 1/4 cycle from the switching clock (d) Generate clock (e).

The division section extraction unit extracts the division sections A.A ', C.C', ... Of the digital signal (a) during the high level period of the switching clock (b), and the switching clock (b). ) Is divided into two series of signals (f) and (g) by extracting the divided sections B · B ′, D · D ′, ... Of the digital signal (a) in the low level period of).

In the separation unit of the restoration unit, the switching unit 39 extracts the first half data (A, C, ...) Of each divided section of the signal (f) in the high level period of the switching clock (c), By extracting the latter half data (A ′, C ′, ...) Of each divided section of the signal (f) in the low level period, it is further separated into two series of signals (h) and (j). Similarly,
In the switching unit 40, the first half data (B, of each divided section of the signal (g) in the high level period of the switching clock (c)
.), And the second half data (B ', D', ...) Of each divided section of the signal (g) in the low level period. Separate into (n).

In the speed conversion section of the restoration section, the audio signal portions of the signals (h), (j), (l) and (n) are respectively responded to the timings of the switching clocks (d) and (e). The signals (i), (k), (m), and (o) are generated by reducing the speed from (8k × 2 + α) bps to 8kbps. The sync code added to the end of each data of the signals (h), (j), (l) and (n) is discarded at this time.

In the judgment selecting section, the switching section 46 outputs the signal (i) during the high level period of the switching clock (d),
In the low level period, the signal (m) is merged with the same path to connect the sections (A, B, C, D, ...) And generate the signal (p). The signal (k) is merged into the same path during the high level period of the clock (e) and the signal (o) is merged into the same route during the low level period (A ′, B ′, C ′, D ′, ...). To generate a signal (q) in which Since the signal (p) is generated in synchronization with the switching clock (d) and the signal (q) is generated in synchronization with the switching clock (e), the signals (p) and (q) have a phase of XHz. The clocks are shifted by ¼ cycle, and the corresponding data sections are temporally overlapped by half sections (the latter half of A and the first half of A ′, the latter half of B and the first half of B ′, the latter half of C and C). The first half of ', the second half of D and the first half of D',
・ ・).

Further, in response to the timing signal from the level fluctuation period detecting section, by comparing the signal levels of the portions where the corresponding data sections of the signal (p) and the signal (q) are overlapped, The higher data section is selected by the switching unit 51 and output to the output unit.

This example is an example, and various embodiments other than the above-described method are possible. For example, in this embodiment, the digitized voice signal is time-divided and then the data in the divided section is duplicated.
A method of multiplexing so that one or more identical data is included is also possible. Further, although the synchronization code is added to the end of each duplicated data, the synchronization code is added to the beginning of each data, or the synchronization code is added only to one position at the beginning or end in the divided section. There is also a method. The structure of each switching unit, the waveform and timing of the switching clock signal,
Alternatively, the structure of the other components may be implemented in any concrete manner as long as the same result can be obtained. In addition, although this embodiment is an example of a radio device mounted on a helicopter, it can be applied to normal wireless communication or wired communication.

[0073]

As described above, according to the present invention, even if the power supply voltage of the transmission device fluctuates in an arbitrary cycle and the transmission signal level fluctuates due to the influence, the influence can be removed by the reception device. Therefore, it is possible to prevent deterioration of communication quality.

If the present invention is applied to a digital radio mounted on a helicopter, even if the power supply voltage of the transmitter radio periodically fluctuates due to the rotation of the rotor at an arbitrary speed of the helicopter, deterioration of the call quality is prevented. can do.

[Brief description of drawings]

FIG. 1 is a diagram illustrating the principle of the present invention.

FIG. 2 is a block diagram of a transmitter according to an embodiment of the present invention.

FIG. 3 is a time chart of signals of respective parts of the transmitter according to the embodiment of the present invention.

FIG. 4 is a block diagram of a receiver according to an embodiment of the present invention.

FIG. 5 is a time chart of signals of respective parts of the receiver according to the embodiment of the present invention.

FIG. 6 is a diagram illustrating a conventional example.

[Explanation of symbols]

1, 70 Microphone 2, 53, 71, 80 Audio amplifier 3, 72 ADM coding unit 4 8 kHz output unit 5 Speed conversion clock generation unit 6 Switching signal output unit 7, 10, 11, 13, 18 to 20, 38 to 41 Four
6, 47, 51 Switching unit 8 Sync code generation circuit 9 Sync code addition circuit 12 Inversion circuit 14, 15, 42-45 Speed conversion circuit 16, 17 Delay circuit 21, 73 Modulation unit 22, 74 Transmission unit 31, 75, 82 Self-rotor rotation period detection unit 32, 76, 83 AGC unit 33, 77 reception unit 34, 78 demodulation unit 351 level detection circuit 352 period detection circuit 353 protection circuit 36 synchronization reproduction circuit 37 signal generation circuit 48, 49 level extraction unit 50 Level comparison unit 52, 79 ADM decoding unit 54, 81 speaker

Claims (5)

[Claims] 1. On the transmission side, time-series communication data is time-divided at a cycle according to a fluctuation cycle of a power supply voltage, and in each divided section, the communication data in the section is speed-converted to a high-speed side and the section concerned. A plurality of same communication data are multiplexed together with a synchronization signal and transmitted, and the receiving side detects the level fluctuation of the received signal, and based on the cycle of the level fluctuation and the synchronizing signal in the received signal, the transmitting side To extract time-series communication data on the original transmission side based on the extracted communication data that is less affected by level fluctuations out of the same communication data in each of the data Communication method. 2. A fluctuation cycle acquisition means (61) for acquiring information on a fluctuation cycle of a power supply voltage, and a time division for time-dividing time-series communication data at a cycle corresponding to the fluctuation cycle acquired by the fluctuation cycle acquisition means. Means (6
2), and a multiplexing means (63) for speed-converting the communication data in each divided section to a high speed side and multiplexing a plurality of the same communication data together with a synchronization signal in the section, and multiplexing by the multiplexing means. Transmitting means for transmitting the signal (6
4) A transmitter comprising: 3. A level fluctuation cycle detecting means (65) for detecting a cycle of level fluctuations of a received signal, and a transmitting side based on a cycle of level fluctuations detected by the level fluctuation cycle detecting means and a synchronization signal in the received signal. A division section extracting means (66) for extracting a division section which is time-divided by the step of extracting the communication data which is less affected by the level fluctuation among a plurality of the same communication data in each division section extracted by the division means extracting means; A receiving device comprising a restoring means (67) for converting the speed to the original speed. 4. The decomposing means (67) separates a plurality of identical communication data in each divided section extracted by the divided section extracting means (66).
A speed conversion means (672) for speed-converting each of the separated plurality of identical communication data into an original speed; and a plurality of separated and speed-converted identical communication data by the level fluctuation cycle detection means (65). 4. The determination / selection means (673) for comparing in a cycle according to the detected level fluctuation cycle, judging communication data having less influence of level fluctuation among them, and selecting the communication data. Receiver. 5. The transmission device according to claim 2, wherein the transmission device is mounted on a helicopter and is operated by using a power source of the helicopter, wherein the fluctuation period acquisition means (61) determines a rotor rotation period of the helicopter as a fluctuation period of a power supply voltage. A wireless transmission device that is designed to be acquired as.