JPH07306784A - Register management device - Google Patents

Abstract

PURPOSE:To remove restrictions from a register which can handle respective instructions although the register which is used distinctively between address and data. CONSTITUTION:The register 1 consists of an address register 2 dedicated to address data and a data register 3 dedicated to arithmetic data, and an instruction decoding part 5 selects the address register 2 or data register 3 according to the value of a register switching flag 6. Kinds of registers (address/register) usable for respective instructions are limited, but the kinds of registers that can handle the instructions can be switched by setting the register switching flag 6. Thus, the registers are separated for addresses and data and then the number of bits in an instruction which specify a register may be small; and an increase in instruction word length can be suppressed, and restrictions are removed from the kinds of registers which can handle the respective instructions to increase the processing speed of a program and decrease the number of program steps.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a register management device capable of changing a register to be operated by each instruction of a CPU by a flag.

[0002]

2. Description of the Related Art As a means for a CPU to execute a program, a plurality of registers are provided in hardware, and necessary to process the program from a memory or an input device into the plurality of registers by executing an instruction included in the CPU. A method of arranging data and performing processing by operating the contents of the register is considered. The data stored in the register includes address data for designating a memory location as a target and information (calculation data) for actual calculation / operation. When executing a program, it is necessary to specify multiple memory locations and target multiple operation data. It has multiple registers in hardware,
A method of arranging those address data and operation data in a register has been adopted. As a result, the frequency of exchanging data in each register can be reduced, and the program execution speed has been improved.

The functions of the register are as follows: (1) Address data and operation data can be used without distinction as the function of the register, and the instructions of the CPU can operate all registers. (2) Address as the function of the register The dedicated registers for data and the registers dedicated for operation data are separately provided.Data transfer and addition / subtraction instructions that are frequently used in address operations and address operations target the registers dedicated to address data. The data transfer and operation instructions that are frequently used in operations generally include address / data separation registers that operate on dedicated registers for operation data. An instruction is composed of an instruction code field that specifies how the instruction moves and a source / destination field that indicates the location of the data itself or the data that is the target of the movement of the instruction. .

Conventionally, in the general-purpose register (1), since the address data and the operation data are operated, the number of registers is as large as about 32, and in order to specify them with an instruction, one register is About 5 bits were needed in the instruction. As a result, the number of parts in the instruction that specify the general-purpose register increases, the number of bits that make up the instruction increases, and the number of programs increases.

On the other hand, in the address / data separation register (2), since the operation target is divided into address data and operation data, the number of each register is about -16. The total number of registers including address registers and data registers is up to 32 as in the general-purpose register of (1).
Although there are as many as about four registers, it is possible to select the registers to be operated by each instruction. Therefore, in order to specify them with an instruction, about 4 bits are required in each instruction per register. Although the increase in the number of bits that make up an instruction can be suppressed compared to general-purpose registers, there are restrictions on the instructions that can be used due to the register function. Therefore, in order to execute a series of processing of the program, data was transferred between the address register and the operation data register, and the processing was executed using the instruction to be used. This has caused an increase and a decrease in the processing speed of the program.

Further, the number of address data and operation data in the program varies depending on the contents of the program, and it is very difficult to specify the number and to generalize the ratio of the address data and operation data. . The general-purpose register is extremely versatile because its use can be freely selected by the program, but even if the address / data separation register lacks one register depending on the program and the other register is left over, those resources can be used. There was a case that could not be used efficiently. Due to the limitation of the number of address registers and data registers, when operating data that cannot be placed in each register, it is necessary to replace the data placed in the registers. Was incurred.

[0007]

As described above, in the prior art, (1) the general-purpose register means has no limitation on the registers that each instruction can handle, but the number of bits designating the general-purpose register in the instruction increases, and the instruction word length is increased. (2) The address / data separation register can suppress the increase in the instruction word length because the number of bits that specify the register in the instruction is small, but there is a limit to the register that each instruction can handle, There was a problem that the number of registers became insufficient, and the number of programs increased in order to perform a series of processing and operations.

An object of the present invention is to solve such a conventional problem and to provide a register management device capable of improving the program processing and reducing the program steps.

[0009]

In order to solve the above-mentioned problems, the register management device of the present invention separates the use of address and data as the function of the register, and, even though it is an address / data separation register, each instruction The register which is the operation target of is configured so that it can be changed by a flag.

[0010]

With this configuration, (1) Since the register function separates the use of the address and the data as the function of the register, the number of bits to specify the register in the instruction may be small, and the instruction word length can be increased. (2) Even though it is an address / data separation register, the register to be operated by each instruction can be changed by a flag, so there is no restriction on the register that can be handled by each instruction and the program can be executed efficiently. It is possible to realize reduction of program steps.

[0011]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment of the present invention will be described below with reference to the drawings. FIG. 1 is a diagram showing the configuration of a register management device according to an embodiment of the present invention. The register 1 is composed of an address register 2 dedicated to address data and a data register 3 dedicated to operation data. The number of each of the address register 2 and the data register 3 is n. On the other hand, the program 4 is input to the instruction decoding unit 5 when the CPU (not shown) starts operating, and the instruction decoding unit 5 selects the address register 2 and the data register 3 according to the value of the register switching flag 6. The program is composed of instructions, and as a breakdown of the instructions, there are (1) an instruction group A for operating the address register 2 in the initial state (2) an instruction group B 1 for operating the data register 3 in the initial state. The bit configuration of the instruction is shown in FIG. 2 as an example.
The configuration is as shown in.

As an example of the number of registers, if the address register 2 and the data register 3 are each configured by n = 8, in order to specify the register in the instruction, the address register (data Register) 000 register number “0” 001 register number “1” 010 register number “2” 011 register number “3” 100 register number “4” 101 register number “5” 110 register number “6” 111 register number “7” 3 bits are required. Therefore, the y-bit and z-bit of the bit configuration of the instruction shown in FIG. 2 are configured with 3 bits when the source operand and the destination operand are designated by registers. Which register an instruction targets is included in the operation code is included in the instruction code, and the instruction decoding unit 5 has a function of decoding the instruction code and specifying the instruction processing content and the operation target register. When the register is designated in the instruction and the register switching flag 6 is “0 (= initial value)”, the instruction decoding unit 5 causes the instruction register A in the initial state to belong to the instruction group A whose operation target is the address register 2. In this case, the address register selection signal 7 is output to the address register 2 and one of the address registers 2 is selected. Further, in the case of an instruction belonging to the instruction group B in which the data register 3 is operated in the initial state, the data register selection signal 8 is output to the data register 3 and one of the data registers 3 is selected.

On the other hand, the register switching flag 6 is set to "1 (≠
In the initial state), the instruction decoding unit 5 outputs the data register selection signal 8 to the data register 3 in the case of an instruction belonging to the instruction group A whose operation target is the address register 2 in the initial state. Select one register out of 3. Also, in the case of an instruction belonging to the instruction group B whose operation target is the data register 3 in the initial state,
The address register selection signal 7 is output to the address register 2 to select one of the address registers 2.

FIG. 3 is a diagram showing a method of using the register when the instructions of the instruction group A are executed. The instructions of the instruction group A operate on the address register in the initial state.
In the present embodiment, the above-mentioned register configuration has eight address registers and eight data registers. As an example of the instruction of the instruction group A,

[0015]

The operation of will be described. The operation of the "data transfer" instruction is an instruction to store the immediate data indicated by the source operand at a memory address offset from the value (base address) of the address register indicated by the destination operand. The data register cannot be selected as a register in order to suppress the increase in the entire instruction code. In this example, the address register number "4" is selected.

However, when the base address value originally to be stored in the address register number "4" is stored in the data register number "4" by register allocation,

[0018]

Cannot be executed. Therefore, conventionally, the following contents were executed as an example of processing. (1) Select one of the address registers and push the value of that address register to the stack area (save area, not shown). (2) Use another instruction to set the value of data register number "4" to the above. Transfer to address register (3) Use the above address register,

[0020]

Execute (4) The value of the pushed original address register is returned to the address register. In this embodiment, by enabling the register switching flag, the instruction decoding unit can change from the selection of the address register to the selection of the data register, and the address register number "4" is selected by this data transfer instruction. The number "4" is selected. The following contents are executed as an example of the process of the present embodiment. (1) Operate the register switching flag to enable register switching (2) Execute the data transfer instruction. That is, as shown in FIG. 3, instead of using the address register number “4”,
The data transfer instruction is executed using the data register number "4".

[0022]

FIG. 4 is a diagram showing how to use the registers when the instructions of the instruction group B are executed. The instructions of the instruction group B operate on the data register in the initial state. In the present embodiment, the above-mentioned register configuration has eight address registers and eight data registers. The operation of the following contents will be described as an example of the instructions of the instruction group B.

[0024]

The operation of the "logical sum" instruction is to perform a "logical sum (AND)" between the data stored in the data register indicated by the source operand and the data stored in the data register indicated by the destination operand. However, it is an instruction to store in the data register indicated by the destination operand. The address register cannot be selected as a register in order to suppress the increase of the entire instruction code. In this example, the data register number "0" is selected as the source operand and the data register number "3" is selected as the destination operand. However, when the values that should be originally stored in the data register numbers “0” and “3” are stored in the address register numbers “0” and “3” by register allocation,

[0026]

Cannot be executed. Therefore, conventionally, the following contents were executed as an example of processing. (1) Select one of the data registers and push the value of that data register to a stack area (save area, not shown). (2) Transfer the value of address register number "0" to the data register. ) Further select one of the data registers, and set the value of that data register to the stack area (save area, not shown)
(4) Using another instruction, address register number “3”
Transfer the value of to the above data register (5) Use the above two data registers,

[0028]

Execute (6) Transfer the value of the data register used as the destination to the address register number “3”. (7) Return the original value of the data register of the pushed source to the data register. (8) Data register of the pushed destination. Returns the original value of to the data register.

In the present embodiment, by enabling the register switching flag, the instruction decoding unit can change from the selection of the data register to the selection of the address register, and the data register numbers "0" and "3" are in this data transfer instruction. The address register numbers “0” and “3” are selected. The following contents are executed as an example of the process of the present embodiment. (1) Operate the register switching flag to enable register switching (2) Execute the data transfer instruction. That is, as shown in FIG. 4, instead of using the data register numbers “0” and “3”, the logical sum instruction is executed using the address register numbers “0” and “3”, and the result is the address register number “3”. 3 "
To store.

[0031]

[0032]

According to this structure, (1) by separating the register into the address / data, the number of bits for designating the register in the instruction can be small, and the increase of the instruction word length can be suppressed. (2) Each instruction It is possible to provide a register management device that can be implemented without any restriction on the type of register (address / register) that can be handled by, and that can improve program processing speed and reduce program steps.

[Brief description of drawings]

FIG. 1 is a diagram showing a configuration of a register management device of the present invention.

FIG. 2 is a diagram explaining a bit configuration of an instruction.

FIG. 3 is a diagram showing how to use a register when an instruction of instruction group A is executed.

FIG. 4 is a diagram showing how to use a register when an instruction of instruction group B is executed.

[Explanation of symbols]

 1 register 2 address register 3 data register 4 program 5 instruction decoding unit 6 register switching flag 7 address register selection signal 8 data register selection signal

Claims (1)

[Claims] 1. A first register for storing address information necessary for a CPU to operate a main memory, and the CPU.
Data retrieved from the main memory or the CPU
A second temporarily holding data to be stored in the main memory
Of the register, and when the CPU executes (1) a first instruction targeting the first register (2) a second instruction targeting the second register: (3) The first instruction operates the second register, and (4) the second instruction operates the first register, according to flags of the first register and the second register. A register management device comprising: