JPH0730411A - Pll circuit and highvision broadcasting receiver using the pll circuit - Google Patents

Abstract

PURPOSE:To approach a stationary phase error to zero without executing adjustment, to reduce circuit size and to minimize the utilization of an analog circuit element. CONSTITUTION:This PLL circuit consists of a voltage controlled frequency oscillator (VCO) 15 and a phase comparing flip flop circuit (FF) 30 for detecting a phase difference between an output signal and an input signal from/to the VCO 15 and the phase difference is controlled to zero by inputting the input signal to the CK or D terminal of the FF 30, inputting a feedback output signal from the VCO 15 to the D or CK terminal of the FF 30 and inputting a comparing output from the FF 30 to the VCO 15.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a PLL circuit used as a clock synchronizing circuit for a digital signal processing circuit, a MUSE signal receiving apparatus and the like, and a high-definition broadcast receiving apparatus using this PLL circuit.

[0002]

2. Description of the Related Art Generally, a clock of a signal processing circuit is required to be in phase with an input signal, and a PLL circuit is used so that a steady phase error becomes zero. Figure 6
Shows a basic primary loop PLL basic circuit. This circuit compares the input signal to the signal input terminal 10 and the output signal of a voltage controlled frequency oscillator (hereinafter referred to as VCO) 15 with a phase comparator 1 including a multiplier 11 and an LPF 12.
Although it is compared by 3, it is difficult to accurately match the phases. This is because the phase difference after synchronization is expressed by the following equation, but the reason why Δω approaches 0 is that there is a limit in manufacturing an analog oscillator. Steady phase error = 2 Angular frequency deviation Δω of signal / loop gain K

As a circuit for making the phase difference 0, there is an integral type loop filter 17 of a secondary loop PLL in which a loop filter is inserted. FIG. 7 shows a case where this is configured by a digital circuit. In this circuit, both the input signal to the signal input terminal 10 and the output signal from the VCO 15 are made into two pulse trains. In order to convert the phase amount into an 8-bit level (an example of quantized 8-bit), it is input to the 256-bit 8-bit counter 18, and one signal is also divided by the counter 19 to match the frequency.

Each bit output of the counter 18 is added to D of the phase comparator 20, and the signal of the counter 19 is input to CK. At the output terminal Q of the phase comparator 20, the contents of the 8-bit counter when the input signal to CK rises is output as a phase error. This form of phase comparison has the functions of a multiplier and an LPF. In such a circuit, FIG.
As described above, the integration term accumulated in the integration accumulator 22 and the constant term that governs the response are added, converted into an analog control voltage by the D / A converter 21, and passed through the amplifier 14 to VCO1.
Input to 5. The VCO control characteristic of positive polarity is shown in FIG.
When a negative phase error occurs as shown in (b), the control voltage is inverted so as to increase the VCO frequency, and the phase error is controlled to 0 as shown in FIG. 8 (c).

[0005]

In the conventional integral loop filter 17 shown in FIG. 7, accurate control is possible, but there is a problem that the circuit configuration is considerably complicated and the cost is high.

An object of the present invention is to bring the steady phase error close to zero without adjustment, and to reduce the circuit scale and minimize the use of analog circuit elements.

[0007]

SUMMARY OF THE INVENTION The present invention is a voltage-controlled frequency oscillator 1 whose frequency changes in response to a control input voltage.
5 and a phase comparison flip-flop circuit 30 for detecting the phase difference between the output signal of the voltage controlled frequency oscillator 15 and the input signal, and the input is input to the CK or D terminal of the phase comparison flip-flop circuit 30. A signal is input and D or C of the phase comparison flip-flop circuit 30 is input.
The feedback output signal of the voltage controlled frequency oscillator 15 is input to the K terminal, and the phase comparison flip-flop circuit 30 is input.
The comparison output of P is input to the voltage controlled frequency oscillator 15 so that the phase difference is controlled to 0.
It is an LL circuit.

[0008]

The basic idea of the present invention is a first-order loop PLL circuit having no loop filter. P of the primary loop
Since the LL steady phase error = Δω / K, the steady phase error in the PLL circuit of the primary loop is brought close to 0. Therefore, in the present invention, the loop gain K is made close to infinity. In order to stably increase the K, it is sufficient to handle only the MSB 1 bit of the quantized signal as a signal as a digital method. The error amount has a positive or negative polarity centered on 0, and the MSB is always amplified to the maximum level regardless of the level of the error amount by converting the MSB to 1 bit indicating the polarity. As a result, it has a stepwise phase comparison characteristic in comparison with the conventional linear phase comparison characteristic, the gain increases, and the phase error approaches zero.

[0009]

Embodiments of the present invention will be described below with reference to the drawings. The basic idea of the present invention is a primary loop PLL circuit without a loop filter. PLL of primary loop
The steady phase error in the circuit is expressed by the following equation. PLL steady phase error of the primary loop = Δω / K As can be seen from this equation, in order to bring the steady phase error in the PLL circuit of the primary loop close to 0, the loop gain K should be close to infinity or the VCO itself. There are two methods of making the difference Δω between the running oscillation angular frequency and the input signal angular frequency close to zero. As described above, there is a limit in manufacturing the analog oscillator to make Δω close to 0. Therefore, in the present invention, K is increased.

In order to stably increase the K, it is sufficient to handle only the MSB 1 bit of the quantized signal as a signal as a digital method. The error amount has a positive or negative polarity centered on 0, and the MSB shows that polarity 1
By converting to bits, it is always amplified to the maximum level regardless of the level of the error amount. As a result, it has a stepwise phase comparison characteristic in comparison with the conventional linear phase comparison characteristic, the gain increases, and the phase error approaches zero.

Specifically, FIG. 1 (a) (b) (c)
Various circuit configurations as shown in (d) are possible. In each case, a voltage-controlled frequency oscillator (hereinafter referred to as VCO) 15 whose frequency changes according to the control input voltage, and this V
Phase comparison flip-flop circuit (hereinafter referred to as FF) 30 for detecting the phase difference between the output signal of the CO 15 and the input signal
Consists of. Of these, the signal input terminal 1 is shown in FIG.
0 is connected to the CK terminal of the FF30, the output terminal Q of the FF30 (negative of Q) is connected to the input side of the VCO15, the output side of the VCO15 is connected to the output terminal 16 and the D terminal of the FF30. An example is shown.

In FIG. 1B, the signal input terminal 10 is connected to the F
Connect to the D terminal of F30, and connect the output terminal Q of FF30 to VC
An example is shown in which the output side of the VCO 15 is connected to the output terminal 16 and the CK terminal of the FF 30 is connected to the input side of the O15.

In FIG. 1C, the signal input terminal 10 is connected to the F
Connect to the CK terminal of F30, and connect the output terminal Q of FF30 to V
An example is shown in which the input side of the CO 15 is connected, the output side of the VCO 15 is connected to the output terminal 16 and the D terminal of the FF 30 is connected.

In FIG. 1D, the signal input terminal 10 is connected to the F
An example in which the output terminal Q bar of the FF 30 is connected to the input side of the VCO 15, the output side of the VCO 15 is connected to the output terminal 16, and the CK terminal of the FF 30 is connected is shown. Of these examples, Figure 1
(A) and (b) show the case where the VCO oscillation frequency characteristic has a positive slope with respect to the control input voltage, and FIG.
(D) is a case where the VCO oscillation frequency characteristic has a negative slope with respect to the control input voltage.

In such a circuit configuration, the phase comparison characteristic showing the relationship between the phase difference and the error amount becomes a linear characteristic represented by a dotted line in the conventional circuit as shown in FIG.
The circuit of the present invention has a step-like characteristic represented by a solid line. Further, the gain of the phase comparator showing the relationship between the phase difference and the gain has a linear characteristic represented by a dotted line in the conventional circuit and a step characteristic represented by a solid line in the circuit of the present invention, as shown in FIG. Becomes

That is, as shown in FIG. 4A, when the input signal to the signal input terminal 10 is sampled at the rising edge of the feedback signal from the VCO 15, the frequency changes while the input signal is "1". However, the comparison output of the FF 30 continues to be “1,” such as 1, 1, 1 ,.
As shown in (b), the input signal to the signal input terminal 10 is VC
When sampling is performed at the rising edge of the feedback signal from O15, while the input signal is "0", the comparison output of the FF30 continues to be "0" even if the frequency changes. The state of FIG. 4A and the state of FIG. 4B are alternately repeated and gradually converge to “1” “0” “1” “0” .. Becomes

Next, the PLL circuit as described above is connected to the VC
A case will be described below in which the present invention is used in a high-definition broadcast receiving apparatus that uses the horizontal synchronization of the MUSE signal as a reference signal to control the O oscillation frequency. The basic clock frequency of the MUSE system is 16.2 MHz of the sampling frequency of the MUSE signal.
It is set to 32.4 MHz for z and internal processing.
The 32.4 MHz oscillator has a voltage controlled oscillator (hereinafter referred to as VCO) 36 as shown in FIG.
In order to control the oscillation frequency of the CO 36, a PLL circuit using horizontal synchronization of the MUSE signal as a reference signal is configured.

The horizontal synchronizing signal of the MUSE signal is as shown in FIG. 10, and the horizontal reference phase point is 1 for A / D conversion.
Match the rising edge of the 6.2 MHz clock (when A / D conversion samples at the rising edge of the clock). For this reason, the above-described present invention described with reference to FIGS. 1 to 5 is used to provide a circuit configuration in which the phase error of the PLL approaches zero without adjustment. That is, the main configuration of the PLL section is
HD signal detection circuit 32 and HD polarity inversion circuit 3 shown in FIG.
3 and a phase comparator 34 composed of a phase comparison flip-flop circuit for detecting a phase difference. The output is a 1-bit pulse having a width according to the control level, and can be used as the control voltage of the VCO 36.

In the processing reference data generating circuit 39, the A / D
The 8-bit MUSE signal sampled by the conversion circuit 31 is first latched at the rising edge of the 16.2 MHz clock. This output is sent to the HD signal detection circuit 32 and is also sent to the frame synchronization circuit 38 to be processed data relating to the control signal generation timing of the internal processed signal.

In the HD signal detection circuit 32, the shift amount of the horizontal reference phase point between the MUSE original signal to be transmitted and the sampled signal is taken every other three sample values, and the average value of both ends is added. And the difference between the median value. From this value, HD detection and the amount of phase are known.

Explaining in more detail with reference to FIG. 11, assuming that the three points are S0, S2, and S4 in FIG. 11A, and the sample values at these points are Q0, Q2, and Q4, respectively.
The amount of phase shift at the point S2 is calculated by the following equation. Q2- (Q0 + Q4) / 2 This operation eliminates the influence of DC level fluctuations such as clamping in the HD section. In the HD signal detection circuit 32, the processing reference data is transferred to the 5-stage shift register by 16.2M.
Store at the falling edge of the Hz clock, first, (Q0 +
Q4) is calculated, and the upper 8 bits including the adder carry are taken and halved to obtain the average value. This result is latched on the rising edge of the clock.

Since the addition result is delayed by one clock,
The next calculation is performed between Q2 and Q3 which is delayed by one clock. Therefore, the apparent calculation of the circuit is as follows. Q3- (Q0 + Q4) / 2 These calculation processes are shown in FIG. 11 (a) (b) in the HD section.
It changes sequentially like (c), and it becomes an output like (d).

To match the reference phase point and the rising edge of the 16.2 MHz clock, that is, to reduce the phase error, the loop gain may be increased. Therefore, as shown in FIG. 11D, only the most significant bit of the output of the subtractor of the HD signal detection circuit 32 is taken, and the 1-bit quantization is "0" when the phase amount is positive and "1" when the phase amount is negative. The value is expanded by doing. As a result, the relative gain of the phase comparison in the vicinity of the reference phase point dramatically increases as shown in FIG. 3, and the phase adjustment is performed even in the present invention circuit of the primary loop PLL which does not have the perfect integral loop filter. A steady phase error of 0 is obtained, which does not require a detector. In FIG. 9, 35 is a filter, 3
Reference numeral 7 is a frequency dividing circuit, and 40 is a control circuit.

[0024]

EFFECTS OF THE INVENTION (1) Since the VCO control signal is binary, the conversion between positive and negative gradients is easy, and the troublesome D / A conversion is not required. (2) No special amplifier is required to increase the loop gain. (3) The steady phase error can be practically set to zero. (4) The number of circuit components is extremely small, the operation is stable, and the cost is low. (5) The phase difference can be brought close to 0 without adjustment. (6) The synchronization speed is sufficiently faster than before.

[Brief description of drawings]

FIG. 1 is a block diagram showing first, second, third and fourth embodiments of a PLL circuit according to the present invention.

FIG. 2 is a phase comparison characteristic diagram showing a relationship between a phase difference and an error amount.

FIG. 3 is a gain characteristic diagram of a comparator showing a relationship between a phase difference and a gain.

FIG. 4 is a waveform diagram of each part when there is a phase difference.

FIG. 5 is a waveform diagram of each part when the phase difference is 0.

FIG. 6 is a block diagram of a conventional PLL circuit.

FIG. 7 is a block diagram of a conventional perfect integration type PLL circuit.

8 is a waveform diagram of the circuit of FIG.

FIG. 9 is a block diagram when the PLL circuit of the present invention is used in a high-definition broadcast receiving apparatus.

10 is a horizontal synchronization HD waveform diagram in FIG. 9.

FIG. 11 is an explanatory diagram showing a process of calculating a phase amount in FIG. 9.

[Explanation of symbols]

10 ... Signal input terminal, 11 ... Multiplier, 12 ... LPF, 1
3 ... Phase comparator, 14 ... Amplifier, 15 ... Voltage control type frequency oscillator (VCO), 16 ... Output terminal, 17 ... Integral type loop filter, 18 ... Counter, 19 ... Counter, 20
... phase comparator, 21 ... D / A converter, 22 ... integral accumulator, 30 ... phase comparison flip-flop circuit (FF),
31 ... A / D conversion circuit, 32 ... HD signal detection circuit, 33
HD polarity inversion circuit, 34 phase detector, 35 filter, 36 voltage control oscillator (VCO), 37 frequency division circuit, 38 frame synchronization circuit, 39 processing reference data generation circuit, 40 control circuit .

 ─────────────────────────────────────────────────── ─── Continuation of the front page (72) Inventor Fumitaka Asami 1015 Kamiodanaka, Nakahara-ku, Kawasaki-shi, Kanagawa Fujitsu Limited

Claims (2)

[Claims] 1. A voltage control type frequency oscillator 15 whose frequency changes according to a control input voltage, and a phase comparison flip-flop circuit for detecting a phase difference between an output signal and an input signal of the voltage control type frequency oscillator 15. CK or D of the phase comparison flip-flop circuit 30.
The input signal is input to the terminal, the feedback output signal of the voltage controlled frequency oscillator 15 is input to the D or CK terminal of the phase comparison flip-flop circuit 30, and the comparison output of the phase comparison flip-flop circuit 30 is input. A PLL circuit characterized in that the phase difference is controlled to 0 by inputting it to a voltage controlled frequency oscillator 15. 2. An external voltage control type frequency oscillator 36.
In a high-definition broadcast receiving apparatus that uses the horizontal synchronization of the MUSE signal as a reference signal to control the oscillation frequency of
A voltage control type frequency oscillator 36 whose frequency changes in accordance with a control input voltage for phase comparison of a USE input signal and an output signal of the voltage control type frequency oscillator 36 and control of the voltage control type frequency oscillator 36, and this voltage control Type frequency oscillator 36 and a phase comparator 34 composed of a phase comparison flip-flop circuit for detecting the phase difference between the input signal and the CK or D of the phase comparator 34.
The input signal is input to the terminal, the feedback output signal of the voltage control type frequency oscillator 36 is input to the D or CK terminal of the phase comparator 34, and the comparison output of the phase comparator 34 is input to the voltage control type frequency oscillator 36. A high-definition broadcast receiving apparatus comprising a PLL circuit configured to control the phase difference to 0 by inputting to the.