JPH0336472B2 - - Google Patents

Description

Detailed Description of the Invention (Technical Field) The present invention provides a horizontal synchronization signal necessary to stably and reliably lock the clock phase when generating a clock for an image signal processing system for an image signal subjected to dot interlacing. waveform and its insertion.

(Prior art) In general, synchronization signals such as frame synchronization pulses and horizontal synchronization signals are applied to image signals subsampled by dot interlacing, or clock signals are used to receive and accurately reproduce such image signals. Regarding generation, unless the image signal subsampled by dot interlacing is resampled at accurate timing on the receiving side, it is impossible to reproduce the original image signal to a practical extent. Therefore, on the receiving side, it is necessary to generate a synchronizing signal that is accurately phase-locked with the various synchronizing signals mentioned above that are added to the image signal on the transmitting side. Furthermore, the clock signal that drives this type of image signal processing system must be phase-synchronized with the dot interlace with much higher precision than the sub-sampling period of the dot interlace.

To perform accurate phase locking on this clock signal, it is desirable to perform continuous synchronization control using burst signals with a large number of waves. It is undesirable to increase the image information signal from the viewpoint of transmission efficiency.

In addition, even if the signal generation timing of the synchronization signal generator itself provided on the receiving side is accurate, the synchronization signal generator and the sampler that performs resampling to accurately reproduce the received image signal If a phase drift exists between the two, highly accurate phase locking cannot be expected at all.

Furthermore, in order to avoid narrowing the dynamic range of the image signal processing system due to so-called synchronization loss, a positive polarity synchronization method is used for the synchronization signal added to the image signal, in which the synchronization signal is added with the same polarity as the image information signal. It is desirable to do so.

The waveform of the horizontal synchronizing signal that solved these above-mentioned problems is the clock phase method proposed by the present inventors in Japanese Patent Application No. 58-093359, as shown in FIG. 1C.
There is. The waveform of this horizontal synchronizing signal is that after the 0 level continues for several clock periods (L level), there is an N/4 level (M level) for one clock period, and then the N/2 level continues for several clock periods. (H level), and then the image information signal continues completely. Here, the N level is the highest level of the dynamic range of the image signal.

The step-like horizontal synchronizing signal waveform shown by the solid line in FIG. 1C is smoothed as shown by the dotted line due to the restriction of the transmission band of the transmission path during image signal transmission. This smoothed horizontal synchronizing signal waveform is processed by the phase detector shown in FIG.
A point at level N/4, which is the middle point between level 0 and level N/2, is detected, and the rising waveform of the horizontal synchronizing signal inside the receiving side is locked to this point.

However, in the horizontal synchronizing signal described in Japanese Patent Application No. 58-093359, a phase error appears when a level clip occurs in the transmission path. In other words, as shown in Fig. 3, when point A at level 0 changes to point A' by level clipping, the midpoint of the level moves to point C'', and the internal horizontal synchronizing signal that is locked to point C'' is originally There is a phase lag with respect to the phase of the horizontal synchronization signal. When point B at level N/2 is level clipped to point B', the phase advances conversely. In addition, since all lines have the same polarity, phase errors will occur if the transmission line is affected by amplitude distortion or non-linearity.

(Summary of the Invention) An object of the present invention is to eliminate the above-mentioned conventional drawbacks, and to stably and reliably adjust the phase of the horizontal synchronization signal added to the image signal on the transmitting side using a relatively simple and inexpensive circuit configuration on the receiving side. A horizontal synchronization signal insertion method that can generate a locked internal horizontal synchronization signal and improve the phase accuracy of the clock pulse for resampling the image signal generated based on the internal horizontal synchronization signal. It is about providing.

That is, in the horizontal synchronization signal insertion method of the present invention, a frame synchronization pulse and a horizontal synchronization signal are added to a television image signal subsampled by dot interlacing and transmitted, and on the receiving side, the phase is adjusted by the frame synchronization pulse and the horizontal synchronization signal. control to form an internal horizontal synchronization signal, control the phase using the internal horizontal synchronization signal to form a clock pulse, and resample the subsampled and transmitted television image signal using the clock pulse to reproduce the original image signal. In the sub-sample transmission method, the horizontal synchronization signal is a positive synchronization type horizontal synchronization signal having the same polarity as the image signal, and when the highest level of the Danamitsu range of the image signal is set to N level, the horizontal synchronization signal is transmitted every horizontal synchronization period. M level approximately equal to the N/2 level for a predetermined period of one clock period, and continuously for the same plurality of clock periods before and after the predetermined period of one clock period, respectively. During the i-th horizontal synchronization period, which is a positive integer, from the M level within the level range exceeding the 0 level and less than the N/2 level and within the level range exceeding the N/2 level and less than the N level. Signal waveforms with L level and H level that are oppositely polarized by equal levels are given, and during the (i+1)th horizontal synchronization period, the signal waveforms are within the level range exceeding the N/2 level and less than the N level. and signal waveforms are provided for the H level and the L level, which are spaced apart from the M level by equal levels and opposite polarities within a level range exceeding the 0 level and less than the N/2 level. It is something to do.

(Example) The present invention will be described in detail below with reference to the drawings.

An example of a combination of a horizontal synchronizing signal and an image signal according to the present invention is shown in FIG. 4, and details of the horizontal synchronizing signal according to the present invention are shown in FIG.

In FIG. 4, the horizontal synchronizing signal of the present invention is as follows: N/4 level is several clocks, N/2 level is one clock,
The 3N/4 level continues for several clocks, and this level is located in the center of the dynamic range of the image signal. Therefore, phase errors in the horizontal synchronizing signal do not occur due to level clipping due to non-linearity of the amplifier. In addition, in order to reduce the influence of nonlinearity in the transmission path, Fig. 5 a and Fig. 5 c
As shown in , if the polarity of the horizontal synchronization signal is inverted for each horizontal line, and the average of the alternating inversions of multiple horizontal synchronization signals (generally an even number) is,
Errors due to non-linearity are also averaged out.

This received horizontal synchronization signal is supplied to the phase detection circuit shown in FIG. 2, as described in the prior art section above. For example, a received horizontal synchronizing signal is supplied to a circuit in which two delay circuits each having a delay time of two clock cycles are connected, and the signal A at both ends is
and B to an adder, and 1/2 of the adder output
is led to the subtracter, and the signal C at the midpoint of the two series delay circuits is also led to the subtracter to obtain a phase detection output signal in the form of A+B/2-C. That is, in the circuit configuration shown in the second diagram, the signal waveforms A, B, and C of the horizontal synchronizing signals appearing at both ends and the midpoint of the two delay circuits 1 and 2 connected in series are as shown in 1 and 4 in the sixth diagram. The sum 1/2 of the signals A and B at both ends, that is, A+B/2, has the waveforms shown in Figures 2 and 5, and the difference output signal waveform of the subtractor 4 has the waveforms shown in Figures 3 and 6. Become. That is,
This becomes the phase detection output signal. If the waveform of this phase detection output signal is sampled at the leading edge of the internal horizontal synchronizing signal, the phase of the transmitted horizontal synchronizing signal and the internal horizontal synchronizing signal will match at the point where the sample value becomes 0. Further, if there is a phase difference between the two, this sample value will not be 0, and moreover, its positive and negative polarities will be reversed every horizontal synchronization period.

Therefore, the reproduced horizontal synchronization signal used as the phase reference of the reproduced clock signal used for resampling the dot interlaced image signal on the receiving side is as follows.
Generally, the rising phase of the horizontal synchronization signal extracted from the received signal is disturbed due to noise addition or waveform distortion during transmission, so a voltage-controlled crystal oscillator is used on the receiving side to stabilize it. It is common practice to form an internal horizontal synchronization signal with the correct waveform and match its phase to the phase of the horizontal synchronization signal extracted from the received signal. Since it is difficult to control the output phase significantly and precisely, an internal horizontal synchronization signal generated by approximately controlling the crystal oscillation phase using the frame synchronization pulse and horizontal synchronization signal extracted from the reception signal is extracted from the reception signal. The phase error of the phase comparison result is zero by comparing the phase with the extracted horizontal synchronizing signal over multiple periods and averaging the above-mentioned individual rising phase disturbances included in the extracted horizontal synchronizing signal. It is common to precisely control the phase of a voltage controlled crystal oscillator so that

Therefore, the polarity is reversed every other horizontal synchronization period, and the internal horizontal The synchronization signal is precisely phase-locked to the transmitted horizontal synchronization signal, and a clock signal is generated based on this precisely phase-locked internal horizontal synchronization signal, and the transmitted sub-sampled image signal is resampled in a timely manner. By doing so, the original image signal can be faithfully reproduced.

Next, when the horizontal synchronization signal is transmitted through a transmission line, etc.
FIG. 7 shows the state when the level is clipped.

The level of the horizontal synchronizing signal on the i-th line is level-clipped as A', B', and C' as shown in FIG. 7a, and the horizontal synchronizing signal on the (i+1)th line is As shown in the figure, when levels are clipped as A'', B'', and C'', the outputs of A+B/2 become as shown in b and e in the figure, respectively.

The phase detection output signals A+B/2-C are as shown in c and f of the figure, respectively. From this,
By performing alternating polarity inversion addition of sample values of the horizontal synchronization signal phase detection output signal over a plurality of horizontal synchronization periods, generally an even number, as described above with reference to FIG. 6, the phase error due to level clip is averaged out. removed.

Next, a case where the horizontal synchronizing signal is affected by nonlinearity of an amplifier or the like in a transmission path will be described using FIG. 8 as an example.

When the horizontal synchronization signal is affected by nonlinear distortion as shown in a and d of the same figure, the output of A+B/2 becomes as shown in b and e of the same figure, and the phase detection output A+B/2-C becomes as shown in c and e of the same figure. It becomes like f. Therefore, by performing alternating polarity inversion addition of horizontal synchronization signal phase detection output signal sample values over even horizontal synchronization periods as described above, phase errors based on nonlinear distortion can also be averaged and removed.

Note that the level clip and nonlinear distortion mentioned above regularly occur due to the characteristics of the transmission path, so the received horizontal synchronization signal is uniformly affected by them, and the horizontal synchronization signal that maintains its original correct phase is In general, synchronization signals do not mix together, and even if they do, there is no way for the receiving side to distinguish between them, so they are treated as the same as the others.
As mentioned above, it is necessary to find the average of multiple phase errors, and the horizontal synchronization signal that maintains the original correct phase can be distinguished from others only when the original correct phase is known. Obtaining the phase error itself becomes meaningless.

Next, FIG. 9 shows an example of the configuration of a horizontal synchronizing signal phase lock circuit according to the method of the present invention using the above-mentioned phase detector. In the illustrated configuration, an image signal subjected to subsampling by dot interlacing is digitized by an analog-to-digital converter 12, and the converted output digital image signal is supplied to a frame pulse detector 13 to detect a frame synchronization pulse. A frame synchronization pulse in the received image signal or an internal frame synchronization pulse from an internal synchronization generator (to be described later) is guided to the horizontal synchronization gate circuit 14 via a switch S, and a frame is generated from the above-mentioned converted output digital image signal. The image signal portion of the section including the horizontal synchronization signal following the synchronization pulse is guided to the horizontal synchronization detector 15 to detect the horizontal synchronization signal. The horizontal synchronization signal and the above-mentioned frame synchronization pulse are sent to the internal synchronization generator 16.
to generate an internal horizontal synchronization signal that is phase-locked to those input synchronization pulses and synchronization signals. Thereafter, the internal horizontal synchronizing signal is guided to the phase detector 17, and as described above with reference to FIGS. , and detect the phase difference between the two, and the phase difference is
The oscillation output pulse train, which is applied to the voltage controlled oscillator 20 via the adder 19 and has an oscillation frequency that changes according to the phase difference, is supplied as a clock pulse to the analog-to-digital converter 12 to perform sampling of the input image signal, etc. Controls the timing of conversion operations. Therefore, for the oscillation output pulse train of the voltage controlled oscillator 20 in the circuit device shown in FIG.
The horizontal synchronization signal at the A/D conversion output of the input image signal is phase-locked, and as a result, it can be extracted as a clock pulse train phase-locked to the digital image signal.

In the illustrated circuit configuration, the phase difference information from the phase detector 17 is transmitted to the voltage controlled oscillator 20.
By feedback to the input image signal and phase-synchronizing the clock pulse of the oscillation output and the horizontal synchronizing signal of the digital image signal using loop control, it is possible to precisely lock the clock phase with respect to the subsampling dot interlace applied to the input image signal. However, when a crystal-controlled voltage-controlled oscillator is used, a residual phase offset occurs permanently. If the loop control gain is increased to such an extent that the residual phase offset can be ignored, hunting will occur in the loop control system and it will become unstable. It is integrated with a relatively long time constant of about the frame period, and when the integrated value exceeds the tolerance range, the polarity is set to pull it back within the tolerance range, and the adder 19 adds it to the detected output phase difference. , automatically adjusts the residual offset.

In addition, the frame synchronization pulse supplied to the horizontal period gate circuit 14 via the switch S is an internally generated frame synchronization pulse when the operation of the loop control system is stable, but the phase difference between the horizontal synchronization signals is extremely large. or, in addition,
Frame synchronization pulses detected from the received image signal are directly provided only when the internally generated ones are out of timing.

In the embodiments described above, the A level of the horizontal synchronizing signal shown in FIGS. 4 and 5 is N/4 or 3N/4, the C level is N/2, and the B level is 3N/4 or N/4. However, the present invention is not limited to this example, and the C level may be approximately the N/2 level, the A and B levels may be equidistant from the C level, and may be between the 0 level and the N level, respectively. .

(Effects) As is clear from the above explanation, according to the present invention, the system horizontal clock is used as a reference for phase locking of the system clock when resampling and image processing an image signal subsampled by dot interlacing. The phase of the synchronization signal can be precisely locked to the transmitted horizontal synchronization signal without being affected by amplitude distortion of the transmission path or nonlinearity of the amplifier, so it is suitable for application to various image processing. .

[Brief explanation of the drawing]

Figures 1 a to c are waveform diagrams showing the configurations of the frame synchronization pulse and horizontal synchronization signal of the earlier application, Figure 2 is the phase detection circuit used in the earlier application and the present invention, and Figure 3 is the horizontal synchronization signal of the earlier application. FIG. 4 is a diagram showing an embodiment of the combination of the horizontal synchronizing signal and image signal of the present invention, and FIG. 5 is a diagram showing the waveform of the horizontal synchronizing signal of the present invention. FIG. 6 is a diagram showing one example in detail, and FIG. 7 is a diagram showing the detection output waveform of the horizontal synchronizing signal phase detection circuit.
The figure shows how the horizontal synchronizing signal is level-clipped, FIG. 8 shows how the horizontal synchronizing signal is subjected to nonlinear distortion, and FIG. 9 shows how the horizontal synchronizing signal is subjected to nonlinear distortion.
FIG. 3 is a block diagram of a horizontal synchronizing signal phase lock circuit. 1, 2... 2 clock delay circuit, 3... Adder, 4... Subtractor, 5... Luminance signal (Y, Y'),
6...Low range (C _WL ) of broadband color signal components, 7...
...High band in wideband color signal component (C _WH ), 8...Narrowband color signal component (C _N ), 9...Frame synchronization pulse (only at the beginning of one frame), 10...Horizontal synchronization signal, 11... ...Image information.

Claims (1)

[Claims] 1 A frame synchronization pulse and a horizontal synchronization signal are added to a television image signal subsampled by dot interlacing and transmitted, and on the receiving side, the phase is controlled by the frame synchronization pulse and the horizontal synchronization signal to form an internal horizontal synchronization signal. In the sub-sampling transmission method, a clock pulse is formed by controlling the phase with the internal horizontal synchronization signal, and the sub-sampled and transmitted television image signal is resampled by the clock pulse to reproduce the original image signal. When the signal is a positive polarity synchronous horizontal synchronization signal that has the same polarity as the image signal, and the highest level of the dynamic range of the image signal is set to N level,
Continuing for a period of one predetermined clock cycle in each horizontal synchronization cycle, the M level is approximately equal to the N/2 level;
During the i-th horizontal synchronization period, where i is a positive integer, the clock signal exceeds the 0 level and becomes N/2 continuously during the same plurality of clock periods, respectively, before and after the predetermined period of one clock period. The M
L level and H level signal waveforms are provided with opposite polarity distances from each other by an equal level, and during the (i+1)th horizontal synchronization period, the level exceeds the N/2 level and is less than the N level. Signal waveforms are provided for the H level and the L level, which are oppositely polarized and spaced apart from the M level by an equal level within the range and within a level range exceeding the 0 level and less than the N/2 level. Characteristic horizontal synchronization signal insertion method.