JPH0730073A - Semiconductor device and manufacturing method thereof - Google Patents

Abstract

PURPOSE:To provide the title semiconductor device and manufacturing method thereof capable of rapidly reading-out and writing-in bit data in the structure optimum for high density integration. CONSTITUTION:Within the title semiconductor device composed of an n<+> source region 7, the first n<-> channel region 5, a barrier layer 6, the second n<-> channel region 5', a pair of n<+> drain regions 2 and insulating films 4 and electrodes 3 opposite to a pair of drain regions, an accumulated electric capacitor is formed of the drain regions 2 and the metallic electrodes 3; a source electrode 10 is formed beneath an N<+> substrate crystal 8; and the bit data are ultra- rapidly written-in and read-out by the tunnel effect of the barrier layer 6.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention is applied to a logic integrated circuit or a semiconductor memory of an electronic computer or its main storage device, OA equipment, personal computer, game equipment or the like, and particularly high-speed read / write and high density. The present invention relates to a semiconductor device having a structure suitable for integration. Furthermore, the present invention relates to a manufacturing method for forming an optimum potential barrier, which is used for manufacturing a semiconductor device having a potential barrier that can be controlled by an external bias.

[0002]

2. Description of the Related Art High speed and high integration of semiconductor devices have been rapidly progressing in recent years. In particular, with regard to high integration of semiconductor memory, mass production of 16 Mbit memory has already started with conventional technology, and a prototype of 64 Mbit memory has been announced. However, the current MOS type (MOS: me
tal oxide semiconductor) or VMOS type (V-groo
If the structure of a semiconductor memory based on (vemetal oxide semiconductor) is miniaturized as it is, the number of electrons contributing to the operation of the memory will decrease and the noise level will be approached, making it difficult to control the operation of the semiconductor memory. Become. This is a serious problem in the vicinity of the 64 Gbit memory in which the number of electrons contributing to the operation is about 100 or less, but it is not limited to the semiconductor memory, but is also a problem of the device affected by the number of operating electrons.

In order to solve such a problem, the present inventor has already found that static induction transistor (SIT: Static Inducti).
on Transistor) has been proposed as a semiconductor memory device using basic memory cells (IEEE JOURNAL OF SOLID-STATE CI).
RCUITS, VOL.SC-13, NO. 5, OCTOBER 1978, p 622, `` Hi
gh Speed and High Density Static Induction Transis
tor Memory ”). The SIT memory is classified into two-terminal memory (ping-pon memory (ping-pon memory (ping-pon memory
g memory)) and three-terminal memory (purse memory (purse me
mory)), and semiconductor memory basically has the following three types according to the storage form of information. That is, a serial memory or a shift register, a random access memory (RAM), and a read only memory (ROM). In the above document, the inventor teaches that SIT can be used to configure the above three types of memories. In these SIT memories, it is easy to make a three-dimensional structure by embedding a part of the memory structure inside the semiconductor substrate.
The integration degree can be increased several times as compared with the MOS type or VMOS type memory currently used. Also, S
Since the IT memory is bulk conduction rather than surface conduction, it is extremely fast, and its low power consumption allows it to have a large capacity.

[0004]

However, the SIT
Even in a ping-pong memory or a parse memory of a memory, the retention characteristic of accumulated information depends on the intrinsic gate potential height determined by the difference between the Fermi level near the MOS capacitor on the drain region which is the accumulation region and the potential of the source region. Therefore, in the electron storage type memory, if electrons are essentially stored, the potential rises, and the height of the intrinsic gate potential decreases accordingly, so that the leak current increases and the retention characteristic deteriorates. Therefore, in order to improve the retention characteristics, it is sufficient to apply a reverse gate bias in advance, but a higher voltage is required at the time of writing / reading.

On the contrary, in the electron depletion type memory, contrary to the electron storage type memory, the more the charge is held, the lower the potential and the higher the intrinsic gate potential are. The speed is slower than that of the electronic storage type memory.

Furthermore, since the principle SIT memories are driving surface storage electric capacitance in static induction transistor, n ^- channel region n ^- p ⁺ gate formed in an island shape so as channel region is pinched off A region needs to be formed. This SIT memory controls an intrinsic gate potential formed between an n ⁺ source region formed at a position opposed to an n ⁺ drain region formed between p ⁺ gate regions to thereby form an accumulation region and a source region. It controls carrier transport between. That is, in the gate floating two-terminal configuration, the electrostatic induction effect by the voltage applied to the surface electrode, and in the three-terminal configuration,
It is based on the electrostatic induction effect by the voltage applied to the surface electrode and the intrinsic gate potential control by the external gate voltage. Therefore, in the conventional SIT memory, since carrier transport between the storage region and the source region by the intrinsic gate potential control is determined by the Boltzmann law, there is room for improvement in order to perform a higher speed and lower noise operation.

Also in the transistor, for example, in a npn-type bipolar transistor, a neutral region remains in the junction barrier layer. FIG. 1 shows the potential distribution of the npn-type bipolar transistor. In FIG. 1, since a flat portion remains in the potential of the barrier layer top portion 1, no electric field is applied. Therefore, during the operation of the semiconductor memory, when the carriers are accumulated from the source region to the accumulation region and the carriers are extracted from the accumulation region to the source region by the write / read operation, carriers such as electrons are generated in a portion where the potential of the barrier layer is flat. Must be transmitted by diffusion, and there is a limit to high speed operation. Further, since the neutral region exists, the height and width of the potential barrier cannot be controlled by the electrostatic induction effect. Therefore, there is room for improvement so that the transistor can operate at higher speed than the conventional transistor.

In order to form a semiconductor device such as the above-mentioned memory, it is necessary to use a crystal growth method having a molecular layer order film thickness controllability of a semiconductor crystal and a position controllability. In addition, since the impurity distribution and the crystal composition must be sharply controlled with about one molecular layer of the crystal,
Requires low temperature growth and low temperature manufacturing processes. Crystal growth methods that meet this requirement include the molecular beam epitaxial growth method (MBE), the MOCVD method, and the molecular layer epitaxial growth method (MLE) developed by the inventors of the present application.

Molecular beam epitaxial growth method (MBE)
Although is a so-called vapor deposition method and has a film thickness controllability of about one molecular layer, its growth process does not guarantee molecular layer growth in principle. Moreover, in order to obtain a good quality crystal, the growth temperature is higher by at least about 200 ° C. than in the molecular layer epitaxial growth method. In the case of GaAs, the Debye temperature is about 360 K in the temperature range of 140 K or higher, so that the difference of the process temperature of 200 ° C. has a great influence on the occurrence of defects. Moreover, MO using an organometallic gas
In the CVD method, an appropriate low temperature process temperature and a film thickness / composition controllability of about one molecular layer are required, so that it is difficult to sequentially form an excellent ultrathin layer in practice.

Therefore, the MLE method, which allows the crystal growth of each monolayer at a low temperature, is suitable. However, when the metal electrode is formed after the crystal growth of about one monolayer, the metal electrode is taken out from the MLE apparatus and then surface-treated. The electrodes are formed by the vapor deposition method. That is, since there is a step of exposing to air, an oxide film grows on the semiconductor surface, so there is room for improvement in the method of forming a good-quality metal-semiconductor contact.

In order to solve such a problem, a first object of the present invention is to provide a semiconductor device capable of controlling a potential barrier formed inside by an external electric field and operating at an ultrahigh speed. Secondly, it is an object of the present invention to provide a low noise and low power consumption semiconductor device which can operate at an ultra-high speed and can improve the retention characteristic of accumulated charges, and can perform high-speed reading / writing. The third purpose is pnp or np depending on the external electric field.
An object of the present invention is to provide a semiconductor device which can control an n-junction barrier and operates at an extremely high speed. A fourth purpose is to make a semiconductor contact with a good quality metal or semiconductor electrode, and
It is an object of the present invention to provide a method for manufacturing a semiconductor device in which a gate mesa portion is formed by low temperature etching.

[0012]

In order to achieve these objects, in the semiconductor device of the invention according to claim 1 corresponding to the first object, a source region, a channel region and a drain region are formed on a semiconductor substrate. In a semiconductor device having an insulating layer and an electrode, an extremely thin barrier layer whose potential can be controlled by supplying an external voltage is sandwiched in a channel region between a source region and a drain region.

According to a second aspect of the semiconductor device of the present invention, in a semiconductor memory having a source region, a channel region, a drain region, a charge storage layer, an insulating layer and an electrode on a semiconductor substrate, The channel region between the source region and the drain region has an extremely thin barrier layer whose potential can be controlled by the supply of an external voltage.

A semiconductor device according to a third aspect of the invention corresponding to the third object is a semiconductor device having a structure in which a drain region, a barrier layer, and a source region are laminated, and the barrier layer is an extremely thin layer. A depletion region is formed in the formed and stacked structure to form a structure without a metallurgical channel region. A semiconductor device according to a fourth aspect of the present invention includes a source region, a first channel region, an ultrathin barrier layer, a second channel region, a drain region, an insulating layer, and an electrode on a semiconductor substrate, and the drain region. And the distance of the intrinsic gate potential saddle formed by the ultra-thin barrier layer is less than the mean free path.

In the semiconductor device corresponding to the first, second or third object, the semiconductor device according to the invention of claim 5 has a structure in which the barrier layer has an extremely thin homojunction structure. Further, the semiconductor device of the invention according to claim 6 is
The barrier layer has an ultrathin heterojunction structure.
According to a seventh aspect of the semiconductor device of the present invention, the barrier layer is formed of an extremely thin insulating layer. Furthermore, the semiconductor device according to the eighth aspect of the invention has a structure in which the barrier layer is formed of an ultrathin heterojunction and has a quantum well potential.

According to a fourth aspect of the present invention, there is provided a method of manufacturing a semiconductor device, comprising: a first step of forming a source region and a second step of forming a first channel region on a semiconductor substrate. Steps corresponding to the third step of forming the barrier layer, the fourth step of forming the second channel region, the fifth step of forming the drain region, the sixth step of forming the insulating layer, and the drain region. It has a seventh step of forming a surface electrode and an eighth step of forming a source electrode, and the seventh step and the ninth step of forming an electrode are performed in-situ without being taken out from the growth apparatus. The process has a structure in which metal deposition and / or low-resistance semiconductor deposition are selectively performed.

In the case of the semiconductor device manufacturing method including the step of forming the gate mesa portion, the light irradiation low temperature etching step is provided on the spot. In this structure, the molecular layer is etched by chlorine gas adsorbed on the surface of the GaAs crystal substrate. Further, the GaAs crystal substrate is subjected to surface treatment in an AsH ₃ atmosphere at a specific temperature in a step before the step of forming the source region.

[0018]

In the semiconductor device having such a structure, the depletion region is formed in the ultrathin barrier layer, and the height and width of the potential of the ultrathin barrier layer are controlled by the external electric field. In addition, the ultra-thin barrier layer serves as a tunnel barrier layer that causes a tunnel phenomenon.

As a result, carriers move in the intrinsic gate region formed by the tunnel barrier layer by a tunnel phenomenon, so that high-speed reading / writing can be performed. Moreover, since the tunnel phenomenon is used, the noise is low, so that the device can operate even if the number of electrons contributing to the operation is reduced. Furthermore, since carriers are moved by the tunnel phenomenon, low power consumption operation can be essentially performed.

In the case of a semiconductor memory that stores carriers,
The leakage current of carriers accumulated due to the potential of the ultra-thin barrier layer disappears. Further, the height and width of the potential of the ultra-thin barrier layer are controlled, and a tunnel phenomenon occurs. As a result, the accumulated carriers move in the intrinsic gate region formed by the tunnel barrier layer by a tunnel phenomenon, so that high-speed read / write can be performed.

In the structure in which the quantum well-like potential distribution is formed, the gate potential is controlled by the gate bias voltage, and when the quantization levels formed in the gate region coincide with each other, tunnel transition probability occurs and charges are transferred. . Since this is a quantum phenomenon, in principle, the response time can be expected up to the limit of the observable time range by the uncertainty principle. Since charges are transferred by the tunnel phenomenon, bit information can be cut off and held with a very small leak current when the quantization levels in the gate regions do not match.

At the npn or pnp junction of the drain region, the barrier layer, and the source region with the ultrathin barrier layer sandwiched, there is a depletion layer satisfying the charge neutrality condition without the channel layer. It becomes a substantial channel layer. The height and width of this depletion region can be controlled by an external electric field. As a result, a semiconductor device that operates at a very high speed and can be highly integrated can be obtained.

If, for example, the drain region is used as a charge storage region and the distance between the drain storage region and the intrinsic gate potential saddle formed by the tunnel barrier layer is set equal to or less than the mean free path of carriers, the carriers stored in the storage region are stored. Does not reach the intrinsic gate region by a diffusion phenomenon, but reaches by, for example, varistic conduction. This makes it possible to increase the amount of change in the current value due to the change in the potential height of the barrier layer even if the structure does not pass through the potential of the barrier layer due to the tunnel phenomenon, thereby improving the operation speed of the semiconductor device. Further, the semiconductor device can be highly integrated, and a sufficient signal can be obtained even if the number of accumulated carriers is reduced.

In the method of manufacturing a semiconductor device according to the present invention, the step of forming an electrode is not taken out from the growth apparatus, and the metal deposition and the low resistance semiconductor deposition are selectively performed in-situ.
Alternatively, since both are performed, the step of exposing to air is eliminated. As a result, no oxide film is formed on the crystal-grown surface, and good-quality electrode semiconductor contact can be made.

Further, in the method of manufacturing a semiconductor device for forming a gate mesa portion, the process of forming the gate mesa portion is not taken out from the growth apparatus, but light irradiation low temperature etching is selectively performed on the spot, so that an npn of about a molecular layer is formed. It can be etched without damaging the structure or damaging the formed sidewalls. Further, as a step prior to the step of forming the source region, surface treatment is performed in an AsH ₃ atmosphere so that a good growth interface can be obtained without destroying the ultrathin npn structure of the molecular layer level.

[0026]

Embodiments of the semiconductor device of the present invention will be described below in detail with reference to the drawings. The first embodiment is a two-terminal memory provided with the barrier layer of the present invention. Figure 2
FIG. 3 is a sectional view showing the structure of the first embodiment. In this embodiment, an n ⁺ -GaAs crystal is used as the semiconductor substrate. 2, this semiconductor device, which are sequentially stacked on n ⁺ substrate crystal 8, an n ⁺ source region 7, the first n ^- a channel region 5, a barrier layer 6, a second n ^-
A channel region 5 ', a pair of n ⁺ drain regions 2,
It has an insulating film 4 and an electrode 3 facing a pair of drain regions. The drain region 2 and the metal electrode 3 form a storage capacitance, and the source electrode 10 is formed on the lower surface of the n ⁺ substrate crystal 8. ing.

The n ⁺ drain region 2 has a carrier density of, for example, 5 × 10 ¹⁸ / cc with selenium added, and has a thickness of about several hundred Å. The first n ^- channel region 5 is about 1500 Å, and the second n ^- channel region 5'is 30.
0 Å and both carrier densities are 1 × 10 ¹⁷ / c
It is formed of a high-purity growth layer of about c or less. Barrier layer 6
Has a carrier density of about 1 × 10 ¹⁹ / cc and a thickness of several Å to several tens of Å. The n ⁺ source region 7 has a carrier density of, for example, 5 × 10 ¹⁸ / cc with selenium added, and has a thickness of several hundred Å to several thousand Å. n ⁺ substrate crystal 8 is 2 × 1
Silicon-doped GaA with carrier density of 0 ¹⁸ / cc
s substrate crystal is used. The source electrode 10 is an n-type Ga.
Any structure that makes good low resistance metal-semiconductor contacts to As crystals is applied. For example, it is AuGe / Ni / Au or the like which is conventionally well applied.

Next, the manufacturing process of this semiconductor device will be described. In order to form this semiconductor device, a crystal growth method having film thickness controllability and position controllability of about one molecular layer must be used. In addition, since the impurity distribution and the crystal composition have to be steeply controlled to form a single molecular layer of a crystal, a low molecular weight epitaxial growth method (MLE: molecular layer epitaxial growth method) capable of low temperature growth and low temperature manufacturing processes.
layer epitaxy). This molecular layer epitaxial growth method is applicable not only to compound semiconductor crystals such as GaAs described below but also to silicon. In addition, a metal organic chemical vapor deposition method using a metal organic gas (MOCVD: metal o
Crystal growth is also possible by rganic chemical vapor deposition), but appropriate low temperature process temperature and film thickness / composition controllability of about one molecular layer are required.

Taking the basic configuration sectional view of FIG. 2 as an example, ML
An example of the manufacturing process by the E method is shown below. On the n ⁺ -GaAs substrate crystal 8 having the {100} plane, for example, about 50
After forming the n ⁺ source region 7 of about 00Å, the first n ⁻ channel region 5 of about 1500Å and the p ^{+ of} several molecular layers.
A barrier layer 6 which is a barrier layer is formed. Further, a second n ⁻ channel region 5 ′ having a thickness of several hundred Å is formed, and an npn structure is continuously grown. Se, for example, is used as an impurity added to the drain region 2 and the source region 7, which are n ⁺ layers. As the source gas, for example, DESe is used, and is introduced after AsH _{3 in} the molecular layer epitaxial growth. Typically, the growth temperature is about 420 ° C. The carrier density is
When grown by the MLE method, a high-concentration n-type conductive layer of 5 × 10 ¹⁸ / cc or a contact layer of about 4 × 10 ¹⁹ / cc can be obtained. In the case of this embodiment, for example, 5 × 10
An impurity doped layer of ¹⁸ / cc is formed.

The barrier layer 6 which is a p ⁺ barrier layer uses, for example, Zn, Be or C as an additive impurity. As the raw material gas, for example, DEZn, DEBe or the like is used. For C, molecular layer epitaxial growth is performed using TMG and AsH _3, and C from TMG is used as it is as an acceptor impurity. The amount of C mixed can be controlled by growing conditions. Incidentally, TMG may be mixed in during the epitaxial growth of the molecular layer using TEG and AsH ₃ . In the case of the present embodiment, for example, the carrier density is 1.5 × 10 ¹⁹ / cc and 1
A 6Å p ⁺ barrier layer is formed. At this time, the two-dimensional carrier density is 2.4 × 10 ¹² / cm ² , and the barrier height is about 0.8 eV.

After forming the npn structure as described above, the insulating film 4 is formed at a low temperature by, for example, a silicon nitride film, a window is opened by a normal photolithography process, and the n ⁺ drain region 2 is formed by regrowth. One of the features of the molecular layer epitaxial growth method is that silicon nitride film and GaA
s Crystal selectivity. That is, no GaAs crystal is deposited on the silicon nitride film. The silicon nitride film may be used as it is as the insulating film 4 of the storage capacitance as long as it has a good interface and a sufficiently small surface recombination rate.

If the interface defect density is high, the insulating film 4
With a large forbidden band width, such as AlGaAs or Zn
It is also possible to use a thin film crystal such as Se. AlGaAs
In the case of 1, the interface can be further improved by adding P and matching the lattice constant with GaAs. After that, MIS (metal insulator semiconductor)
Alternatively, in order to form a MOS (metal oxide semiconductor) capacitor, the insulating film 4 at a position corresponding to the drain region 2 is thinned to form a metal electrode 3 to be a capacitor electrode.

Finally, a good low resistance metal contact is made to the n-type GaAs crystal, eg AuGe / Ni / A.
The u-type source electrode 10 is deposited. However, the conventional AuGe / Ni / Au-based metal-semiconductor contact is
When formed by a vapor deposition method, a thick alloy layer which is not suitable for the ultra-thin multilayer semiconductor structure of about one molecular layer of the present invention may be formed without intentional alloying. Further, if the electrode is formed after the crystal growth after being surface-treated after being taken out into the air, it is impossible to expect good-quality metal-semiconductor contact.

Therefore, it is suitable for the constitution of the present invention to employ a step of selectively performing metal deposition in situ after epitaxially growing the ultrathin multilayer semiconductor structure. The source electrode 10 is formed by selective deposition of aluminum by introducing an organometallic gas of aluminum, such as triisobutylaluminum or dimethylaluminum hydride.
Should be formed. In these organometallic metals of aluminum, the metal is selectively deposited only on the GaAs crystal surface at a low temperature of about 200 ° C., so that it is suitable for the process of the ultrathin multilayer semiconductor structure having a thickness of about one molecular layer of the present invention. There is.

When there is a subsequent temperature raising process such as regrowth, a refractory metal such as W or Mo is used. Also in this case, when an organic metal gas source such as tungsten or molybdenum such as tungsten hexacarbonyl is used,
Since metal deposition can be performed at a low temperature of 500 ° C. or less, it is suitable for the process of the present invention for forming an ultrathin multilayer semiconductor structure having a thickness of about one molecular layer. Of course, tungsten fluoride monosilane or As used in the conventional silicon process is used.
Tungsten deposition by H ₃ reduction is also applicable. Also important in the case of low-resistance metal-semiconductor contact by metal deposition is the semiconductor surface state immediately before deposition, which seriously affects the coverage and the electrical characteristics.

In this embodiment, the structure on the n ⁺ substrate crystal is shown, but it is very effective to form on the high resistance substrate especially for reducing the parasitic capacitance.

Next, the operation of the first embodiment will be described. Referring to FIG. 2, the second channel region 5'is completely pinched off by the diffusion potential between the barrier layer 6 serving as the p ⁺ gate and the second n ^- channel region 5'or a constant reverse gate bias voltage. In the case of, the electrons accumulated in the n-type drain region 2 are retained because they are surrounded by the wall of the potential corresponding to the diffusion potential or the reverse gate bias voltage, and the memory operation becomes possible. At this time, the drain region 2 serves as one electrode of the storage capacitance.

FIG. 3 is a schematic view showing the potential distributions of the channel center AA 'section and the BB' section passing through the drain region in FIG. In FIG. 3, the dotted line is the potential distribution along the center of the n-type channel regions 5 and 5 ′, and the solid line is the potential distribution along the region including the drain region 2. When a positive write pulse voltage is applied to the metal electrode 3 on the surface, the potential distribution changes due to the electrostatic induction effect by the drain voltage of SIT. Therefore, the electrons in the n ⁺ source region 7 exceed the potential 9 to rapidly charge the surface storage capacitance, and the Fermi level and the potential distribution change in the direction of higher energy because the electrons are stored. Therefore, the write time constant is determined by the MOS capacitor and the resistance of the npn structure. Although the npn structure is used in this embodiment, the structure is not limited to this, and an element structure of opposite conductivity type may be used.

Next, the write / read operation when the semiconductor device of the present invention is used as a two-terminal memory will be described in detail. FIG. 4 is a conceptual diagram showing changes in the potential distribution during writing and reading operations. When the bias voltage is not applied in the initial state (FIG. 4A), the Fermi levels of the semiconductor side and the surface metal electrode 3 coincide with each other, and the peaks of the potential barrier 9 of the barrier layer 6 exist. When the write positive voltage pulse is applied to the surface metal electrode 3, the potential of the surface metal electrode 3 is lowered relative to the semiconductor side as shown by the arrow (FIG. 4B), and as a result, the semiconductor Since the height of the potential 9 of the side barrier layer 6 decreases and the width of the potential also narrows, the tunnel transition probability increases, and electrons are injected from the source region to the surface accumulation region by the tunnel phenomenon, resulting in a write operation. Ends.

When electrons are accumulated in the accumulation region just below the surface insulating layer 4, the potential of the accumulation region is raised due to the existence of electrons as shown in FIG. 4 (c). However, the barrier layer 6
The potential 9 causes no leak current, and the stored information can be well retained. Next, when a negative bias voltage pulse is applied to the surface electrode 3, the potential of the surface metal electrode 3 rises relatively to the semiconductor side, and at the same time, the height of the potential 9 of the barrier layer 6 seen from the charge storage layer is increased. Since the width can be reduced and the width can be narrowed, the read operation is completed at an ultrahigh speed by tunneling the carriers from the charge storage layer to the source side.

As described above, in the two-terminal memory, since the structure has the ultra-thin barrier layer which can be controlled by the external voltage, carriers move in the intrinsic gate region formed by the tunnel barrier layer by the tunnel phenomenon, so that the high speed is achieved. Can read and write. Moreover, since the tunnel phenomenon is used, the noise is low, so that the device can operate even if the number of electrons contributing to the operation is reduced. Furthermore, since carriers are moved by the tunnel phenomenon, low power consumption operation can be essentially performed.

Next, the second embodiment will be described. The second embodiment is an application of the barrier layer of the present invention to a two-terminal memory as a heterojunction structure. FIG. 5 is a sectional view showing the structure of the second embodiment. In FIG. 5, the barrier layer 6 of the first embodiment has an ultrathin heterojunction structure made of different materials, and the rest is the same as that of the first embodiment.

A manufacturing process of a semiconductor device having this ultrathin hetero structure will be described. The channel layers 5 and 5'are
For GaAs as described in the first embodiment, it can be as a barrier layer, for example, Al _X Ga _1-X As and ZnSe layer is applied. Here, x is an Al composition. GaAs and Al _x Ga
_{Since 1-X} As has different lattice constants, lattice strain occurs at the bonded interface. In order to eliminate the lattice strain in order to prevent the occurrence of defects due to the lattice strain, for example, several percent is added to the Al _X Ga _1-X As layer.
The lattice strain at the heterojunction interface can be eliminated by adding P to form Al _X Ga _1-X As _Y P _1-Y .

The material of the channel layer and the barrier layer is not limited to the GaAs material. In, which has a higher electron mobility than GaAs
A material having various forbidden bands such as an As-based material and having a forbidden band larger than the forbidden band width of the semiconductor material of the channel layers 5 and 5 ^′ may be used as the barrier layer material, and preferably the channel layer material and the barrier layer. It is required that the layer material crystals have close lattice constants and crystal systems.

The lattice constant and the crystal system do not necessarily have to be the same. For example, silicon is a diamond-type crystal system, GaAs and ZnSe are the same as the diamond crystal system, in which different elements are alternately arranged, but the wurtz-type crystal material or Si found in ZnSe formed at high temperature or Si.
C hexagonal material and a certain plane orientation, for example, {11
It is possible to match in the 1} plane. Therefore, for example, when the channel layer is silicon, the heterojunction barrier layer can be a SiC or GaAs layer.

Next, an example of a manufacturing process for forming the barrier layer 6 by a heterojunction is shown below. The n ⁺ GaAs substrate crystal 8 surface having a {100} plane is heated to about 480 ° C. in an AsH ₃ atmosphere in a crystal growth chamber to remove a contaminant layer such as surface oxides and carbides and at the same time obtain a good surface. After that, for example, an n ⁺ source region 7 of about 5000 Å is formed, and then a first n ⁻ channel region 5 of about 1500 Å is formed. Removal of surface oxides, etc., is more effective at higher temperatures, but at temperatures above about 480 ° C, the risk of destroying ultra-thin multi-layered structures, such as molecular layers, increases, so use low-temperature surface treatment. Is desirable.

The n ⁺ source region is a molecular layer epitaxial growth method by alternately introducing gallium organometallic gas such as TEG (triethylgallium) or TMG (trimethylgallium) or gallium chloride such as gallium trichloride and AsH ₃ (arsine). During the gas introduction sequence of
Se (diethyl selenium) gas is introduced, for example, after introducing AsH ₃ . Typically the substrate temperature is 200-600 ° C
Although it is about the degree, 480 ° C. or lower is desirable. At this time, when light irradiation in the ultraviolet region such as a high-pressure mercury lamp is performed, the surface migration of the surface-adsorbed species due to heat cannot be expected due to the low temperature growth, but the surface migration is activated by the light energy so that the crystal It is possible to improve the property. The substrate temperature is selected as an optimum temperature for surface adsorption and surface reaction of the introduced gas, and does not have to be a constant temperature.

The carrier density in that case can be controlled by the DESe gas introduction pressure and the introduction time. Typically,
A high-concentration impurity-added layer of about 5 × 10 ¹⁸ / cc to 1 × 10 ²⁰ / cc or more is applied. In order to reduce the effective drain / source distance, a high-concentration impurity-doped layer is required for the n ⁺ source and drain regions,
It is desirable that a so-called δ or digitally doped layer of 1 × 10 ²⁰ / cc or more can be applied. The impurity gas that imparts n-type conductivity to the crystal growth layer is not limited to DESe, but DETe, which is an organometallic compound of Te that is a group VI element, can be applied.

The formation of the n ^- channel layer is performed by TEG and the like and A
It is formed by molecular layer epitaxial growth in which no impurity gas is intentionally added by alternately introducing sH ₃ . In this case, the conductivity type is usually n-type. In order to control the electron concentration more precisely, a small amount of silicon is added by introducing a silicon compound gas such as Si ₂ H ₆ (disilane) or SiH ₄ (monosilane). The introduction of the silicon compound gas is performed after the introduction of TEG. Also in this case, the substrate temperature is typically selected to be the optimum temperature for the surface reaction of the introduced gas, and does not have to be a constant temperature.

Next, a heterojunction barrier layer is formed. A
To form the 1GaAs heterojunction barrier layer, first, an aluminum organometallic gas such as DMAlH (dimethylaluminum hydride), TlBAl (triisobutylaluminum) or TMAl (trimethylaluminum) is introduced from another gas introduction nozzle simultaneously with TEG or the like. . T
The composition of Ga and Al adsorbed on the surface is controlled by the ratio of the introduction gas pressure and the introduction time of EG and these aluminum organometallic gases, and the subsequent introduction of AsH ₃ introduces monomolecular AlG.
An aAs layer is formed.

Usually, when impurities are not intentionally added,
It is typically a p-type conductive layer, but of course p
II such as Zn, Mg or Be for obtaining type conductivity II
Controllability can be improved by adding an impurity gas of a group element. As the impurity source gas, DEZn (diethyl zinc), Mg (Cp) ₂ (dicyclopentazinyl magnesium), DEBe (diethyl beryllium), or the like is used. Also in this case, the substrate temperature is typically about 480 ° C. or lower. The substrate temperature is selected as an optimum temperature for surface adsorption and surface reaction of the introduced gas, and does not have to be a constant temperature.

Another example of the process for forming the heterojunction barrier layer by the molecular layer epitaxial growth method is Ga such as TEG.
After GaAs molecular layer formed by alternately introducing the source gas and the AsH _3, a step of forming alternating AlAs molecular layer by alternately introducing the aluminum source gas and the AsH ₃ such TIBAl. In this case as well, usually, when impurities are not intentionally added, a p-type conductive layer is typically formed in many cases. Of course, in order to obtain p-type conductivity, an impurity gas of a Group II element such as Zn, Mg, or Be is used. The controllability can be improved by adding. DEZn, Mg (Cp) ₂ , DEBe and the like are similarly used as the impurity source gas. Also in this case, typically, the substrate temperature of about 480 ° C. or lower is desirable. The substrate temperature is selected as an optimum temperature for surface adsorption and surface reaction of the introduced gas, and does not have to be a constant temperature.

After forming the heterojunction barrier layer as described above, for example, the second n ^- channel layer 5 of about 300 Å is formed.
^' Is formed by alternate introduction of TEG and AsH ₃ . After that, the formation of the n ⁺ drain region, the formation of the insulating layer, the formation of the metal electrode, and the like are performed in the same manner as the process shown in the first embodiment.

The first and second n ^- channel layers need not actually have a finite metallurgical thickness. That is, in the npn structure of the n ⁺ drain region / p ⁺ barrier layer / n ⁺ source region, the n ⁺ drain region / p ⁺ barrier layer junction and the p ⁺ barrier layer / n ⁺ source region junction are actually n ^−. Even if there is no channel layer, a depletion layer exists so as to satisfy the charge neutrality condition, and the depletion region becomes a substantial channel layer.

For example, n ⁺ drain region / p ⁺ barrier layer /
As the structure of the n ⁺ source region, n ^- without providing a channel layer, p ⁺ barrier layer p = 9 × 10 ¹⁹ / cc high-concentration doped layer 36Å of and n ⁺ drain region and n,
^{When the +} source region is formed in a region of 5 × 10 ¹⁹ / cc and about 500 Å, a substantial channel layer of several tens of Å is formed due to depletion of both junctions. FIG. 7 shows an example of the device structure without the channel layer.

In the case of a GaAs-based crystal material, an example using AsH ₃ as the arsenic source gas is shown.
Not only ₃ but also arsenic organometallic gas with less toxicity can be applied. Further, TEIn (triethylindium), TMIn (trimethylindium), or the like is used as a source gas when an indium-based crystal material is used. In the case of silicon-based crystal material, SiH ₂ CI ₂
The silicon molecule layer epitaxial growth layer can be formed by alternate introduction of (dichlorosilane) and hydrogen, alternate introduction of dichlorosilane and monosilane, or the like. In the case of a ZnSe-based crystal material, DEZn and H ₂ Se (selenium hydride) or DEZn and DESe are used as the source gas.

Next, the operation of the second embodiment will be described. FIG. 6 is a diagram showing a potential distribution when the barrier layer 6 is formed of an ultrathin hetero barrier. When the barrier layer is formed of the ultrathin heterobarrier, the potential of the valence band of the ultrathin heterobarrier extends beyond the transmission band as shown in FIG. With reference to FIGS. 2 and 6, the surface electrode 3
When a positive write pulse voltage is applied to, the potential distribution changes due to the electrostatic induction effect due to the drain voltage of SIT, so that the electrons in the source region 7 have potential 9
Through the tunnel phenomenon to rapidly charge the surface storage capacity, and the Fermi energy level and potential distribution change toward higher energy due to the accumulation of electrons. Therefore, the write time constant is determined by the MOS capacitor and the resistance of the npn structure.

The amount of electric charge accumulated in the capacitor corresponds to the difference in Fermi level between the drain region 2 and the source region 7. Since this difference and the height of the heterobarrier determine the height of the intrinsic gate of the npn structure, the amount of the current component flowing over the intrinsic gate in the leak current in the accumulated state is determined. That is, the retention characteristic of the memory is affected.

In the electron storage type memory, the potential of the storage region is essentially increased, so that the current component flowing beyond the potential 9 which is the intrinsic gate is considered to be large, but the retention characteristic is good because of the presence of the hetero barrier. It will be Here, if the height of the potential 9 of the intrinsic gate is made higher by applying the reverse gate bias voltage, the leak current is further reduced and the retention characteristic of the memory is improved.

In a normal SIT memory, when the reverse gate bias is applied, the writing / reading speed becomes slower with the same pulse voltage, so the writing / reading voltage needs to be made higher, but the writing / reading is performed by the tunnel phenomenon through the hetero barrier. Because it does, it can be done at high speed. As described above, the ping-pong memory, which is a two-terminal memory, has a simple structure and is easy to operate, and thus is suitable for a large-capacity memory structure.

Next, a third embodiment in which the present invention is applied to a three-terminal memory will be described. FIG. 8 is a sectional view of a three-terminal structure in the third embodiment. In FIG. 8, except for the gate region 11 ′ and the gate electrode 11, it is the same as the first embodiment.
In this embodiment, the gate region 11 'forms an n ⁺ / i / p ⁺ structure from the side wall of the channel. N of the gate region 11 '
^{The +} layer is extremely thin and only a few molecular layers thick. The n ⁺ layer of the gate region 11 'is, for example, selenium-added 4 × 10 ¹⁹ / cc
It has a carrier density of. The i layer of the gate region 11 ′ is a high-purity growth layer similar to that used for the channel region 5, and a thickness of about 100 Å is sufficient.

The p ⁺ layer of the gate region 11 'is formed of a Zn-added layer in this embodiment and has a carrier density of 6 × 10 ¹⁹ / c.
It is enough that the thickness is about c and the thickness is about 100Å. For the gate region 11 ', any combination of metals that can form a low resistance metal semiconductor contact to GaAs with the gate metal can be applied. In this example, Ti / Pt / Au was used.

It has been reported that the Ti / Pt / Au electrode structure acts as a barrier metal that prevents Pt from entering the semiconductor side of Au. However, in reality, it is difficult to completely prevent the diffusion of Au and the like, and it is not desirable to form a high-quality interface in the structure by the vapor deposition method. Therefore, even in this electrode configuration, the in-situ metal deposition step following the epitaxial process as described in the source electrode section is suitable for the step of the present invention for forming an ultrathin multilayer semiconductor structure having a thickness of about one molecular layer. . In the structure of the present invention shown in FIG. 8, since extremely thin layers are laminated in multiple layers, heat treatment at high temperature cannot be performed. Therefore, the metal electrodes such as the source electrode 10 and the gate electrode 11 are formed by non-alloying treatment. In this embodiment, the high-concentration p ⁺ barrier layer 6 forms a tunnel barrier layer for carriers in the drain accumulation region.

The manufacturing process by the MLE method will be described by taking the configuration sectional view of FIG. 8 as an example. The manufacturing process of the two-terminal type memory according to the first embodiment is almost the same as that of the three-terminal type memory structure according to the third embodiment, except that a gate region 11 'described below is formed. There is. First, a gate mesa portion is formed by a normal photolithography technique. The gate mesa depth is approximately the depth at which the gate region is connected to the p ⁺ barrier layer 6. Drain / intrinsic gate distance is tens to
The molecular layer etching method is effective because it becomes a very shallow depth of several hundred Å. For example, chlorine gas is adsorbed on the surface at a low temperature near 0 ° C., and ultraviolet irradiation is performed, so that the gate mesa region can be formed with a controllability of about one molecular layer. The sidewalls are anisotropically etched with good selectivity. This method is a low damage process because it is at a low temperature and there is no ion bombardment such as plasma. Therefore, it is most suitable for the device structure formation having a very thin multi-layer thin film structure of about several Å together with the molecular layer epitaxial growth method.

After forming the gate mesa region, the gate is formed again.
Region 11 'is formed by regrowth. The gate region 11 'is
For example, just p⁺It may be homozygous. Side wall of npn structure
Side to n⁺Or p as i layer⁺-i-n⁺Joining game
The gut structure is also applicable. p⁺6x10 layers¹⁹/ Cc
Carrier density is about 100Å, i layer is 1 × 10 ¹⁶/ C
c is about 100Å, and n⁺4x10 layers¹⁹/
It is a few molecular layers at about cc. 6 × 1 containing a large amount of impurities
0¹⁹/ Cc p⁺When the crystallinity of the layer deteriorates, p⁺Layers
5 x 10¹⁸/ Cc layer of about 250Å and 6 × 10¹⁹/
p of about cc⁺⁺It has a two-layer structure of 100 Å.

In order to prevent the gate / source or gate / drain junction from being broken down by tunnel injection, an i-GaAs layer of about 100 Å is sufficient. To further improve the junction characteristics, the gate regrowth is performed after forming an insulating layer such as a silicon nitride film on the side wall of the gate. The insulating layer on the side wall of the gate contributes to the improvement of the withstand voltage between the heavily doped source region and the gate region. In addition, AlG by molecular layer epitaxial growth method
An aAs hetero gate or MIS gate is applied. In either case, the structure may be such that the tunnel barrier width or height can be controlled by the electrostatic induction effect.

Next, the operation of the third embodiment will be described. Referring to FIG. 8, by applying to the extent of or removal lowers the potential existing in the channel region 5 'during the write time and read memory operation a pulse voltage to the gate 11, the barrier layer is a p ⁺ barrier layer By reducing the barrier height or effective barrier width of 6 to reduce the resistance of the npn structure at the time of writing / reading, it is possible to configure a memory that operates at a higher speed than a ping-pong memory having a two-terminal configuration. Further, by applying a pulse voltage to the gate 11, the barrier layer 6 to be a tunnel barrier layer
It is possible to increase / decrease the tunnel transition probability and reduce the resistance of the npn structure to write / read bit information in the drain side accumulation region.

In order to improve the retention characteristic of the memory cell, a reverse gate bias voltage is applied in the electron accumulation state,
By applying a gate pulse voltage that cancels the reverse gate voltage during reading / writing, high-speed operation can be performed without increasing the writing / reading voltage. Further, by applying an appropriate gate bias, the tunnel transition probability of the heterobarrier can be reduced and the write / read operation can be performed.

Not only is the gate potential formed of a single p ⁺ barrier layer as in the first embodiment or a hetero barrier layer as in the second embodiment, but it is also possible to use, for example, a double hetero barrier or np ⁺ np ^+. Multiple structure p ⁺
If the barrier layer is used as the barrier layer, the retention characteristics of the carriers accumulated in the drain side storage capacitor can be written / read out only when the external gate voltage matches the tunnel transition of the multiple quantum well. Like This will be described in detail as a fourth embodiment.

In the fourth embodiment, the quantum well layer is formed by using the barrier layer 6 shown in FIG. 8 as an ultrathin heterostructure having two different thicknesses. Other configurations are similar to those of the third embodiment. The operation of the semiconductor device having the multiple quantum well structure according to the fourth embodiment will be described below. FIG. 9 is a potential diagram of the multiple quantum well structure. In FIG. 9, the solid line shows the potential distribution and the resonance level at zero bias,
The dotted line shows the potential distribution and resonance level when an external bias voltage is applied. As shown in FIG. 9, the quantized level (or resonance level) formed in the quantum well-like potential 12 is an intrinsic energy level E _n determined by a function of the quantum well width L _Z and the order _n. Have. Therefore, by determining the appropriate quantum well widths L _Z1 and L _Z2 , different quantization levels E _n1 and E _n2 can be formed in the first quantum well and the second quantum well, respectively.

In the initial state, E _n1 (quantization level shown by 14 in FIG. 9) and E _n2 (quantization level shown by 16 in FIG. 9) do not match, so that there is almost no tunnel transition probability and carrier flow. Does not occur. For example, by applying a positive write voltage pulse to the surface metal electrode 3 to lower the potential 10 of the surface metal electrode, the barrier layer 6 is electrostatically induced.
When the potential 12 of is reduced, the quantized levels E _n1 (quantized level shown by 14 in FIG. 9) and E _n2 (resonated level shown by 18 in FIG. 9) formed in each quantum well are Coincidence, the tunnel transition probability of potential 10 increases,
Electrons flow from the source region to the surface accumulation region and accumulate,
The write operation is complete. Even if the surface potential rises as a result of the completion of the write operation and the accumulation of electrons on the surface, the quantized level E formed in each quantum well
_n1 (quantization level indicated by 14 in FIG. 9) and E _n2 (16 in FIG. 9)
Quantization level (1) does not match, so that there is almost no leak current flowing through the barrier layer 6 and good retention characteristics can be obtained.

Next, a negative read voltage pulse is applied to the surface metal electrode 3 or a positive read voltage pulse is applied to the source electrode so that the potential 10 of the surface metal electrode 3 is relative to the semiconductor side. , The quantization level E _n1 (14 in FIG. 9) formed in each quantum well again.
Quantization level) and E _n2 (resonance level 18 in FIG. 9) coincide with each other, and the tunnel transition probability of the potential 9 of the barrier layer 6 is generated. The movement occurs due to the tunnel phenomenon, and the read operation can be performed at extremely high speed.

Next, a fifth embodiment will be described. The barrier layer 6 shown in FIG. 8 is a homojunction to form a three-terminal transistor. The homozygosity is the same as in the first embodiment.
In this embodiment, the saddle portion distance L of the potential 9 (see FIG. 10) of the intrinsic gate region formed by the drain accumulation region 2 and the tunnel barrier layer 6 shown in FIG. 8 is set to be equal to or less than the mean free path of carriers. . It is desirable that the n ^- channel layers 5 and 5'be as pure as possible and have no defects so as not to be scattered by impurities and the like. In the case of GaAs, the distance between the drain storage layer 2 and the tunnel barrier layer changes depending on the carrier density of the n ⁻ channel layer 5 ′ between them, but the carrier density is about 1 × 10 ¹⁴ / cc or less to about 1 × 10 ¹⁷ / cc. It is about tens to hundreds of Å.

Next, the operation of the fifth embodiment will be described. FIG. 10 shows a potential distribution diagram showing the operation and energy distribution of electrons. In FIG. 10, a hatched region 22 shows the relationship between electron energy and momentum. When a voltage is applied to the gate electrode 11, the height and width of the potential 9 can be controlled, and the accumulated electrons 20 move over the peak of the potential 9. Since the carriers accumulated in the accumulation region do not reach the intrinsic gate region by a diffusion phenomenon but reach by the ballistic conduction, the writing / reading speed is further improved. In the case of this embodiment, even if the structure does not pass through the barrier layer by the tunnel, the amount of change in the current value due to the change in the height of the potential barrier is a normal bipolar transistor (BPT).
It can be made much larger than
A sufficient signal can be obtained even if the number of carriers stored in the unit memory cell is reduced.

That is, in the structure of this embodiment, the barrier layer 6 is depleted, and carriers are accumulated from the source region to the accumulation region and carriers are accumulated from the accumulation region to the source region in the write / read operation during the operation of the semiconductor memory. At the time of drawing out, carriers such as electrons move in the barrier layer due to drift due to the internal electric field, so that high speed operation is possible. Further, the height and width of the potential 9 of the barrier layer can be controlled by the electrostatic induction effect. The above is the operation as a transistor, but the semiconductor memory is composed of a combination of a storage capacitor and a transistor, and the operation speed thereof is determined by the charge / discharge time constant of the storage capacity of the transistor, enabling high-speed operation of the semiconductor memory. .

The semiconductor device having the structure of this embodiment is
Since reading and writing are transmitted by the tunnel phenomenon, they are ultimately transmitted at high speed within the observable time range by the uncertainty principle. Thermionic emission type S as a memory cell
When IT is used, the amount of change in current due to a change in gate potential is large at a low bias voltage. Therefore, even if the number of electrons contributing to the operation is reduced by miniaturization, the noise level itself is the same as that of a conventional bipolar transistor (BPT: bipolar).
transistor)), but operates without being buried in the noise level. Also, a dynamic memory that destructively reads and writes bit information can be configured,
A static memory that can read and write while holding bit information can also be configured.

Next, a sixth embodiment will be described. In this embodiment, the barrier layer 6 in the third embodiment is composed of an extremely thin insulating layer, and the other structures are the same as those in the third embodiment. This ultra-thin insulating layer is formed to have a thickness of about 1 to 150 Å. In that case, it is particularly important to reduce the interface defect density. With an ultrathin layer of this degree, the potential distribution in the insulating layer can be controlled by applying a voltage to the gate electrode 11. Therefore, the operation / effect in this embodiment is similar to that in the fifth embodiment.
Have an effect.

Next, a seventh embodiment will be described. As shown in FIG. 2 and FIG. 8, the structure so far is composed of a MOS capacitor having a drain region 2 which is a high-concentration impurity-added layer and a metal electrode 3 with an insulating film 4 having a thin storage capacitance interposed therebetween. However, not only the metal electrode but also the electric field effect due to the structure of the semiconductor / insulating film / drain layer with high concentration
It is possible to store bit information. In either configuration, the writing / reading operation of the accumulated bit information is performed at an extremely high speed by the tunnel phenomenon through the ultra-thin tunnel barrier layer arranged in the immediate vicinity of the accumulation layer, and the tunnel barrier layer obtains good retention characteristics. To be

[0079]

As is clear from the above description, in the semiconductor device of the present invention, the depletion region is formed in the ultrathin barrier layer, and the height and width of the potential of the ultrathin barrier layer can be controlled by the external electric field. Also, the ultra-thin barrier layer becomes a tunnel barrier layer that causes a tunnel phenomenon. As a result, carriers move in the intrinsic gate region formed by the tunnel barrier layer by a tunnel phenomenon, so that high-speed read / write can be performed. Moreover, since the tunnel phenomenon is used, the noise is low, so that the device can operate even if the number of electrons contributing to the operation is reduced. further,
Since the carrier is moved by the tunnel phenomenon, it is possible to operate with low power consumption.

When the semiconductor memory for accumulating carriers is constructed, there is an effect that the leak current of the accumulated carriers can be eliminated by the potential of the ultrathin barrier layer. Further, since the height and width of the potential of the ultra-thin barrier layer can be controlled to cause a tunnel phenomenon, the accumulated carriers move in the intrinsic gate region formed in the tunnel barrier layer by the tunnel phenomenon, and thus high-speed read / write is possible. It has the effect that it can.

In the configuration in which the quantum well-like potential distribution is formed, the gate potential can be controlled by the gate bias voltage, and when the quantization levels formed in the gate region are matched with each other, tunnel transition probability occurs and charge transfer occurs. It has the effect that Since this is a quantum phenomenon, in principle, the response time can be shortened to the limit of the observable time range by the uncertainty principle. Since charges are transferred by the tunnel phenomenon, when the quantization levels in the gate regions do not match, there is an effect that bit information can be blocked / held with a very small leak current.

In a semiconductor device having an npn or pnp junction of a drain region, a barrier layer, and a source region with an ultrathin barrier layer sandwiched between them, there is a depletion layer satisfying the charge neutrality condition even without a channel layer. The converted region can be a substantial channel layer. Since the height and width of the potential of the depletion region can be controlled by an external electric field, the depletion region can operate at a very high speed and can be highly integrated.

In a semiconductor device in which the drain region is, for example, a charge storage region, and the distance between the drain storage region and the intrinsic gate potential saddle formed by the tunnel barrier layer is about the mean free path of carriers or less, the charge is stored in the storage region. The generated carriers can reach the intrinsic gate region by diffusion conduction, for example, instead of reaching by diffusion phenomenon. By this, even if the structure does not pass through the potential of the barrier layer by the tunnel phenomenon,
This has the effect that the amount of change in the current value due to the change in the potential height of the barrier layer can be increased and the operating speed of the semiconductor device can be improved. In addition, the semiconductor device can be highly integrated, and a sufficient signal can be obtained even if the number of accumulated carriers occurs.

In the method of manufacturing a semiconductor device, the step of forming an electrode is not taken out from the growth apparatus, and the metal deposition and / or the low-resistance semiconductor deposition are selectively performed on the spot, so that the step of exposing to air is eliminated. You can This has the effect that no oxide film is formed on the crystal-grown surface and a good-quality electrode semiconductor contact can be formed.

Further, in the method of manufacturing a semiconductor device for forming the gate mesa portion, the step of forming the gate mesa portion is not taken out from the growth apparatus, and light irradiation low temperature etching is selectively performed in-situ to obtain a layer of about a molecular layer. This has an effect of not damaging the npn structure and damaging the formed sidewall.

Further, by treating the surface in an AsH ₃ atmosphere as a pre-step of the step of forming the source region, it is possible to obtain a good growth interface without destroying the ultra-thin npn structure of about molecular layer. Have an effect.

[Brief description of drawings]

FIG. 1 is a potential distribution diagram of an npn-type bipolar transistor.

FIG. 2 is a sectional view showing the configuration of the first exemplary embodiment of the present invention.

3 is a schematic diagram showing potential distributions of a channel center AA ′ cross section and a BB ′ cross section passing through a drain region in FIG.

4A is a conceptual diagram showing a potential distribution of a two-terminal memory in an initial state in which a bias voltage is zero, FIG. 4B is a schematic diagram showing changes in the potential distribution during a write operation of the two-terminal memory, and FIG. 6A is a schematic diagram showing a potential distribution of a charge accumulation state of the two-terminal memory, and FIG. 9D is a schematic diagram showing a change of the potential distribution during a read operation of the two-terminal memory.

FIG. 5 is a sectional view showing a configuration of a second exemplary embodiment of the present invention.

FIG. 6 is a schematic diagram showing a potential distribution when a tunnel barrier layer is formed of an ultrathin hetero barrier in the second embodiment.

FIG. 7 is a cross-sectional view of a device structure without channels.

FIG. 8 is a sectional view showing a configuration of a third exemplary embodiment of the present invention.

FIG. 9 is a diagram showing changes in the potential distribution of the quantum well structure when a zero bias and an external bias are applied according to the fourth embodiment of the present invention.

FIG. 10 is a potential distribution diagram when the distance between the intrinsic gate potential saddle portion formed by the drain accumulation region and the tunnel barrier layer is set to about the average free path of carriers or less.

[Explanation of symbols]

2 n ⁺ drain region 3 metal fourth insulating film 5,5 'n ^- channel 6 barrier layer 7 n ⁺ source regions 8 n ⁺ substrate crystal 9 intrinsic gate region of the potential 10 source electrode 11 gate electrode 11' gate region

Claims (13)

[Claims] 1. In a semiconductor device having a source region, a channel region, a drain region, an insulating layer and an electrode on a semiconductor substrate, a channel region between the source region and the drain region is supplied with an external voltage. A semiconductor device having an extremely thin barrier layer sandwiched between potentials. 2. In a semiconductor memory having a source region, a channel region, a drain region, a charge storage layer, an insulating layer, and an electrode on a semiconductor substrate, a channel region between the source region and the drain region, A semiconductor device having an ultrathin barrier layer sandwiched between potentials which can be controlled by supplying an external voltage. 3. A semiconductor device having a structure in which a drain region, a barrier layer, and a source region are stacked, wherein the barrier layer is formed of an extremely thin layer, and a metallurgical channel region is formed in the stacked structure. A semiconductor device characterized by the absence thereof. 4. A source region is sequentially formed on the semiconductor substrate,
The intrinsic gate potential saddle portion having the first channel region, the ultra-thin barrier layer, the second channel region, the drain region, the insulating layer, and the electrode, and the intrinsic gate potential saddle portion formed by the drain region and the ultra-thin barrier layer. A semiconductor device characterized in that the distance is formed to be less than the mean free path. 5. The semiconductor device according to claim 1, 2, 3, or 4, wherein the barrier layer has an ultrathin homojunction structure. 6. The semiconductor device according to claim 1, 2, 3, or 4, wherein the barrier layer has an ultrathin heterojunction structure. 7. The semiconductor device according to claim 1, wherein the barrier layer is formed of an extremely thin insulating layer. 8. The semiconductor device according to claim 1, 2, 3 or 4, wherein the barrier layer is formed of an ultrathin heterojunction and forms a quantum well potential. 9. A first step of forming a source region, a second step of forming a first channel region, a third step of forming a barrier layer, and a second channel on a semiconductor substrate. A fourth step of forming a region, a fifth step of forming a drain region, a sixth step of forming an insulating layer, a seventh step of forming a surface electrode corresponding to the drain region, and a source electrode A method of manufacturing a semiconductor device having an eighth step of forming an electrode, wherein the seventh step and the ninth step of forming an electrode selectively perform metal deposition and low deposition in-situ without taking out from the growth apparatus. A method of manufacturing a semiconductor device, characterized in that a step of performing resistance semiconductor deposition or both of them is performed. 10. The first step of forming the source region is a step having a pre-step of performing a surface treatment on the GaAs crystal substrate in an AsH ₃ atmosphere at a specific temperature. A method for manufacturing a semiconductor device according to claim 1. 11. A first step of forming a source region and a second step of forming a first channel region on a semiconductor substrate.
Step, a third step of forming a barrier layer, a fourth step of forming a second channel region, a fifth step of forming a drain region, and a sixth step of forming an insulating layer. ,
A seventh step of forming a gate mesa portion, an eighth step of forming a gate region, a ninth step of forming a surface electrode corresponding to the drain region, and a tenth step of forming a source electrode.
A method of manufacturing a semiconductor device, which comprises the step of, wherein the step of forming the gate mesa portion is a step of in-situ light irradiation low temperature etching. 12. The light irradiation low temperature etching is GaA.
The method of manufacturing a semiconductor device according to claim 11, wherein a molecular layer etching step using chlorine gas adsorbed on the surface of the s crystal substrate is performed. 13. The first step of forming the source region is a step having a pre-step of performing a surface treatment on the GaAs crystal substrate in an AsH ₃ atmosphere at a specific temperature. A method for manufacturing a semiconductor device according to claim 1.