JP3188844B2 - Semiconductor device and manufacturing method thereof - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device which is used for a semiconductor device and operates at a high speed suitable for high-density integration and a method of manufacturing the same. And a method of manufacturing the same.

[0002]

2. Description of the Related Art In recent years, high integration of semiconductor devices has progressed remarkably, and mass production of 16 Mbit memory has already begun with conventional technology. Prototypes of 64 Mbit and 1 Gbit memory have been announced one after another. I have. However, the miniaturization of the conventional semiconductor device structure is mainly due to the miniaturization of the pattern size, and therefore, it must be limited to the photolithography accuracy. At present, the speed of a semiconductor device is increased by reducing the stray capacitance by miniaturizing an element pattern size by improving photolithography accuracy.

In view of the above, the present inventors have already invented an electrostatic induction transistor, and have proposed an ideal type electrostatic induction transistor capable of maximizing its performance (hereinafter, this ideal type electrostatic induction transistor will be described below). The induction transistor is referred to as “ISIT device”.)

In this ISIT device, when carriers from a source region composed of a high-concentration impurity region reach a drain region through a potential barrier, the miniaturization is extremely limited to reach the drain at a carrier heat velocity without collision with a crystal lattice. Since it is performed, the transistor operates at extremely high speed. Since the potential barrier is controlled by the electrostatic induction effect of the external gate voltage and the source / drain bias voltage, a further high-speed operation is expected. In addition, we have proposed a configuration in which carrier injection from the source region is based on the tunnel phenomenon.
It is called T.

[0005] This ISITT is expected to exhibit a further extreme high-speed performance because the tunneling probability of the potential barrier or the tunnel injection layer is controlled by the external gate voltage and the source / drain bias voltage.
Thus, the distance that the carrier reaches without collision with the crystal lattice is, for example, about 100 nm in the case of GaAs, and about 8 nm in the case of Si. Such an I
Since the SIT device and the ISITT device are inevitably miniaturized, the structure is essentially suitable for high integration as well as high-speed operation. In addition, the SIT device is extremely fast because it is bulk conduction instead of surface conduction, and is inherently low noise because the high-purity crystal region is a carrier conduction layer, and is suitable for large capacity due to its low power consumption. ing.

[0006]

However, in the above-mentioned conventional ISIT device and ISITT device, when the distance between the source and the drain is GaAs, it is about 100 nm, and
In the case of i, the ultimate miniaturization of about 8 nm, which is on the order of a molecular layer, is performed. Therefore, there is a possibility that the source-drain stray capacitance is increased and the operation speed is reduced.

In the vertical transistor structure in which a regrown gate is formed on the side wall of the drain region / potential barrier layer / source region structure, the regrown gate has a side wall surface different from the low index main surface and a different crystal plane orientation of the main surface. Therefore, there is a problem that it is not always easy to grasp the characteristics of the gate growth layer.

It is an object of the present invention to provide a semiconductor device which can operate at high speed, has a very small gate-drain stray capacitance, and can easily form a regrown gate region with clear characteristics, and a method of manufacturing the same. .

[0009]

According to the present invention, there is provided a semiconductor device comprising a source region, a potential barrier layer,
Gate region and drain connected to potential barrier layer
Static induction transistor type semiconductor device having a region
In the above, on the semiconductor substrate, an ultra-thin source region consisting of a first conduction type high concentration impurity added layer, a counter conduction type regrowth ultra-thin potential barrier layer formed on the side wall of this ultra-thin source region, above this regrowth ultrathin potential barrier layer
First conduction type formed on the side wall opposite to the ultra-thin source region side
Ultra-thin drain region composed of high-concentration impurity doped layer
Formed on the regrown ultra-thin potential barrier layer
Regrowth and a ultra-thin gate region, the potential barrier height and the potential of the regrowth Ultrathin potentiometer <br/> interstitial barrier layer by a voltage applied to the regrowth ultrathin gate <br/> preparative region By controlling one or both of the barrier widths, tunneling from the ultra-thin source region to the re-grown ultra-thin drain region
The carrier to be controlled is configured.

Further, the semiconductor device of the present invention has an effective
Make sure that the source-drain distance is 17 nm or less.
Features. Ultra-thin source region and ultra-thin drain
Characterized in that the thickness of the region is 30 to 50 nm
I have. Also, the thickness of the ultra-thin potential barrier layer is set to 0.
The thickness is 3 to 3 nm. In addition,
The configuration in which the long ultra-thin gate region has a homojunction pin structure
Have. Also, the regrown ultra-thin gate region is made of p-type Al.
The structure is an npn structure including a heterojunction using GaAs.
Have

The semiconductor device of the present invention having such a structure.
Has extremely low stray capacitance and carrier
Extremely tunnel barrier layer
It has a high operating speed. Also, a potential barrier layer
Is extremely thin and the effective source-drain distance is short.
The carrier is optimized by the gate voltage
Is tunnel controlled. Also, source and drain regions
Is extremely thin, which results in extremely low stray capacitance.
Please. In addition, a pin structure in which the gate region is a homojunction or
Npn structure including heterojunction using p-type AlGaAs
Therefore, the potential of the potential barrier layer is extremely fast.
And normally on or normally on
Device characteristics can be selectively realized.

[0012] To achieve the above object, the present invention
The method comprises the steps of: adding a first conductive type high-concentration impurity on a semiconductor substrate;
Forming an ultra-thin source region consisting of a layer;
Etching to form sidewalls in the source region;
Process to clean the side wall surface, and the opposite conduction type to the side wall surface
Forming an ultra-thin potential barrier layer;
On the side wall opposite to the ultra-thin source layer of the
Ultra-thin drain region consisting of conductive highly doped layer
Process and clean the surface of the ultra-thin potential barrier layer.
Purification process and cleaned ultra-thin potential barrier
Forming a regrown ultra-thin gate region on the layer;
Source region, ultra-thin drain region and regrown ultra-thin gate region
Forming an electrode on the substrate.

Further, a side wall is formed in the ultra-thin source region.
In the etching step, the etching protection film is formed at about 200 ° C.
Formed by low damage plasma deposition at low temperature
N. Also, side to the ultra-thin source area
The etching process for forming the wall is performed by using Si for forming the side wall.
After forming the N window, irradiate ultraviolet rays at a low temperature of about 90 ° C.
And ozone incineration treatment. Also,
The etching process for forming sidewalls in the ultra-thin source region
The ultra-thin source region is made of a GaAs or AlGaAs material
If the etching method is a photo-excited halogen-based gas
It is characterized by etching. In addition, ultra-thin saw
Process to clean the side wall surface of the
The process of cleaning the rear layer surface is an ultra-thin potential burr
When the layer is made of GaAs or AlGaAs material
Table exposed to arsine atmosphere at a low temperature of 360-480 ° C
It is a surface cleaning process.

Further, an ultra-thin potential barrier layer and
The step of forming the ultra-thin drain region comprises the step of:
The char barrier layer and the ultra-thin drain region are GaAs-based
Or, when it is an AlGaAs-based material,
Is epitaxially grown only on GaAs crystal without deposition
Characterized by the molecular layer epitaxial growth method
You. In addition, the ultra-thin source and drain regions
The process of forming an electrode in the long ultra-thin gate region is performed by using an ultra-thin source.
Region and ultra-thin drain region or regrown ultra-thin gate region
Is a p-type GaAs-based or AlGaAs-based layer
Using trimethylgallium and arsine as reaction gases
P ⁺ contact by molecular layer epitaxial growth method
Selective epitaxial growth of layer on contact area
Tungsten hexacarbonyl on p ⁺ contact layer
Is a method of forming metal electrodes by a metal deposition method using
It is characterized by that. In addition, ultra-thin source region and ultra-thin drain
Of forming electrodes in the in-region and the regrown ultra-thin gate region
But very thin source and drain regions or regrown
Ultra-thin gate region is made of n-type GaAs or AlGaAs
Layer, use diethyl tellurium as the reaction gas
N ⁺ contact layer by molecular layer epitaxial growth method
Selective epitaxial growth on the contact part
Tungsten hexacarbonyl on n ⁺ contact layer
It is a method of forming a metal electrode by the used metal deposition method
It is characterized by the following.

According to the manufacturing method of the present invention having such a configuration,
In the case of extremely thin layers on the order of molecular layers,
Flat npn structure with very shallow junction
Can form a pnp semiconductor device,
The horizontal npn structure or pnp structure is formed almost flat.
Re-grown ultra-thin gate region is easily formed
You. Ultra-thin source region, ultra-thin potential barrier layer
And ultra-thin drain region while maintaining semiconductor characteristics.
Molecular layer epitaxy that can be as thin as the molecular layer
Since it is formed by the long method, the stray capacitance is extremely small.
Wear. In addition, the source region, potential barrier
Since the gate layer and drain region are extremely thin,
Region regrows on low index plane almost same as semiconductor substrate main surface
Is done.

Also, SiN for side wall formation etching is used.
If the protective film is formed by low damage plasma deposition,
It does not disturb the impurity profile of the order. Ma
After the photolithography process,
Process can improve the impurity profile at the molecular layer level.
The surface can be cleaned without disturbing. Also, re-epitaxy
The surface cleaning treatment performed just before char growth
In an arsine atmosphere, impurities on the order of molecular layers
The surface can be cleaned without disturbing the profile. Ma
For forming a potential barrier layer and a drain region
By selective epitaxy by molecular layer epitaxy
In the case of the vertical growth method, an etching step is not required, and
Therefore, the process can be simplified. In addition, the electrode forming method,
Selective epitaxial by molecular layer epitaxial growth method
Very low-resistance electrodes can be obtained by using the growth method and metal deposition method.
Can be

[0017]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS Hereinafter, the present invention will be described in detail based on embodiments shown in the drawings. FIG. 1 is a sectional view of the basic structure of the present invention. This embodiment is an ISIT device, and uses a GaAs crystal as a semiconductor substrate. In FIG. 1, a semiconductor device 12 includes a high-resistance GaAs substrate crystal 1.
Above, the n ⁺ source region 2, a p ⁺ potential barrier layer 4 formed on the sidewall of the n ⁺ source region 2, the p
^The n ⁺ drain region 5 formed on the side wall of the n ⁺ source region 2 via the ⁺ potential barrier layer 4 forms a substantially flat lateral npn structure with a very shallow junction depth. Further, the regrowth gate region 6 formed on the p ⁺ potential barrier layer 2, the n ⁺ contact layer 10 and the source metal electrode 3 laminated on the n ⁺ source region 2, and the regrowth gate region 6 are laminated on the regrowth gate region 6. A p ⁺ contact layer 11 and a gate metal electrode 8, and an n ⁺ contact layer 10 and a drain metal electrode 7 laminated on the n ⁺ drain region. The regrowth gate region 6 is formed selectively on the same low index plane orientation as the main surface by selective epitaxy growth.

The n ⁺ source region 2 has a carrier density of, for example, 0.5 to 5 × 10 ¹⁹ / cc to which selenium is added,
The thickness is about 30 to 500 nm. The p ⁺ potential barrier layer 4 is, for example, 2 to 9 × 10 ¹⁹ / c with zinc addition.
It has a carrier density of c and a thickness of about 0.3 to 3 nm. The n ⁺ drain region 5 has a carrier density of, for example, 0.5 to 5 × 10 ¹⁹ / cc to which selenium is added, and has a thickness of about 30 to 50 nm. Regrowth gate region 6
Takes, for example, a pin structure in the case of a homojunction gate structure, and a p-type AlGa in the case of a heterojunction gate structure.
It has an npn structure using an As layer.

In the case of the homojunction gate structure, when the n layer having the pin structure is a layer to which an impurity having a concentration sufficient to lower the potential barrier is added, the normally-on ISIT characteristic of the present structure can be obtained. In addition, when the potential barrier is high, the ISI of this configuration having normally-off characteristics
T characteristics are obtained. In this embodiment, about 0.8 e
It is designed to have a potential barrier height of about V.

In the hetero-junction gate structure, the barrier height of the potential barrier layer 4 is controlled by the bias voltage applied to the gate electrode.

Source metal electrode 3 and drain metal electrode 7
Any structure that forms a good low-resistance metal-semiconductor contact with an n-type GaAs crystal is applied. In order to obtain a low-resistance metal-semiconductor contact, the metal electrode layer is formed by, for example, a lift-off method in the case of AuGe / Ni / Au or Ti / Au, which are conventionally applied well. In the structure of the present invention, a heat treatment at a high temperature is not performed because an extremely thin layer is laminated in multiple layers. Therefore, metal electrodes such as a source electrode and a gate electrode are formed by a non-alloying treatment or a metal semiconductor contact having an ultrathin alloy layer, and are, for example, low-temperature generated metal deposition films.

The ISIT structure of this embodiment has a gate width of 1
It is a 00 micron device. For example, at an effective source-drain distance of 17 nm, the source-drain stray capacitance is easily attained in the order of fF (femtofarad). Here, the effective source-drain distance is not a metallurgical junction distance but a distance including a depletion region that spreads to the source / drain side, which becomes a carrier path.

In the ISIT device shown in FIG. 1, in both the homo-junction and hetero-junction gate structures, the potential barrier height of the potential barrier layer 4 is increased by the electrostatic induction effect of the bias voltage applied between the external gate electrode and the source / drain. Is controlled to perform the SIT operation. In the structure of this embodiment using GaAs having a source-drain distance of about 17 nm, since the potential barrier layer 4 is extremely narrow, carriers pass through the potential barrier layer 4 by a tunnel effect. Therefore, the potential barrier layer 4 is formed by the electrostatic induction effect of the bias voltage applied between the external gate electrode and the source / drain.
The height and width of the potential barrier are controlled to perform a tunnel injection type SIT operation, that is, an ISITT operation.

Next, the manufacturing method of this embodiment will be described. In order to form an element as in the present embodiment, it is necessary to use a crystal growth method having a film thickness controllability and a position controllability almost in the order of a molecular layer of a crystal. In addition, since the impurity distribution and the crystal composition must be sharply controlled in the order of the molecular layer of the crystal, the low-temperature growth and the low-temperature manufacturing process must be performed. At present, a crystal growth method satisfying this requirement is a molecular layer epitaxial growth method (ML) proposed and developed by the present inventor himself.
E) is suitable. The molecular layer epitaxial growth method can be applied not only to a compound crystal such as GaAs described below but also to silicon.

The molecular beam epitaxy (MBE) is a so-called vapor deposition method. Even if it has a film thickness controllability on the order of a molecular layer, its growth process does not guarantee the molecular layer growth in principle. Moreover, in order to obtain good quality crystals, the growth temperature is at least about 200 ° C. higher than that of the molecular layer epitaxial growth method. In the case of GaAs, since the Debye temperature is about 360 K in a temperature range of 140 K or more, the difference of the process temperature of 200 K has a great effect on the occurrence of defects. MO using organic metal gas
Although the CVD method can be applied, an appropriate low-temperature process temperature and film thickness / composition controllability on the order of molecular layers are required.

Hereinafter, a case where the present embodiment is to grow a crystal based on the MLE method will be described. FIG. 2 is a structural sectional view showing the manufacturing process of the present embodiment. With reference to FIG.
On the {100} plane high resistance GaAs substrate crystal 1, n of about 300 (angstrom), for example, by MLE method.
⁺ Grow source region 2. For example, Se is used as an impurity added to the n ⁺ source region 2. For example, DESe is used as a gas source, and DESe is introduced after introduction of triethylgallium (hereinafter, referred to as TEG) or arsine during molecular layer epitaxial growth. Typically, the growth temperature is about 360-480 ° C. The introduction pressure and the introduction time of TEG are, for example, about 2 seconds at 0.5 to 5 × 10 ⁻⁶ Torr, and the introduction pressure and the introduction time of arsine are about 0.1 second.
It is about 10 seconds at 1-1 × 10 ⁻³ Torr. DESe
Pressure and time are, for example, 0.5 to 5 × 10 ^-6 To
rr is about 2 seconds. When grown by this method, a high concentration n-type GaAs conductive layer having a carrier density of about 0.5 to 5 × 10 ¹⁹ / cc is obtained.

Referring to FIG. 2B, a silicon nitride film (S) is formed on the entire main surface by low-damage plasma deposition at a low temperature of about 200.degree.
iN) 9 is formed. At this time, the plasma generation region and the deposition portion, that is, the crystal holding portion are separated from each other,
Reduces damage to crystals during plasma deposition.

Thereafter, an SiN window for forming a side wall is formed by a usual photolithography technique. Normal plasma etching is applied to the SiN window opening etching for forming the groove, but a method with small ion impact energy is used to reduce damage to the GaAs crystal. Since an ultrathin organic layer remains on the surface after the ordinary photolithography process, for example, 90 ° C.
The ozone incineration process is performed while performing ultraviolet irradiation at a low temperature.

In the ISIT device according to the present invention, since the carrier conductive layer is very close to the crystal surface even if it is a bulk region, it is necessary that the etching process for forming the side wall has low damage. For this purpose, the sidewall formation etching is performed by photoexcitation gas etching.

The photo-excitation gas etching is performed using a halogen-based gas such as chlorine gas or bromo gas.
Since etching depth accuracy and surface flatness on the order of molecular layers are required, spontaneous etching does not occur.
It is performed under ultraviolet irradiation at a low temperature of about ℃ or less. That is,
When there is no ultraviolet irradiation, the etching is performed under a low temperature condition where etching does not substantially proceed. Since light irradiation gas etching is rate-limiting by the surface reaction, it is extremely sensitive to the surface state of the sample.

Since the etching reaction is stopped only by the presence of the oxide film of about Å, the surface cleaning treatment is performed immediately before the photo-excitation gas etching. In addition, this surface cleaning treatment needs to be performed at a sufficiently low temperature so as not to disturb the impurity profile on the order of the molecular layer. This is achieved, for example, at a low temperature of 360 to 480 ° C. in an arsine atmosphere. When the surface treatment is performed at 480 ° C., it is preferable to perform the surface treatment under an arsine pressure of, for example, around 8 × 10 ⁻⁴ Torr. In this embodiment, a side wall having a depth of about 30 nm is formed by photoexcitation gas etching.

The sample on which the side walls have been formed by the photoexcited gas etching is immediately put into a molecular layer epitaxial growth apparatus as it is. The GaAs surface etched by the photoexcited gas is protected by a halogen-based gas, for example, a chlorine gas.

Referring to FIG. 2C, the p ⁺ potential barrier layer 4 and the n ⁺ drain layer 5 are successively grown by GaAs molecular layer epitaxial growth. Done. This surface cleaning treatment needs to be performed at a sufficiently low temperature so as not to disturb the impurity profile on the order of the molecular layer. This is achieved, for example, at a low temperature of 360 to 480 ° C. in an arsine atmosphere. When the surface treatment is performed at 480 ° C., it is preferable to perform the surface treatment under an arsine pressure of about 8 × 10 ⁻⁴ Torr, for example.

The p ⁺ potential barrier layer 4 uses, for example, Zn (zinc), Be (beryllium) or C (carbon) as an additional impurity. The source gas is, for example, DEZ
n, DEBe or the like is used. About C, TMG and As
The molecular layer epitaxial growth using H3 was performed, and TM
C from G is directly used as an acceptor impurity.
The amount of C mixed is controlled by the growth conditions. Or TE
TMG may be mixed during the molecular layer epitaxial growth using G and AsH3.

In the case of the present embodiment, for example, the p ⁺ potential barrier layer 4 having a carrier density of 6 × 10 ¹⁹ / cc and a thickness of 3 nm is formed. At this time, the height of the potential barrier is about 0.
8V is obtained. The n ⁺ drain layer 5 is formed under the same growth conditions as in the case of forming the source layer region, and is formed to about 30 nm. At this time, since the molecular layer epitaxial growth layer does not deposit on SiN 9 and has selectivity for growing only on the GaAs crystal, after the selective growth, the semiconductor surface becomes almost flat and the semiconductor main surface appears.

In the above, the p ⁺ potential barrier layer 4 is made of Ga
In the case of forming a homojunction of As, for example, by using an organometallic gas of aluminum such as dimethyl aluminum hydride or the like, Al _x Ga ₁ -x As (including X = 1) / GaAs by a molecular layer epitaxial growth method.
Can be formed.

Referring to FIGS. 2D and 2E, after the sidewall npn structure is formed as described above, a silicon nitride film 9 'is again formed on the surface of the sample at a low temperature, and a window is opened by a normal photolithography process. Then, the gate region 6 is formed by selective regrowth. After the photolithography process,
Usually, since an ultrathin organic material layer remains on the surface, the ozone incineration treatment is performed while performing ultraviolet irradiation at a low temperature of about 90 ° C., for example. Immediately before the regrowth of the gate region, a surface cleaning process is performed. In addition, this surface cleaning treatment needs to be performed at a sufficiently low temperature so as not to disturb the impurity profile on the order of the molecular layer. This is, for example, 360-48
This is achieved by performing the process at a low temperature of 0 ° C. in an arsine atmosphere. When performing surface treatment at 480 ° C., for example, 8
It is preferable to carry out under an arsine pressure near x10 ^-4 Torr. Note that no GaAs crystal is deposited on the silicon nitride film.

Next, referring to FIG. 2F, an n ⁺ contact layer 10 or a p ⁺ contact layer 11 is formed to obtain a low-resistance metal semiconductor contact. As the n ⁺ contact layer, for example, an n ⁺ GaAs growth layer using diethyl tellurium (DETe) as an impurity gas is used. The selective epitaxy is performed only on the GaAs crystal by the molecular layer epitaxial growth method, but the introduction pressure is 0.5 to 5 × 10 ⁻⁶ T.
After the introduction of TEG or arsine at orr, it is introduced for 2 to 40 seconds after evacuation. 1x10
N ⁺ contact layer 10 with a very high concentration exceeding ²⁰ / cc
Is selectively grown. After that, a metal electrode region is formed.

As the p ⁺ contact layer 11, for example, a p ⁺ GaAs growth layer with a high concentration of carbon using trimethyl gallium (TMG) and arsine is selectively grown only on the exposed GaAs surface. TMG is 0.5-50 × 10 ^-6
Arsine is introduced at a pressure of Torr for 2 to 20 seconds, and arsine is introduced at a pressure of 0.1 to 1 × 10 ⁻⁴ Torr for 2 to 200 seconds. By this selective epitaxial growth, 1 × 1
Ap ⁺ contact layer 11 having a carrier density approaching 0 ²⁰ / cc is formed.

Incidentally, metal-semiconductor contact is extremely important in determining the operation speed of the device. Therefore, extremely low-resistance metal-semiconductor contacts are required. Furthermore, not only the present invention but also ultra-high-speed semiconductor devices have an ultra-thin multilayer structure. Not applicable.

The following three types of electron conduction mechanisms by metal-semiconductor contact can be considered. The first conduction mechanism is a thermionic conduction mechanism. This is a mechanism that conducts through a potential barrier formed by metal-semiconductor contact by thermal energy. The second conduction mechanism is a tunnel conduction mechanism. This is a mechanism in which, when the potential barrier width formed by the metal-semiconductor contact is extremely small, electrons are transferred from the metal to the semiconductor through the potential barrier layer by a tunnel phenomenon. In a metal-semiconductor contact of an actual device, the second conduction mechanism is considered to be dominant because the contact layer is an extremely heavily doped layer. The third conduction mechanism is a conduction mechanism via a defect level. Usually, an ideal metal-semiconductor contact is hardly formed, and a lattice mismatch or a defect due to an interface inclusion layer exists near the metal-semiconductor contact interface. A mechanism that conducts through these defect levels existing in the potential barrier of the metal-semiconductor contact has been considered.

In order to reduce the contact resistance of the metal-semiconductor contact, in the case of the first mechanism, the height of the potential barrier may be reduced. What is necessary is just to make the function difference small. For this purpose, a metal having a small work function and generally a small electronegativity may be used. The height of the potential barrier determined by the work function difference between metal and semiconductor is called the Schottky limit, but such an ideal metal-semiconductor contact has hardly been formed so far. In most cases, the potential barrier is determined. In the case of the second mechanism, a metal having a small work function may be selected to lower the potential barrier, and the semiconductor may be doped with a high concentration of impurity to reduce the width of the depletion layer formed by the metal-semiconductor contact. In the case of the third mechanism, the contact resistance can be reduced by forming a defect necessary for conduction near the interface.

In this embodiment, a high-concentration impurity-added layer using DETe is used as the n ⁺ contact layer 10, and a high-concentration impurity-added layer using TMG and arsine is used as the p ⁺ contact layer 11. The metal electrode region is formed by, for example, a metal deposition method using tungsten hexacarbonyl. Since it is not an alloy contact having a thick alloy layer, a contact layer thickness of at most about 15 nm is sufficient. The impurity concentration is typically close to 1 × 10 ²⁰ cm ⁻³ .

Immediately before metal deposition, a low-temperature surface treatment is performed. This is 1 × 10 ⁻³ at a low temperature of, for example, 360 to 480 ° C.
This is achieved by performing the process in an arsine atmosphere near Torr. When performing surface treatment at 480 ° C., for example, 8
It is preferable to carry out under an arsine pressure near x10 ^-4 Torr.

For forming a low-resistance metal semiconductor contact, low-temperature surface treatment is important. With such a method, n-type GaAs
An extremely low contact resistance of 3.5 × 10 ⁻⁷ Ωcm ² is obtained for the s crystal. 1 × 1 for p-type GaAs
An extremely low contact resistance of 0 ^-8 Ωcm ² is obtained.

In the ISIT apparatus of the present invention, elements are formed by the above-described steps, and the source / drain junction depth is as shallow as the molecular layer, which is the thickness controllability of the molecular layer epitaxial growth. The side walls are formed by a photoexcited gas etching method which is anisotropic etching showing good selectivity. This method is a low-damage step because it is at low temperature and there is no ion bombardment such as plasma. Therefore, it is most suitable for forming the device structure of the present invention having a very thin junction depth of about Å together with the molecular layer epitaxial growth method.

The metal electrodes for the source, drain and gate regions are formed on a very clean surface which has been subjected to low-temperature surface treatment by a metal deposition technique. In this method, a metal-semiconductor contact having an extremely low contact resistance having only an extremely thin alloy layer on the order of molecular layers is formed.
It can be applied to a device and operates at a very high speed. In addition,
The invention is not limited to these embodiments,
Applicable as appropriate.

[0048]

As will be understood from the above description, since the semiconductor device of the present invention has a very shallow source-drain junction depth on the order of a molecular layer, the effect that the source-drain stray capacitance can be extremely reduced can be obtained. Have.
Therefore, the semiconductor device of the present invention can operate at a very high speed. Also, since the distance between the source and potential barrier is set to be equal to or less than the carrier mean free path,
Carrier conduction is performed without collision with the crystal lattice, and an effect that an extremely high-speed operation can be performed is obtained. Further, when the carrier conduction is caused by a tunnel phenomenon, there is an effect that a higher-speed operation can be performed. Further, since the potential barrier control is based on the electrostatic induction effect, there is an effect that extremely high-speed operation can be performed without a carrier accumulation effect. In addition, the crystal surface after the formation of the lateral npn structure is almost flat and almost the same as the low index main surface, so that the characteristics of the regrown gate region can be easily grasped. In addition, the source, drain and gate metal electrodes
Since it has an extremely low contact resistance formed by the ultrathin metal deposition layer, it has an effect that it can operate at an extremely high speed.

Next, the method of manufacturing a semiconductor device according to the present invention has an effect that a source region / potential barrier layer / drain region junction can be formed in a flat lateral npn structure or a pnp structure in an extremely shallow molecular layer order. Further, since the horizontal npn structure or the pnp structure can be formed almost flat, there is an effect that the formation of the regrown gate region becomes easy. Further, since the step of forming the ultra-thin source region and the regrown ultra-thin gate region is the molecular layer epitaxial growth method, the ultra-thin source region and the re-grown ultra-thin gate region whose position is controlled at a low temperature can be formed at a low temperature. It has the effect of. In addition, since a step of cleaning the side wall of the source region and the surface of the potential barrier layer at a low temperature is provided, the junction surface between the source region and the potential barrier layer and the junction surface between the potential barrier layer and the gate region are formed extremely well. It has the effect of being able to. Further, in the step of forming the electrode, a step of removing the oxide film on the surface or not forming the oxide film is provided, so that there is an effect that an extremely low-resistance metal semiconductor contact can be formed.

[Brief description of the drawings]

FIG. 1 is a sectional view of a basic structure of the present invention.

FIG. 2 is a structural sectional view showing a manufacturing process according to the embodiment of the present invention.

[Explanation of symbols]

REFERENCE SIGNS LIST 1 substrate crystal 2 n ⁺ source region 3 source metal electrode 4 p ⁺ potential barrier layer 5 n ⁺ drain region 6 regrowth gate region 7 drain metal electrode 8 gate metal electrode 9, 9 ′ SiN film 10 n ⁺ contact layer 11 p ⁺ Contact layer

────────────────────────────────────────────────── ─── Continuation of the front page (56) References JP-A-4-299574 (JP, A) JP-A-3-209730 (JP, A) (58) Fields investigated (Int. Cl. ⁷ , DB name) H01L 29/80 H01L 29/06

Claims (14)

(57) [Claims] A source region and a potential barrier layer;
Region and drain connected to the potential barrier layer of
Static induction transistor type semiconductor device having
An ultra-thin source region composed of a first conduction type high-concentration impurity-doped layer on a semiconductor substrate, and a counter conduction type regrowth ultra-thin potential barrier layer formed on a side wall of the ultra-thin source region. ,
The ultra-thin source of this regrown ultra-thin potential barrier layer
The high conductivity of the first conductive type formed on the side wall opposite to the region side
A regrown ultra-thin drain region consisting of a pure-added layer,
Regrowth ultrathin formed on long ultrathin potential barrier layer
And a gate region, and controls one or both of the potential barrier height and the potential barrier width of the regrown ultrathin potential barrier layer by a voltage applied to the regrowth ultra-thin gate region, the ultra-thin source calibration tunneling from region to the regrowth ultrathin drain region
A semiconductor device characterized by being configured to control a rear . 2. The ultra-thin source region, regrown ultra-thin drain
Region and the regrown ultra-thin potential barrier layer are made of GaAs.
If it is a system material, the effective source-drain distance
The semiconductor device according to claim 1, wherein the thickness is 17 nm or less . 3. When the ultra-thin source region and the re-grown ultra-thin drain region are made of a GaAs-based material, the thickness of the ultra-thin source region and the re-grown ultra-thin drain region is 30.
The semiconductor device according to claim 1, wherein the thickness is from 50 nm to 50 nm . 4. The ultra-thin regrowth potential barrier layer according to claim 1, wherein
In the case of a GaAs-based material, the regrowth ultra-thin potential
4. The semiconductor device according to claim 1 , wherein the thickness of the signal barrier layer is 0.3 to 3 nm . 5. The method according to claim 1, wherein the regrowth gate region is a homojunction p-type.
5. The semiconductor device according to claim 1, wherein the semiconductor device has an in-structure . 6. The GaAs-based ultra-thin regrowth gate region
If the material, the regrown ultra-thin gate region is p-type A
The semiconductor device according to any one of claims 1 to 4, wherein the semiconductor device has an npn structure including a heterojunction using lGaAs . 7. A step of forming an ultra-thin source region comprising a first conductive type high concentration impurity doped layer on a semiconductor substrate;
Etching process to form sidewalls in this ultra-thin source region
When a step of cleaning the formed sidewall surface, this
Formation of counter-conducting ultra-thin potential barrier layer on side wall surface
And the ultra-thin potential barrier layer
First conductivity type high concentration impurities on the side wall opposite to the source region
A step of forming an ultra-thin drain region made of an additive layer, and a step of cleaning the surface of the ultra-thin potential barrier layer,
Forming a regrown ultrathin gate region on the cleaned ultrathin potential barrier layer; and forming electrodes in the ultrathin source region, the ultrathin drain region and the regrown ultrathin gate region. A method for manufacturing a semiconductor device comprising: 8. d to form a sidewall on the ultra-thin source region
In the etching step, the etching protection film
Low damage plasma deposition at low temperature
The method for manufacturing a semiconductor device according to claim 7, wherein the semiconductor device is SiN . 9. d to form a sidewall on the ultra-thin source region
In the etching step, the Si for forming the sidewall is formed.
After forming the N window, irradiate ultraviolet rays at a low temperature of about 90 ° C.
9. The method for manufacturing a semiconductor device according to claim 8, wherein an ozone ashing process is performed. 10. An etching step for forming a side wall in the ultra-thin source region, wherein the ultra-thin source region is formed of GaAs.
Etching when using s-based or AlGaAs-based materials
10. The method of manufacturing a semiconductor device according to claim 7, wherein the method is photo-excited halogen-based gas etching. 11. The ultra-thin source region side wall surface is cleaned.
And cleaning the ultra-thin potential barrier layer surface
Is performed when the ultra-thin potential barrier layer is formed of GaAs.
If it is a system-based or AlGaAs-based material, 360 to 48
Surface cleaning treatment by exposing to an arsine atmosphere at a low temperature of 0 ° C
Characterized in that that method of manufacturing a semiconductor device according to claim 7 10. 12. The ultra-thin potential barrier layer and
The step of forming the ultra-thin drain region is performed by the step of
The char barrier layer and the ultra-thin drain region are GaAs-based
Or, when it is an AlGaAs-based material,
Is epitaxially grown only on GaAs crystal without deposition
The method of manufacturing a semiconductor device according to claim 7, wherein the method is a molecular layer epitaxial growth method. 13. The step of forming electrodes in the ultra-thin source region, the ultra-thin drain region and the regrown ultra-thin gate region ,
The ultra-thin source and drain regions are regrown
Ultra-thin gate region is made of p-type GaAs or AlGaAs
Reacts trimethylgallium with arsine when it is a layer
P by the molecular layer epitaxial growth method used as a gas
⁺ Select contact layer for contact layer
Grown on the p ⁺ contact layer.
Metal electrode formation by metal deposition method using carbonyl
The method for manufacturing a semiconductor device according to claim 7, wherein the method comprises: 14. The method of forming electrodes in the ultra-thin source region, the ultra-thin drain region and the regrown ultra-thin gate region ,
The ultra-thin source and drain regions are regrown
Ultra-thin gate region is made of n-type GaAs or AlGaAs
Layer, use diethyl tellurium as the reaction gas
N ⁺ contact layer by molecular layer epitaxial growth method
Is selectively epitaxially grown on the contact portion, and the n
^{+ Use} tungsten hexacarbonyl on contact layer
The method for manufacturing a semiconductor device according to any one of claims 7 to 12, wherein a metal electrode is formed by a metal deposition method.