JPH032350B2 - - Google Patents

Description

[Detailed description of the invention] The present invention relates to semiconductor memory elements.

The present invention provides a semiconductor memory element which is based on an operating principle different from that of, for example, a MOS type memory having a floating gate, which has been used as a semiconductor memory element so far, and which enables faster operation.

In a semiconductor memory element, the speed of carrier movement determines the response speed of the element.

The device structure of the present invention improves the electron mobility compared to the previous one.
This is a significant improvement over MOS type field effect transistors, and aims to speed up device operation.

The basic structure of the semiconductor memory device of the present invention is as follows.

Since FIG. 1a is a sectional view of a main part of a typical example of a semiconductor memory device of the present invention, the principle will be explained using this. As will be described later, the semiconductor memory device of the present invention is not limited to this example.

It has a narrow forbidden band semiconductor layer 3 and two wide forbidden band semiconductor layers 2 and 4 sandwiching it, and the wide forbidden band semiconductor layer and the narrow forbidden band semiconductor layer are mutually connected to form a heterojunction at the interface between the two layers. lattice matching has been achieved. Furthermore, each of the heterojunctions has a conduction band step or valence band step large enough to confine carriers in the narrow bandgap semiconductor layer. One of the two wide band gap semiconductor layers, for example, the semiconductor layer 2 close to the substrate 1 (generally, a semi-insulating semiconductor substrate is used as the substrate) is connected to the first and second electrodes 5 and 6 of the semiconductor device. (commonly referred to as source and drain electrodes). A carrier control electrode is provided on the other wide forbidden band semiconductor layer 4. This control electrode may be provided directly on the semiconductor layer 4 or may be provided via an insulating layer. The impurity concentrations of the two wide bandgap semiconductor layers 2 and 4 are higher than that of the narrow bandgap semiconductor layer 3. It is convenient that the difference in concentration is 500 times or more. When GaAs-GaAlAs-based materials are used, the narrow bandgap semiconductor layer is non-doped and has an impurity concentration that is naturally mixed in during manufacturing, usually about 1×10 ¹⁴ to 1×10 ¹⁵ cm ^-3 or less. ,
The wide forbidden band semiconductor layer has a density of about 5×10 ¹⁶ to 3×10 ¹⁸ cm ⁻³ . Carriers are secured in the potential well formed at the interface between the narrow bandgap semiconductor layer and the wide bandgap semiconductor layer, mainly due to the difference in impurity concentration between the two semiconductor layers.

The two wide forbidden band layers 2 and 4 have the same conductivity type.

The configuration is such that the carriers 8 generated at the interface between the second wide forbidden band semiconductor layer 4 and the narrow forbidden band semiconductor layer 3 do not come into electrical contact with the first and second electrodes 5 and 6. For example, the length of the wide forbidden band semiconductor layer 4 provided with the carrier control electrode 7 with respect to the carrier running direction is determined by the first and second electrodes 5,
A spacing of less than 6 is advantageous.

Further, it is preferable to provide an undoped wide band gap semiconductor layer at the interface between the narrow band gap semiconductor layer 3 and the wide band gap semiconductor layers 2 and 4. 1st
Figure b is a sectional view showing this example. 2' and 4' are the undoped wide bandgap semiconductor layers. In the figure, parts with other symbols are shown in Figure 1a.
It is similar to This structure can achieve its purpose by stopping the doping of the wide bandgap semiconductor layer near the aforementioned heterojunction, or by starting doping only after forming a non-doped layer near the heterojunction. The appropriate thickness is about 20 Å to 60 Å. It is possible to prevent impurities from diffusing from the wide bandgap semiconductor layer to the narrow bandgap semiconductor layer, and to reduce scattering of ionized impurities near the interface of the narrow bandgap semiconductor layer. Furthermore, it is also useful for preventing impurities in the wide bandgap semiconductor layer from diffusing into the narrow bandgap semiconductor layer.

The operation of the storage device will be explained using FIG. FIG. 2 shows the conduction electron band of the energy band structure in the gate electrode portion of the device shown in FIG. The control electrode 7 of the carrier is a shot electrode. 2, 3, 4 and 7 in Figure 2 are the first
Parts of the semiconductor layer with the same reference numerals in the figure are shown.
Reference numerals 8 and 9 indicate two-dimensional electron gas generated at the interface between the two wide bandgap semiconductor layers 2 and 4 and the narrow bandgap semiconductor layer 3. 10 is the Fermi level. 2 when no voltage is applied to the control electrode 7 of the carrier.
The thickness and impurity concentration of the second wide forbidden band semiconductor 4 are selected so that a dimensional electron gas 8 exists.

Since the two-dimensional electron gas 8 exists at the interface, the threshold voltage of the gate voltage for flowing current between the source 5 and the drain 6 becomes larger than in the case without this. Note that this current flowing between the source and drain is mainly due to the traveling of the two-dimensional electron gas 9 existing at the interface between the semiconductor layers 2 and 3.

Now, by further applying a pulsed negative potential to expel the electron gas 8 from the potential well, no electrons exist at the interface between the semiconductor layers 3 and 4. In this state, the threshold voltage of the gate voltage decreases, so the current between the source and drain increases for the same gate voltage.

Therefore, the above two states can be made to correspond to "0" and "1" in binary logic operation.

In this way, the present invention provides two carrier trapping regions, one at a time at the double heterojunction interface, and controls the presence of carriers in one of the trapping regions by a signal applied to the gate electrode, so that the presence or absence of the carriers can be controlled. High-speed dynamic memory was made possible by using a phenomenon that affects the current flowing through the other capture region. By making the narrow bandgap semiconductor layer of the double heterojunction undoped to eliminate impurity scattering, and by lowering the temperature to eliminate phonon scattering, sub-nanosecond operation is possible.

Note that when the carrier control electrode 7 is not biased, the depletion layer existing under the control electrode 7 forms a heterojunction between the wide forbidden band semiconductor layer 4 and the narrow forbidden band layer 3 near the control electrode 7. Therefore, there is a two-dimensional electron gas 8 that becomes a carrier at the stepped portion of the energy generated at the heterojunction interface. When a desired signal voltage is applied to the control electrode, the depletion layer should reach the heterojunction on the side closer to the control electrode 7, and the carrier should no longer exist at the energy step in the conduction band. . Therefore, it is necessary to select the concentration and thickness of the dopant in the wide forbidden band semiconductor layer on the side closer to the control electrode 7 so as to satisfy the above conditions.

In order to make the carrier mobility in the present semiconductor memory element higher than room temperature and to prevent the carrier from thermally deviating from the step of the conduction band generated at the heterojunction surface, the effect of the present invention can be made more remarkable. Cool to at least 100K or less.

Hereinafter, the present invention will be explained in detail with reference to Examples.

Example 1 This example uses an undoped GaAs layer and an n-type Ga _0.7 Al _0.3
This is an example of high-speed dynamic memory that utilizes two-dimensional electron gas generated at the interface with the As layer. A sectional view of the main part thereof is shown in FIG.

5×10 ¹⁶ cm ^-3 ~3× on semi-insulating GaAs substrate 1
n-Ga _0.7 doped with Si in the range of 10 ¹⁸ cm ^-3
Al _0.3 As layer 2 (thickness 0.05-1μm), undoped
GaAs layer 3 (thickness 0.02-0.1 μm), n=5×10 ¹⁶ ~
Ga _0.7 doped with Si in the range of 3×10 ¹⁸ cm ^-3
Grow Al _0.3 As layer 4. The well-known molecular beam epitaxial method was used as the growth method.

The molecular beam epitaxial method has advantages such as being able to rapidly change doping and being able to grow at low temperatures, and is convenient for manufacturing the memory device of the present invention.

Cr, Ti, and Au are successively deposited without taking out the semiconductor substrate formed so far from the growth chamber.
A shotgun junction is formed at the interface between the semiconductor layer 4 and this metal layer. This metal layer is processed into a gate electrode 7 by photolithography. Subsequently, the region other than the n-Ga _0.7 Al _0.3 As portion below the gate electrode 7 is removed by etching. Finally, Au−Ge
The ohmic electrodes 5 and 6 are formed from -Ni alloy, and the dynamic memory is completed.

Dynamic memory has the remarkable advantage that when operated at low temperatures, electron mobility increases and written information is less likely to be thermally lost.

At 77K, the electron mobility in this dynamic memory is approximately 50,000 cm ² V ^-1 S ^-1 , which is extremely low.
It's fast.

The memory write time was 400 psec, and the read time was 200 psec.

Embodiment 2 FIG. 3 is a sectional view of a main part showing another embodiment of the present invention.

This embodiment differs from the first embodiment in that the two-dimensional electron gas used for memory writing is formed by a buried gate electrode section.

In the figure, 1 is a semi-insulating GaAs substrate, 3 is an undoped
GaAs layer 0.2 μm, 21 is n-Ga _0.7 Al _0.3 As layer (n=
8×10 ¹⁷ cm ^-3 , thickness 0.03 μm), 4 is n-Ga _0.7
Al _0.3 As layer (n=1×10 ¹⁸ cm ^-3 , thickness 0.05 μm) 5,
6 is a source and drain electrode, and 7 is a control gate.

On the semi-insulating GaAs substrate 1, by MBE method,
Grow an undoped Ga _0.7 Al _0.3 As layer 2, 2 μm thick.
Next, Si ions were implanted at an accelerating voltage of 150 kV, and n
A mold region 21 is formed and annealed at 850°C.

The surface of the growth layer is coated with H ₂ SO ₄ to a thickness of 0.2 μm:
After etching with a mixture of H ₂ O ₂ :H ₂ O (3:1:1), water washing is performed for 2 hours to clean the surface and form an oxide film. After that, MBE
After heating at 570°C in the device and removing the surface oxide film, undoped Ga _0.7 Al _0.3 As layer 22, 40 Å, undoped GaAs layer 3, 0.1 μm, undoped Ga _0.7 Al _0.3
As layer 23, 40 Å, Si doped (n=10 ¹⁸ cm ^-3 )
A Ga _0.7 Al _0.3 As layer 4 with a thickness of 0.05 μm is sequentially grown using the MBE method. Next, use a solution of phosphoric acid, hydrogen peroxide, and ethylene glycol (1:1:3) to remove the
0.2 μm mesa etching is performed to form an inverted mesa-shaped semiconductor region, leaving the n-type region 21 in the center. The ohmic electrodes 5 and 6 are thicker than this reverse mesa-shaped step.
is made of Au-Ge-Ni alloy (0.6 μm thick).
The ends 5' and 6' of the inverted mesa region are regions in which the semiconductor and electrode metal are alloyed. A control gate 7 is formed in a region above the buried floating gate 21 by laminating Ti, Pt, and Au.
The lift-off method was used for electrode formation in both cases.

FIG. 4 shows a plan view and wiring state in the case of a single element. The buried gate 21 is not wired. The same numbers as in FIG. 3 indicate the same parts. I C
In this case, wiring is formed on a commonly used interlayer insulating film having contact holes.

In this type of device, the electron gas accumulated at the hetero interface is 8 and 9, and 8 is connected to the outside through an ohmic electrode, and is used for signal reading.

8 are sucked out by the positive pulse applied to the gate electrode 7, and the electron trap becomes empty. Therefore, the current-voltage characteristics in channel 9 change,
Information can be read.

Embodiment 3 FIG. 5 is a sectional view of an improved memory element shown in Embodiment 1, which can operate at a temperature close to room temperature. Undoped GaAs layer 3 in Example 1
is divided into two layers 31 and 32, and between these layers n
- It has a structure in which a layer 33 of Ga _1-x Al _x As (0<x0.3) is inserted.

FIG. 6 shows the lower end of the conduction electron band of the energy band structure in the gate electrode portion of the device. 8 and 9 indicate two-dimensional electron gases as in FIG. 2, and 10 indicates Fermi units.

The semiconductor layers 31 and 32 basically have the same properties as the semiconductor layer 3 described above.

This prevents the electron gases 8 and 9 from moving toward each other due to heat, and prevents stored information from thermally evaporating.

Cooling to 77K significantly improves electron mobility. The intermediate layer 31 may be P-type doped GaAs.

Although the present invention has been described using GaAs-GaAlAs as a specific example, it can also be implemented using other semiconductor materials.
For example, AlGaAs−AlGaAs, GaAs−
Examples include AlGaAsP, InP-InGaAsP, InP-InGaAs, and InAs-GaAsSb.

[Brief explanation of the drawing]

1A and 1B are cross-sectional views of a typical semiconductor memory element of the present invention, FIG. 2 is a band model diagram of the element of FIG. 1A, FIG.
The figure is a plan view of the embodiment shown in FIG. 3, FIG. 5 is a sectional view of an element of another embodiment, and FIG. 6 is a band model diagram of the element of FIG. 5. DESCRIPTION OF SYMBOLS 1... Semi-insulating semiconductor substrate, 2, 4... Wide forbidden band semiconductor layer, 3... Narrow forbidden band semiconductor layer, 5, 6...
...Electrode, 7...Carrier control electrode, 8,9...
Two-dimensional electron gas.

Claims (1)

[Claims] 1 a narrow bandgap semiconductor layer and a first layer sandwiching the narrow bandgap semiconductor layer;
Two second wide bandgap semiconductor layers are provided, the first and second wide bandgap semiconductor layers are of the same conductivity type and have impurity concentrations that are compared to the impurity concentration of the narrow bandgap semiconductor layer. The two interfaces between the narrow bandgap semiconductor layer and the first and second wide bandgap semiconductor layers have a conduction band step of a size necessary to confine carriers in the narrow bandgap semiconductor layer. A first and a second semiconductor layer having a valence band step and in contact with the first wide forbidden semiconductor layer and connected to a carrier at the interface between the first wide forbidden semiconductor layer and the narrow forbidden semiconductor layer. an electrode is formed, the second wide bandgap semiconductor layer is not connected to the first and second electrodes, and the second wide bandgap semiconductor layer and the second wide bandgap semiconductor layer are formed on the second wide bandgap semiconductor layer. A semiconductor memory element comprising an electrode for controlling carriers at an interface with the narrow bandgap semiconductor layer.