JPS5840855A - Semiconductor memory cell - Google Patents

Abstract

PURPOSE:To obtain a memory storage operating at high speed by holding a semiconductor layer with narrow forbidden band width Eg by the wide layer of the same conduction type Eg, attaching electrodes connected to the carriers of an interface with a central layer at both ends of one layer and forming the carrier control electrode of the interface by the other layer. CONSTITUTION:Si Added N-Ga0.7Al0.3As 2 (0.05-1mum thickness) in 5X10<15>- 3X10<16>cm<-3>, GaAs not added 3 (0.02-0.1mum thickness) and Si added N- Ga0.7Al0.3As 4 in the same concentration as the layer 2 are stacked onto semi-insulating GaAs 1, and mutually lattice-aligned, and each junction section has conduction-band stage difference or valence-band stage difference sufficient for confining carriers into the layer 2 with small Eg. The layer 2 is connected to the electrodes 5, 6, and the carrier control electrode 7 is shaped onto the layer 4 in size shorter than a section between the electrodes 5, 6. It is preferable that concentration difference among the layers 2, 4 and 3 is five hundred times or higher, and it is effective that layers not added 2', 4' with wide Eg are formed to these interfaces within the range of 20- 60Angstrom thickness. According to this constitution, the speed of the operation of the cell is increased.

Description

[Detailed description of the invention] The present invention relates to semiconductor memory elements.

The present invention provides a semiconductor memory element that is based on an operating principle different from that of, for example, an MO8 type memory having a floating gate tf, which has been used as a semiconductor memory element so far, and is capable of higher-speed operation.

In a semiconductor memory element, the speed of carrier movement determines the response speed of the element.

The device structure of the present invention greatly improves electron mobility compared to conventional MO8 type field effect transistors, thereby increasing the speed of device operation.

The basic structure of the semiconductor memory device of the present invention is as follows.

Since FIG. 1(a) is a top view of a typical example of the semiconductor memory device of the present invention, the principle will be explained using this. As will be described later, the semiconductor memory device of the present invention is not limited to this example.

It has a narrow forbidden band semiconductor layer 3 and two wide forbidden band semiconductor layers 2 and 4 sandwiching it, and the wide forbidden band semiconductor layer and the narrow forbidden band semiconductor layer are mutually connected to form a heterojunction at the interface between the two layers. is lattice matched. Furthermore, each of the heterojunctions has a conduction band step or valence band step large enough to confine carriers in the narrow bandgap semiconductor layer. One of the two wide bandgap semiconductor layers, for example, the semiconductor layer 2 near the substrate 1 (generally, a semi-insulating semiconductor substrate is used) is the first and second electrode 5.6 of the semiconductor device. (commonly referred to as source and drain polarization). A carrier control electrode is provided on the other wide forbidden band semiconductor layer 4. This control electrode may be provided directly on the semiconductor layer 4 or may be provided via an insulating layer. The impurity concentration of the two wide bandgap semiconductor layers 2.4 is the same as that of the narrow bandgap semiconductor layer 3.
It's thicker than that. It is convenient that the difference in concentration is 500 times or more. G a As - G a A tA
When using s-based materials, the narrow band gap semiconductor layer is non-conforming.
Concentration of impurities that are naturally mixed in during the manufacturing process of Dawg and pear.
Normally, the width is about I x 10"-I x 1015 cm-" or less, while the wide bandgap semiconductor layer is about 5 x 10" to 3 x
It is about 10"crn-". Carriers are secured in the potential well formed at the interface between the narrow bandgap semiconductor layer and the wide bandgap semiconductor layer, mainly due to the difference in impurity concentration in the amphibodiic conductor layer.

The two wide forbidden band layers 2.4 have the same conductivity type M.

The carriers 8 generated at the interface between the second wide bandgap semiconductor layer 4 and the narrow bandgap semiconductor layer 3 cause the first and second electric charges f! 5
．． It is constructed so that it does not come into electrical contact with 6. for example,
It is convenient to make the length of the wide forbidden band semiconductor layer 4 provided with the carrier control electrode 7 in the direction of the carrier running force shorter than the distance between the first and second t-poles 5°6. be.

Further, it is preferable to provide a wide forbidden band semiconductor layer without doping 1 at the interface between the narrow forbidden band semiconductor layer 3 and the wide forbidden band semiconductor layers 2 and 4. 1) is a sectional view showing this example. 2' and 4' are the undoped wide bandgap semiconductor layers. In the figure, other reference numerals are the same as in FIG. 1(a). This structure can achieve its purpose by stopping the doping of the wide bandgap semiconductor layer near the above-mentioned heterojunction, or by starting the doping only after forming a layer with no doping near the heterojunction. The appropriate thickness is about 20 to 60A.

It is possible to prevent impurities from diffusing from the wide bandgap semiconductor layer to the narrow bandgap semiconductor layer, and to reduce scattering of ionized impurities near the interface of the narrow bandgap semiconductor layer. Furthermore, it is also useful for preventing impurities in a wide bandgap semiconductor from diffusing into a narrow bandgap semiconductor layer.

The operation 71il of the storage device will be explained using FIG. FIG. 2 shows the conduction electron band of the energy band structure in the gate electrode portion of the device shown in FIG. The carrier control range +iA7 is determined by a Schottky electrode. 2, 3.4, and 7 in FIG. 2 indicate portions of the semiconductor layer having the same reference numerals as in FIG. 8° 9 indicates a two-dimensional electron gas generated at the interface between the two wide bandgap semiconductor layers 2.4 and the narrow bandgap semiconductor layer 3. 10 is the Fermi level.

2 when no voltage is applied to the control electrode 7 of the carrier.
The thickness and impurity concentration of the second wide bandgap semiconductor 14 are selected so that a dimensional electron gas exists.

Because there is a two-dimensional electron gas 8 existing at the interface,
The threshold voltage of the gate voltage for causing a current to flow between the source 5 and the drain 6 becomes thicker than in the case without this.

The current flowing between the source and drain is mainly due to the two-dimensional electron gas 90 traveling at the interface between the semiconductor layers 2 and 3.

Now, a pulsed negative potential is further applied in a superimposed manner, and the electron gas 8
By expelling the electrons from the potential well, no electrons exist at the interface between the semiconductor layers 3 and 4. In this state, the threshold voltage of the gate electrode portion decreases, so that the source-drain current increases for the same gate spiral voltage.

Therefore, the above two states can be defined as "0" in binary logic operation.
" and "l".

In this way, the present invention provides two carrier trapping regions of 11 regions each at the double heterojunction interface, and controls the presence of carriers in one of the trapping regions by a signal applied to the gate electrode to determine the presence or absence of carriers. High-speed dynamic memory was made possible by using the phenomenon in which one current influences the current flowing through the other capture region.

By using the semiconductor layer in the narrow forbidden band of the double heterojunction as an andog, eliminating impurity scattering, and lowering the temperature to eliminate phonon scattering, operation in less than 20 seconds is possible.

Note that when the carrier control electrode 7 is not biased, the depletion layer existing under the control electrode 7 is located between the wide forbidden band semiconductor layer 4 and the narrow forbidden band layer 3 near the control electrode 7. The two-dimensional magneton gas 8, which does not reach the heterojunction and therefore becomes a carrier, exists in the stepped portion of the energy generated at the heterojunction interface.

When the desired signal 'direct pressure' is applied to the control valve,
The depletion layer reaches the heterojunction on the side closer to the control electrode 7,
It is necessary that the carriers no longer exist in the energy step portion of the conduction band. Therefore, it is necessary to select the concentration and thickness of the dopant in the wide bandgap semiconductor layer closer to the control electrode 7 so as to satisfy the above conditions.

In order to make the carrier mobility in the present semiconductor memory element larger than the total room temperature and to prevent the carriers from deviating thermally from the step of the conduction band generated at the heterojunction surface, the effect of the present invention can be made more remarkable. Allow to cool to at least 100 ℃ or less.

Hereinafter, the present invention will be described in detail with reference to all embodiments.

Example 1 This example uses an undoped GaAs layer and an n-type GaAs layer.
This is an example of a high-speed dynamic memory that utilizes two-dimensional electron gas generated at the interface with the A 1o, 3A 6 layer. A sectional view of the main part thereof is shown in FIG.

5810 "cm-" on semi-insulating GaAs substrate 1
3 x 10"cm-" range 8i1)"-Peer fL
, tan-G a6. , A to, s , A-8 layer 2 (thickness 0.05 to 1 μm), and Anne layer 4 are grown. The well-known molecular beam epitaxial method was used as the growth method.

The molecular beam epitaxial method has advantages such as being able to rapidly change doping and being able to grow at low temperatures, and is convenient for manufacturing the memory device of the present invention.

The semiconductor substrate formed up to this point is not taken out from the growth chamber (the Cr, Ti, and Au are continuously evaporated, and the semiconductor layer 4 is removed from the growth chamber).
A Schottky junction is formed at the interface between the metal layer and the metal layer. This metal layer is processed into a gate electrode 7 by photolithography. Continuing, n-Gao under the gate electrode 7
, , Am, the (9) area other than the HAs area is removed by etching. Finally, Au-G e
The dynamic memory is completed by forming ohmic electrodes 5.6 using -Ni alloy.

This dynamic memory has the remarkable advantage that when operated at low temperatures, electron mobility increases and written information is less likely to be thermally lost.

In 77, the electron mobility in this dynamic memory is approximately 50,000 crn"V-'S-", which is extremely high speed.

The memory commit time was 400 pSec, and the read time was 200 psec.

Example 2 FIG. 3 is a sectional view of a main part showing another embodiment of the present invention.

This embodiment differs from the first embodiment in that the two-dimensional electron gas used for memory writing is formed by a buried gate electrode section.

In the figure, 11 is a semi-insulating GaAa substrate, 13 is an undoped G
aAs layer 0.2 μm, 21 is n-(10) Ga a6. , At(,,g As layer(n=8 X i
O"cm-", thickness 0.03μm), 20 is n
-G ao, Nimu, 3As layer (n=IX10"cm
-'', thickness 0.05 μm) 15°16 is the source and drain da, and i7 is the control gate.

On the semi-insulating GBAs substrate 1, by MBE method,
An As layer of 2.2 μIn is grown. Next, Si ions are implanted at a cutting speed voltage of 150 kV to form an n-type region 21, and annealing is performed at 850C.

The surface of the growth layer was coated with HgSO4:Hi to a thickness of 0.2 μm.
After etching with a mixed solution of O2'H*O (3' 1 + 1), water washing is performed for 2 hours to clean the surface and form an oxide film. Thereafter, the oxide film on the surface was removed by heating at 570C in an MBE apparatus, and then an undoped G ao, y A J, o, s A 8 layer 22.
40 people, Andog G a As layer 3.0,1μm1
Andog Gao, , Ato, , As layer 23.40 people,
Si doped (n”10”crn-”) Ga(,,,
Aj (,,, As layer 4.0.05 μm is grown sequentially by MBE method. Next, using phosphoric acid, peroxide (11) hydrogen, ethylene glycol (1:1:3) solution, 0.2 μm from the surface is grown. Mesa etching is performed to form an inverted mesa-shaped semiconductor region leaving the n-type region 21 in the center.

The ohmic electrodes 5 and 6 are thicker than this reverse mesa-shaped step.
f A u -G e -N i 7 o i (0,6
(μm thick). The ends 5' and 6' of the inverted mesa region are regions in which the semiconductor and electrode metal are alloyed. A control gate 17 is formed in a region above the buried floating gate 21 by laminating Ti, Pt, and Au. ``The lift-off method was used for polarization formation in both cases.

FIG. 4 shows a plan view and wiring state in the case of a single element. The buried gate 21 is not wired. The same numbers as in FIG. 3 indicate the same parts. In the case of an IC, wiring is formed on a commonly used interlayer insulating film having contact holes.

In this type of device, the electron gas accumulated at the hetero interface is 8 and 9, and 8 is connected to the outside through an ohmic electrode, and is used for signal reading.

(12) 8 is sucked out by the positive gas applied to the gate electrode 7, and the electron trap becomes empty. Therefore, the current-voltage characteristics in the channel 9 change, and information can be read out.

Embodiment 3 FIG. 5 is a sectional view of an improved memory element shown in Embodiment 1, which can operate at a temperature close to room temperature. Andog G a As layer 3t2J@31 in Example 1
．． It is divided into 32 layers, and between these layers n-Ga, -, At
, As (o<X<o, a) Jili33 has a structure with k insertion.

FIG. 6 shows the lower end of the conduction electron band of the energy band structure in the gate electrode portion of the device.

8.9 indicates a two-dimensional electron gas as in FIG. 2, and lO indicates the Fermi level.

The semiconductor layers 31 and 32 basically have the same properties as the semiconductor layer 3 described above.

This prevents the electron gases 8 and 9 from moving toward each other due to heat, and prevents stored information from thermally evaporating.

(13) If the electron mobility is cooled to 77■, the electron mobility will be greatly improved.
But that's fine.

Although the present invention has been described using a GaAs-GaAzAs sidetone example, other semiconductor materials may also be used.

For example, AzGaAs-AtGaAs, GaAs-A
tGaAsP, InP-InGaAsP, InP-I
Examples include HGIAs or llAs-GaAs8b.

[Brief explanation of the drawing]

FIGS. 1(a) and (b) are cross-sectional views of alternative semiconductor memory elements of the present invention, FIG. 2 is a band model diagram of the element in FIG. 1(a), and FIG. 3 is another embodiment. Figure 4 is a cross-sectional view of the element in Figure 3.
5 is a plan view of the embodiment shown in the figure, FIG. 5 is a sectional view of an element of another embodiment, and FIG. 6 is a band model diagram of the element of FIG. 5. DESCRIPTION OF SYMBOLS 1... Semi-insulating semiconductor substrate, 2, 4... Wide forbidden band semiconductor layer, 3... Narrow forbidden band semiconductor layer, 5#6... Electrode, 7... Control electrode for carrier, 8 .9...Two-dimensional electron gas. Agent Patent Attorney Toshiyuki Usuda (14) ￥J 1 Figure (a) (b) Figure Z Figure 3 Figure χ 4 Figure S Figure 6 Continued from page 1 [phase] Inventor Sakae Yamada Sanbe Kokubunji City Hitachi, Ltd. Central Research Laboratory, 1-280 Higashi-Koigakubo @ Inventor Michiharu Nakamura 258- Hitachi, Ltd. Central Research Laboratory, 1-280 Higashi-Koigakubo, Kokubunji City

Claims (1)

[Claims] 1. A narrow bandgap semiconductor layer and two wide bandgap semiconductor layers, a first and a second, are provided sandwiching the narrow bandgap semiconductor layer, and the first and second wide bandgap semiconductor layers are provided.
The wide forbidden band semiconductor layers are of the same conductivity type, and their impurity concentrations are large enough to confine carriers in the narrow band semiconductor layer at the two interfaces with the narrow band semiconductor layer. First and second semiconductor layers having a valence band step and connected to carriers at the interface between the first wide forbidden semiconductor layer and the narrow forbidden semiconductor layer in contact with the first wide forbidden semiconductor layer. an electrode is formed, the second wide bandgap semiconductor layer is not connected to the first and second electrodes, and the second wide bandgap semiconductor layer is connected to the second wide bandgap semiconductor layer and the second wide bandgap semiconductor layer. 1. A semiconductor memory element having a pole for controlling carriers at an interface with a narrow bandgap semiconductor layer. 2. The semiconductor memory element according to claim 1, wherein a thin, undoped wide band gap layer is present at the interface between the narrow band gap semiconductor layer and the first and second wide band gap semiconductor layers. It is characterized by consisting of: 3. In the semiconductor memory device according to claim 2, the undoped thin wide forbidden band layer has a thickness of 20 to 30%.
It is characterized by a thickness of 60A. 4. The semiconductor memory element according to claim 1 or 2, characterized in that the narrow bandgap semiconductor layer is not doped.