JPH0729940A - Semiconductor device - Google Patents

Abstract

PURPOSE:To provide a semiconductor device wherein a field effect transistor operates with high reliability, by improving heat dissipation efficiency. CONSTITUTION:In a semiconductor chip 31, a field effect transistor having a source earthing circuit is formed in the surface side region of a semiconductor substarate, and a gate electrode 32, a source electrode 23 and a drain electrode 34 are exposed on the surface side. A metal film 35 is formed on the surface from the upper part of the source electrode 33 to the rear along the side surface of the semiconductor chip 31. The surface side of the semiconductor chip 31 is bonded to an insulator board 1 by using conductive adhesive agent 37, in the manner in which the gate electrode 32, the source electrode 33, and the drain electrode 34 are electrically connected with an input wiring pattern, a metal wiring pattern, and an output wiring pattern, respectively. A heat sink 36 is bonded on the metal film 35 by using adhesive agent having an excellent thermal conductivity.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention has a semiconductor chip having a field effect transistor formed thereon mounted on an insulating substrate having a wiring pattern formed thereon. The present invention relates to a semiconductor device used as an output amplifier.

[0002]

2. Description of the Related Art Conventionally, a wire bonding method has been mainly used as a method of assembling a semiconductor chip.

FIG. 3 shows the structure of a conventional semiconductor device.
At the center of the insulating substrate 1, a semiconductor chip 21 having a field effect transistor formed in the front surface region is mounted with its back surface side adhered. A gate electrode 22, a source electrode 23, and a drain electrode 2 are provided on the front surface side of the semiconductor chip 21.
4 are formed, and the metal wires 25, 26, and
It is electrically connected to the input wiring pattern 41, the metal wiring pattern 42, and the output wiring pattern 43 formed on the insulating plate 1 via 27.

However, according to such a wire bonding method, the use of metal wires poses problems in workability and reliability. Therefore, various wireless bonding methods have been developed, and one of them is the flip chip method.

According to this flip-chip method, a semiconductor device is mounted on an insulating substrate such that a metal wiring pattern on the insulating substrate and a plurality of electrodes having a bump structure protruding from the semiconductor chip are almost directly connected to each other. It is formed by aligning and adhering the semiconductor chip to the semiconductor chip.

Note that such a prior art is disclosed in the document "IC
Packaging Technology, (Edit) Japan Microelectronics Association, (Issue) Industrial Research Committee, etc.

[0007]

According to the above conventional semiconductor device, since the field effect transistor is formed on the semiconductor substrate having high thermal resistance, a large amount of heat generated during operation is not well dissipated. There is a problem that a malfunction is caused.

Further, there is also a problem that heat generated from the field effect transistor promotes wear deterioration in each part of the field effect transistor.

Therefore, the present invention has been made in view of the above problems, and an object of the present invention is to provide a semiconductor device in which a field effect transistor functions with high reliability by improving a heat dissipation effect.

[0010]

The semiconductor device of the present invention comprises:
In order to achieve the above object, an insulating substrate having a metal wiring pattern formed on a surface thereof, and a semiconductor chip having a source electrode, a gate electrode and a drain electrode forming a field effect transistor exposed on the surface side. And a metal film is formed on the semiconductor chip from one electrode selected from the plurality of electrodes to the back surface along the side surface, and the metal film on the selected electrode and other It is characterized in that the front surface side of the semiconductor chip is arranged so as to face the insulator substrate and is bonded so as to directly connect the electrode to the metal wiring pattern.

It is preferable that the semiconductor chip has a heat dissipation plate bonded to a metal film arranged on the back surface.

[0012]

According to the present invention, the metal film is formed on one electrode exposed on the front surface side of the semiconductor chip and on the surface extending along the side surface to the back surface. Therefore, when the field effect transistor formed in the semiconductor chip operates, the Joule heat generated in the electrode and its vicinity conducts through the metal film and reaches the back surface side via the side surface of the semiconductor chip, so that the ambient air Well dissipated in. Therefore, the field effect transistor is cooled well.

Further, since the front surface side of the semiconductor chip is adhered to the insulator substrate, the metal film on one electrode and the other electrodes are directly connected to the metal wiring pattern on the insulator substrate. Therefore, since there is almost no parasitic inductance between these electrodes and the metal wiring pattern, the adverse effect on the electric signal of the field effect transistor is almost eliminated.

[0014]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS The structure and operation of an embodiment according to the present invention will be described below with reference to FIGS. In the description of the drawings, the same elements will be denoted by the same reference symbols, without redundant description.

First, the structure of one embodiment of the semiconductor device of the present invention will be described. 1A is a sectional view showing the structure of the present embodiment, and FIG. 1B is a plan view showing the structure of the semiconductor chip used in the embodiment of FIG. 1A.

An input wiring pattern 44 made of Al or the like, a metal wiring pattern (GND) 45, and an output wiring pattern 46 are formed in a predetermined arrangement on the insulating substrate 1, and the semiconductor chip 31 is placed on these. Has been done. Note that these wiring patterns may have a multilayer structure on the front surface side of the insulating substrate 1 or a throughput structure that communicates with the back surface side of the insulating substrate 1.

In the semiconductor chip 31, a field effect transistor having a source grounded circuit is formed in a front surface side region of a semiconductor substrate made of Si or the like, and transistor electrodes of a gate electrode 32, a source electrode 33 and a drain electrode 34 are formed on the front surface side. Have a bump structure and are exposed in a predetermined arrangement. Further, a metal film 35 made of Au or the like is formed by metal plating on the surface from the source electrode 33 to the back surface along the side surface of the semiconductor chip 31.

A conductive adhesive 37 is applied to the front surface side of the semiconductor chip 31 so as to connect the gate electrode 32, the metal film 35, and the drain electrode 34 to the input wiring pattern 44, the metal wiring pattern 45, and the output wiring pattern 46, respectively. It is used and adhered to the insulating plate 1. The source electrode 33 is grounded by being electrically connected to the metal wiring pattern 45. On the metal film 35 located on the back surface side of the semiconductor chip 31, a heat dissipation plate 36 made of Al, Cu, or the like is adhered with an adhesive having good thermal conductivity. The heat radiating plate 36 has a plate-shaped lower portion and a large number of upright rod-shaped upper portions.

The source electrode 33 coated with the metal film 35 includes not only the pad portion but also a metal exposed portion having the same potential. Further, the gate electrode 32 and the drain electrode 34 are formed to have substantially the same height as the height of the source electrode 33 and the metal film 35 on the surface of the semiconductor chip 31. further,
The gate electrode 32 and the drain electrode 34 are made of a conductive adhesive 37.
Are directly connected to the input wiring pattern 44 and the output wiring pattern 46, respectively.
It is connected to the metal wiring pattern 45 with a conductive adhesive 37 via 5.

Next, the operation of the above embodiment will be described.

When the field effect transistor formed on the semiconductor chip 31 operates, the Joule heat generated in the source electrode 33 and its vicinity conducts through the metal film 35 and reaches the back surface side of the semiconductor chip 31, and the heat dissipation plate 36 Dissipates well in the surrounding air. Therefore, since the field effect transistor is cooled well, malfunction due to heat generation is reduced. In addition, wear deterioration due to heat generation is reduced in each part of the field effect transistor.

Further, the metal film 3 for covering the source electrode 33
5, the gate electrode 32, and the drain electrode 34 are almost directly connected to the input wiring pattern 44, the metal wiring pattern 45, and the output wiring pattern 46, respectively. Therefore, there is almost no parasitic inductance between them, and the conductivity is satisfactorily enhanced. Therefore, the adverse effect on the electric signal of the field effect transistor is almost eliminated, and the malfunction is reduced.

Next, the configuration of an embodiment of a high output amplifier using the semiconductor device of the present invention will be described. Figure 2
It is sectional drawing which shows the structure of a present Example.

A small output transistor 2, a high output transistor 3, an input connector 5 and an output connector 6 are mounted on the insulating substrate 1 via wiring pattern portions 4, respectively. The small output transistor 2 has the same structure as the conventional semiconductor device, and the gate electrode 2 of the semiconductor chip 21 is
2. The source electrode 23 and the drain electrode 24 are electrically connected to the input wiring pattern 41, the metal wiring pattern 42, and the output wiring pattern 43 on the insulator substrate 1 via the metal wires 25, 26, and 27, respectively. On the other hand, the high-power transistor 3 is configured similarly to the semiconductor device of the present invention, and the gate electrode 32, the source electrode 33, and the drain electrode 34 of the semiconductor chip 31 are formed on the insulating substrate 1 by using the conductive adhesive 37. Are electrically connected to the input wiring pattern 44, the metal wiring pattern 45, and the output wiring pattern 46.

The input wiring pattern 41 is the input connector 5
In addition, the output wiring patterns 46 are electrically connected to the output connectors 6, respectively. Also, the output wiring pattern 43
The input wiring pattern 44 and the input wiring pattern 44 are electrically connected to each other.

Next, the operation of the above embodiment will be described.

The input signal input from the input connector 5 is output to the high output transistor 3 as an electric signal amplified by the small output transistor 2 with a relatively small amplification factor. The high output transistor 3 has a relatively high amplification factor and can function with high reliability by improving the heat dissipation effect and reducing the parasitic inductance as described above. Therefore, the electric signal input to the high-output transistor 3 is amplified with a relatively high amplification factor and is output to the output connector 6
Is output from.

The present invention is not limited to the above embodiment, but various modifications can be made.

For example, in the semiconductor device of the above embodiment, since the field effect transistor has the source ground circuit, the metal film is formed on the surface from the source electrode to the back surface along the side surface of the semiconductor chip. On the other hand, when the field effect transistor has a gate ground circuit and a drain ground circuit, by forming a metal film on the surface extending from the gate electrode and the drain electrode along the side surface of the semiconductor chip to the back surface, respectively, the same effect can be obtained. Is obtained.

[0030]

As described in detail above, according to the semiconductor device of the present invention, the metal film is formed on one electrode exposed on the front surface side of the semiconductor chip and on the surface extending along the side surface to the back surface. By being formed, the Joule heat generated by the operation of the field effect transistor conducts through the metal film, reaches the back surface side, and is well dissipated in the surrounding air.
Therefore, since the field effect transistor is cooled well, malfunctions due to heat generation and wear deterioration of each part are reduced.

Further, the semiconductor chip is bonded to the insulator substrate on the front surface side so that the metal film on one electrode and the other electrodes are almost directly connected to the metal wiring pattern on the insulator substrate. However, there is almost no parasitic inductance between these electrodes and the metal wiring pattern. Therefore, the adverse effect on the electric signal of the field-effect transistor is almost eliminated, and the malfunction is reduced.

Therefore, according to the present invention, the field effect transistor functions as a high power amplifier with high reliability.

[Brief description of drawings]

FIG. 1A is a sectional view showing a structure of an embodiment of a semiconductor device of the present invention, and FIG. 1B is a plan view showing a structure of a semiconductor chip used in the embodiment of FIG. .

FIG. 2 is a sectional view showing the configuration of an embodiment of a high-power amplifier using the semiconductor device of the present invention.

FIG. 3 is a perspective view showing a configuration of a conventional semiconductor device.

[Explanation of symbols]

1 ... Insulator substrate, 2 ... Small output transistor, 3 ... High output transistor, 4 ... Wiring pattern part, 5 ... Input connector, 6 ... Output connector, 21, 31 ... Semiconductor chip, 2
2, 32 ... Gate electrode, 23, 33 ... Source electrode, 2
4, 34 ... Drain electrode, 25, 26, 27 ... Metal wire, 35 ... Metal film, 36 ... Heat sink, 37 ... Conductive adhesive, 41, 44 ... Input wiring pattern, 42, 45 ... Metal wiring pattern, 43 , 46 ... Output wiring pattern.

─────────────────────────────────────────────────── ─── Continuation of the front page (51) Int.Cl. ⁶ Identification number Internal reference number FI Technical indication H01L 29/812 (72) Inventor Jiro Fukui 1 Tayacho, Sakae-ku, Yokohama-shi, Kanagawa Sumitomo Electric Industries Co., Ltd. Company Yokohama Works (72) Inventor Ryoji Sakamoto 1 Taya-cho, Sakae-ku, Yokohama-shi, Kanagawa Sumitomo Electric Industries, Ltd. Yokohama Works

Claims (2)

[Claims] 1. An insulating substrate having a metal wiring pattern formed on a surface thereof, and a semiconductor chip having a source electrode, a gate electrode and a drain electrode forming a field effect transistor exposed on the surface side, On the semiconductor chip, a metal film is formed from one electrode selected from the plurality of electrodes to the back surface along the side surface, and the metal film on the selected electrode and other A semiconductor device, wherein a front surface side of the semiconductor chip is arranged facing and bonded to the insulating substrate so as to directly connect the electrode to the metal wiring pattern. 2. The semiconductor device according to claim 1, wherein the semiconductor chip has a heat sink bonded to the metal film arranged on the back surface.