JPH07297295A - Mos transistor structure and charge transfer device with it - Google Patents

Abstract

PURPOSE:To provide a MOS transistor structure that realize a lower drain voltage without decrease of conversion ratio of output voltage to input voltage and decrease of margin of the output voltage. CONSTITUTION:An enhancement MOS transistor (A) is structured by forming a P type well region 14 that comprises a substrate with a two-layer structure of upper and lower layers, forming two N<++> type impurity regions 15 and 16 on a substrate surface side of P<+> type impurity region 14b of the upper layer of two layer structured P-type well region 14 and arranging a gate electrode 18 at the upper part of a channel region between these regions 15 and 16. A depletion type MOS transistor (B) is structured by forming 2 N<++> type impurity region 19 and 20 on the substrate surface side of P<+> type impurity region 14b, forming N<+> type impurity region 21 on the substrate surface side of channel region between these regions 15 and 16 and arranging a gate electrode 22 on it.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a MOS transistor structure and a charge transfer device using the same, and more particularly to an enhancement type MOS transistor and a depletion type M transistor.
MOS with OS transistor formed on the same substrate
The present invention relates to a transistor structure and a charge transfer device having an output section using the transistor structure.

[0002]

2. Description of the Related Art A MOS transistor circuit composed of a combination of an enhancement type MOS transistor and a depletion type MOS transistor is used as a source follower circuit forming an output section of a solid-state image pickup device, for example. Here, the enhancement type MOS transistor means that when a gate voltage is applied to a threshold voltage or more,
It is a MOS transistor of a type in which a drain current flows for the first time, and a depletion type MOS transistor is a type of MOS transistor in which a drain current flows even if a voltage is not applied to the gate.

In the case of manufacturing the enhancement type MOS transistor and the depletion type MOS transistor, a MOS transistor structure in which both types of transistors are formed on the same substrate is generally used in order to make the manufacturing process common and to reduce the cost. is there. Also, this M
Enhancement type M in the OS transistor structure
The P-type substrate forming the OS transistor and the depletion type MOS transistor is formed of a single layer.

[0004]

By the way, in the solid-state image pickup device, in order to increase the commercial value, the drain voltage having the highest voltage at the output portion is made to be low.
However, in the conventional MOS transistor structure in which the enhancement-type MOS transistor and the depletion-type MOS transistor are formed on the same substrate, when the drain voltage is reduced, the gate voltage also becomes low. In the transistor, the potential under the gate also becomes shallow, which causes accumulation of holes.

Here, accumulation means MOS.
In the structure, this is a phenomenon in which majority carriers are concentrated at the semiconductor interface in contact with the oxide film. Therefore, conventional MOS
In the transistor structure, when the drain voltage is lowered, the conversion ratio (gain) of the output voltage with respect to the input voltage is significantly reduced. In addition, there is a problem that the output voltage margin due to the power supply variation of the drain voltage, the potential variation, and the like disappears, and a stable output voltage cannot be guaranteed.

The present invention has been made in view of the above problems, and an object thereof is to reduce the drain voltage without decreasing the conversion ratio of the output voltage to the input voltage or eliminating the output voltage margin. It is to provide a MOS transistor structure capable of voltage conversion.

[0007]

In the MOS transistor structure according to the present invention, the substrate is a P-type substrate having an upper and lower two-layer structure, and two Ns formed on the surface side of the upper layer of the P-type substrate having the two-layer structure. An enhancement-type MOS transistor is formed by the gate-type impurity region and the gate electrode disposed above the channel region between the two N-type impurity regions, while it is formed on the surface side of the upper layer of the P-type substrate having the two-layer structure. A depletion type MOS transistor is constituted by the two N-type impurity regions, the N-type impurity region formed on the surface side of the channel region between the two N-type impurity layers, and the gate electrode arranged above the N-type impurity region. ing.

[0008]

In the MOS transistor structure having the above structure,
For example, if the impurity concentration of the upper layer of the two-layer structure is set higher than that of the lower layer, the potential under the gate does not change in the enhancement type MOS transistor due to the action of the upper layer when the drain voltage is lowered.
Therefore, it is possible to prevent accumulation of holes. On the other hand, in the depletion type MOS transistor,
The two-layer structure facilitates matching of the maximum potential and the minimum potential when the substrate voltage is constant.

[0009]

Embodiments of the present invention will now be described in detail with reference to the drawings. FIG. 6 is a configuration diagram showing an example of an interline transfer type CCD solid-state imaging device to which the present invention is applied. In FIG. 6, a plurality of photoelectric conversion elements 61 that are arranged two-dimensionally and photoelectrically convert incident light, and accumulate the signal charges obtained by the photoelectric conversion elements 61, and the plurality of photoelectric conversion elements 61 are arranged in each vertical column. An image pickup unit 63 is configured by a vertical transfer register 62 that vertically transfers the signal charges read from the photoelectric conversion element 61.

In this image pickup section 63, the photoelectric conversion element 6
1 is composed of a photodiode, for example, and the vertical transfer register 62 is composed of a CCD. The signal charges transferred to the vertical transfer register 62 are sequentially transferred to the horizontal transfer register 64 in units corresponding to one scanning line. The signal charges for one scanning line are sequentially transferred in the horizontal direction by the horizontal transfer register 64. Horizontal transfer register 64
A charge detection unit 65, which is, for example, an FDA (Floating Diffusion Amplifier) for detecting the transferred signal charges, is arranged at the final end of the.

In the charge detector 65, the signal charges transferred by the horizontal transfer register 64 are transferred to the floating diffusion FD via the output gate OG. This floating diffusion F
The potential of D is reset to the reset drain voltage V _RD in a predetermined cycle by the reset pulse φ _RG . In the subsequent stage of the charge detection unit 65, the floating
An output unit 66 that converts the signal charges transferred to the diffusion FD into a voltage and outputs the voltage is arranged.

The output section 66 includes drive-side MOS transistors Q _1D and Q _2D and load-side MOS transistors Q _1L and
It is configured by a two-stage source follower circuit composed of Q _2L . Then, the load side MOS transistors Q _1L , Q
The gates of _2L are commonly biased by the DC power supply 67, and the gate of the driving MOS transistor Q _{1D at} the first stage is connected to the floating diffusion FD of the charge detection unit 65.

In the output section 66, the drive side M of the first stage is
The OS transistor Q _1D has an enhancement type MOS transistor configuration, and has a second-stage drive-side MOS transistor Q _2D and load-side MOS transistors Q _1L , Q.
_2L has a depletion type MOS transistor configuration. An embodiment of the present invention applied to the source follower circuit that constitutes the output unit 66 of this CCD type solid-state image pickup device will be described below. The output unit 66 will be described as being formed on the same substrate as the main body of the CCD solid-state imaging device.

FIG. 1 is a sectional view showing a first embodiment of a MOS transistor structure according to the present invention. FIG. 1A shows a sectional structure of an enhancement type MOS transistor, and FIG.
Shows the cross-sectional structure of the depletion type MOS transistor. In FIG. 1, the same N as the apparatus main body
The first P-type well region 12 is formed on the type silicon substrate 11, and the second P-type well region 14 is formed as the P-type substrate of the output section 66 via the N-type impurity region 13.

The second P-type well region 14 includes a P-type impurity region 14a in the lower layer and a P-type impurity region 1 in the lower layer.
It has a two-layer structure including an upper P ⁺ type impurity region 14b having a higher concentration than 4a. In forming the second P-type well region 14, a thin concentration of impurity ions is ion-implanted into the region where the second P-type well region 14 is formed with a high energy, and then the same mask is used. Is used to implant a high concentration of impurity ions at low energy. As a result, the second P-type well region 14 can be easily doubled.

In FIG. 1A, on the substrate surface side of the P ⁺ type impurity region 14b in the upper layer of the second P type well region 14, two N ⁺⁺ type impurity regions 15 serving as a drain region and a source region are formed. , 16 are formed. A gate electrode 18 is provided above the channel region between the two N ⁺⁺ type impurity regions 15 and 16 with a gate oxide film 17 interposed therebetween. This forms an enhancement type MOS transistor.

In FIG. 1B, two N ⁺⁺ type impurity regions 19 serving as a drain region and a source region are formed on the substrate surface side of the P ⁺ type impurity region 14b in the upper layer of the second P type well region 14. , 20 are formed, and these two N
^An N ⁺ type impurity region 21 is formed on the substrate surface side of the channel region between the ⁺⁺ type impurity regions 15 and 16. The gate oxide film 1 is formed above the N ⁺ type impurity region 21.
A gate electrode 22 is arranged via 7. This constitutes a depletion type MOS transistor.

Considering the conventional example, in the conventional MOS transistor structure, the second P-type well region 14 which is a P-type substrate has a single layer structure. Therefore, when the drain voltage V _D is lowered, the gate voltage V _G is also lowered, but the conventional enhancement MO
In the S transistor, as shown by the broken line in FIG.
Since the potential under the gate also becomes shallow, there is a problem that accumulation of holes occurs. The solid line shows the potential before lowering the voltage.

On the other hand, even in the depletion type MOS transistor, the second P type well region 14 is formed under the same conditions as those of the enhancement type MOS transistor, so that the substrate voltage is kept constant as shown in FIG. 3B. Since it is difficult to match the maximum potential and the minimum potential of the depletion type MOS
Drain current that is dominant in the transistor and punch through that occurs between the N-type silicon substrate 11 and the gate electrode poses a problem.

On the other hand, in the MOS transistor structure according to the first embodiment having the above structure, the second P-type well region 1 is formed.
In the enhancement type MOS transistor (A), the drain voltage V _D is lowered and the gate voltage V _G is also lowered due to the P ⁺ -type impurity region 14 b having a high concentration on the substrate surface side of 4. As shown by the broken line in FIG. 2A, since the potential under the gate does not change, accumulation of holes in the second P-type well region 14 can be prevented.

As a result, even if the drain voltage V _D is lowered, the conversion ratio of the output voltage with respect to the input voltage is significantly reduced, and the output voltage margin is lost due to the power source variation and the potential variation of the drain voltage. Nothing. On the other hand, in the depletion type MOS transistor (B), the second P-type well region 14 is
Since the layered structure facilitates matching of the maximum potential and the minimum potential as shown in FIG. 2B, punch-through that occurs between the N-type silicon substrate 11 and the gate electrode 22 can be prevented.

FIG. 4 is a sectional view showing a second embodiment of the MOS transistor structure according to the present invention. FIG. 4A is a sectional view of an enhancement type MOS transistor, and FIG.
Shows the cross-sectional structure of the depletion type MOS transistor. In the figure, the same parts as those in FIG. 1 are designated by the same reference numerals. In FIG. 4, the first P-type well region 12 is formed on the same N-type silicon substrate 11 as the device body, and the second P-type well region 24 is shown in FIG. 6 via the N-type impurity region 13. The point that the output portion 66 is formed as a P-type substrate is the same as in the first embodiment.

The second P-type well region 24 has a two-layer structure consisting of a lower P ⁺ -type impurity region 24a and an upper-layer P-type impurity region 24b having a lower concentration than the lower P-type impurity region 24a. Has become. In forming the second P-type well region 24, a high concentration of high-energy impurity ions are implanted into the region where the second P-type well region 24 is formed using a mask, and then the same mask is used. Is used to implant a low concentration of impurity ions at low energy. As a result, the second P-type well region 24 can be easily doubled.

In FIG. 4A, on the substrate surface side of the P type impurity region 24b in the upper layer of the second P type well region 24, two N ⁺⁺ type impurity regions 15 serving as a drain region and a source region, 16 are formed. A gate electrode 18 is provided above the channel region between the two N ⁺⁺ type impurity regions 15 and 16 with a gate oxide film 17 interposed therebetween. This forms an enhancement type MOS transistor.

In FIG. 4B, on the substrate surface side of the P type impurity region 24b in the upper layer of the second P type well region 24, two N ⁺⁺ type impurity regions 19 serving as a drain region and a source region, 20 are formed, and the two N
^An N ⁺ type impurity region 21 is formed on the substrate surface side of the channel region between the ⁺⁺ type impurity regions 15 and 16. The gate oxide film 1 is formed above the N ⁺ type impurity region 21.
A gate electrode 22 is arranged via 7. This constitutes a depletion type MOS transistor.

In the MOS transistor structure according to the second embodiment having the above-described structure, the second P-type well region 24 has two
In the enhancement type MOS transistor (A), the potential under the gate becomes shallow as shown by the solid line in FIG. 5A because the P ⁺ type impurity region 24a having a high concentration is formed by layering, and the accumulation of holes is reduced. Since there is a sufficient margin for increasing the drain voltage V _D , the accumulation of holes does not occur even if the drain voltage V _D is lowered, as indicated by the broken line in FIG.

On the other hand, in the depletion type MOS transistor (B), the second P-type well region 24 is formed into two layers,
By forming the P ⁺ -type impurity region 24a having a higher concentration than the upper layer at a deep position under the gate, the potential of the P ⁺ -type impurity region 24a becomes shallower than before when the substrate voltage is set to the same voltage as before. . As a result, when the drain voltage is lowered, the potential under the gate becomes shallower as indicated by the broken line in FIG.
The problem of punch through that occurs between the type silicon substrate 11 and the gate electrode 22 can be improved.

In the above embodiment, the MOS transistor structure according to the present invention is applied to the output section of a so-called CCD area sensor in which photoelectric conversion elements are two-dimensionally arranged, but the photoelectric conversion elements are arranged in a line. The present invention can be similarly applied to the output section of the arranged so-called CCD line sensor and the output section of the CCD type delay element.

Furthermore, the present invention is not limited to the application to the output section of the charge transfer device, but an enhancement type MOS transistor and a depletion type MO transistor.
The S transistor can be applied to all MOS transistor structures formed on the same substrate.

[0030]

As described above, according to the present invention,
In a MOS transistor structure in which an enhancement-type MOS transistor and a depletion-type MOS transistor are formed on the same P-type substrate, the P-type substrate has an upper and lower two-layer structure, for example, the impurity concentration of the upper layer is set to be higher than that of the lower layer. As a result, when the drain voltage is lowered, the potential under the gate does not change in the enhancement-type MOS transistor, so that accumulation of holes can be prevented, and in the depletion-type MOS transistor, the maximum when the substrate voltage is constant is set. Since it is easy to match the potential and the minimum potential, it is possible to prevent punch-through between the substrate and the gate.

As described above, when the drain voltage is lowered, the gate voltage is also lowered, and it is possible to prevent accumulation of holes, which is a problem especially in the enhancement type MOS transistor, so that the output voltage is converted into the input voltage. The drain voltage can be lowered without lowering the ratio or eliminating the output voltage margin.

Further, by configuring the output part of the charge transfer device such as the charge transfer part and the delay element in the solid-state image pickup device by using the MOS transistor structure according to the present invention,
Decrease the conversion ratio of the output voltage to the input voltage,
Since the drain voltage can be lowered without losing the output voltage margin, it is possible to enhance the commercial value of the solid-state imaging device, the delay element, etc. by lowering the drain voltage which is the highest in the output section. .

[Brief description of drawings]

FIG. 1 is a cross-sectional view showing a first embodiment of the present invention.

FIG. 2 is a potential diagram according to the first embodiment.

FIG. 3 is a potential diagram according to a conventional example.

FIG. 4 is a sectional view showing a second embodiment of the present invention.

FIG. 5 is a potential diagram according to the second embodiment.

FIG. 6 is a configuration diagram of an example of a CCD solid-state imaging device.

[Explanation of symbols]

11 N-type silicon substrate 12 First P-well region 14, 24 Second P-well region (P-type substrate) 15, 16, 19, 20 N ⁺⁺ -type impurity region 21 N ⁺ -type impurity region 18, 22 Gate electrode

─────────────────────────────────────────────────── ─── Continuation of the front page (51) Int.Cl. ⁶ Identification code Internal reference number FI Technical indication H01L 21/339 29/78 H01L 29/78 301 H

Claims (4)

[Claims] 1. An enhancement type MOS transistor having a depletion type MOS transistor and an enhancement type MOS transistor formed on the same substrate, wherein the substrate is a P type substrate having a two-layer structure. Is the above 2
Two Ns formed on the surface side of the upper layer of the layered P-type substrate
Type impurity region and a gate electrode disposed above the channel region between the two N type impurity regions, the depletion type MOS transistor is formed on the surface side of the upper layer of the P type substrate of the two-layer structure. Two N-type impurity regions, an N-type impurity region formed on the surface side of the channel region between the two N-type impurity layers, and a gate electrode disposed above the N-type impurity region. MOS transistor structure characterized by. 2. The MOS transistor structure according to claim 1, wherein the impurity concentration of the upper layer of the P-type substrate having the two-layer structure is set higher than that of the lower layer. 3. The MOS transistor structure according to claim 1, wherein the P-type substrate having the two-layer structure has an upper layer impurity concentration set lower than an impurity concentration of the lower layer. 4. A charge transfer section for transferring signal charge, a charge detection section for detecting the signal charge transferred by the charge transfer section, and a signal charge detected by the charge detection section for converting into an electric signal. A charge transfer device comprising an output part for outputting, wherein the output part is constituted by using the MOS transistor structure according to claim 1, 2, or 3.