JP3144828B2 - Method for manufacturing solid-state imaging device - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to an amplifier of the output circuit or the amplifier built-in image sensor of C CD type image pickup device, to a method especially to reduce the 1 / f noise achieve low noise.

[0002]

2. Description of the Related Art Conventionally, a CCD solid-state imaging device has been widely used as a solid-state imaging device used in a home video camera or the like. This type of CCD solid-state imaging device is described in, for example, Technical Report of the Institute of Television Engineers of Japan, Vol.
No. pp. 61-66 (1989.2).

The CCD type solid-state image pickup device described in the above document has an element structure called an interline type shown in FIG. 9, and its output circuit comprises a two-stage source follower circuit shown in FIG. The constituent transistor has a cross-sectional structure shown in FIG. In FIG. 9, 81
Is a photodiode for performing photoelectric conversion, 82 and 83 are vertical CCDs and horizontal CCDs for transferring signal charges photoelectrically converted by the photodiodes, and 84 is an output circuit for detecting and outputting signal charges. The signal charges photoelectrically converted by the photodiode 81 are collectively sent to the vertical CCD 82,
Next, the data is transferred to the horizontal CCD 83 line by line, and then sequentially transferred in the horizontal CCD 83, converted into a voltage by the output circuit 84, and output to the outside of the element.

[0004] In FIG. 10, reference numerals 92 and 93 denote driver transistors constituting a first-stage source follower, respectively.
Load transistors 94 and 95 are driver transistors and load transistors constituting the next-stage source followers, respectively, and 91 is a reset transistor for resetting a floating diffusion layer to which signal charges are sent from the horizontal CCD 96 every transfer cycle of the horizontal CCD. It is. Also, RD, R
G is the reset voltage and reset pulse terminal of the floating diffusion layer, VG is the gate voltage terminal of the load transistor,
OD is a power supply voltage terminal of the output circuit. The signal charges are transferred from the horizontal CCD 96 to the floating diffusion layer, and the resulting potential change is detected by the first-stage source follower including the transistors 92 and 93, and output to the outside of the element by the next-stage source follower including the transistors 94 and 95. Next, the reset pulse is applied to the reset transistor 9.
1 and the floating diffusion layer is reset to a reset voltage. The above operation is repeated, and signals are sequentially output. Note that transistors 91, 93 to 95 are depletion type transistors, and transistor 92 is an enhancement type transistor. FIG. 11 is a diagram showing the A- of the first-stage source follower driver transistor 92 in FIG.
FIG. 3 is a view showing a cross-sectional structure diagram of A ′, in which a polysilicon gate 5 is formed in a double well 3 in a p-well 2 formed on an n-type substrate 1, and an n + serving as a drain source is self-aligned therewith. Diffusion layer 4 and first layer aluminum 9 are formed.

[0005]

The noise of the above conventional example is as follows.
It mainly occurs in the output circuit 84. The noise of the output circuit is
It comprises reset noise caused by the thermal noise of the reset transistor 91, 1 / f noise of the transistor constituting the output circuit, and thermal noise. According to the knowledge of the authors, among these three components, the reset noise is obtained by the correlated double sampling method.
Further, thermal noise can be reduced by shortening the channel of the transistor. As a result, 1 / f noise was the main cause of the noise, and the upper limit of the signal-to-noise ratio was generated.

This problem is a problem not only in a CCD solid-state imaging device but also in a solid-state imaging device having a built-in amplifier for detecting and amplifying an optical signal charge, such as a line amplification MOS imaging device or a pixel amplification imaging device. is there.

[0007]

An object of the present invention is to provide a CCD type solid-state imaging device,
The 1 / f noise of the amplifying solid-state imaging element of the line amplifier MOS type image pickup device and the pixel amplifying type imaging device is reduced, it is to improve the signal-to-noise ratio.

[0009]

In order to achieve the above object, an amplifier for detecting and amplifying an optical signal of an amplifying solid-state imaging device such as a CCD solid-state imaging device, a line amplification MOS imaging device, or a pixel amplification imaging device is provided. Fluorine ions were implanted into the formation region. More specifically, M
After forming the gate of the OS transistor, fluorine ions were implanted into the source and drain of the MOS transistor. Alternatively, fluorine ions were implanted into the source / drain of the junction field effect transistor constituting the amplifier .

[0010]

[Action] CCD type solid state imaging device, by fluorine optical signal driven into the formation region of the amplifying device for detecting amplification of the amplification type solid-state imaging device of the line amplifier MOS type image pickup device and the pixel amplifying type imaging element, 1 / f noise interface state of SiO ₂ -Si interface causing inactivates, 1 / f noise is reduced. In the CCD type solid-state imaging device and the amplification type solid-state imaging device,
By limiting the implantation of fluorine to the region where the amplifier is formed and not implanting the photoelectric conversion element, the 1 / f noise reduction of the amplifier can be reduced without causing damage to the photoelectric conversion element due to the ion implantation of fluorine. I can do it. Further, when fluorine is implanted into the source / drain after the gate of the MOS transistor is formed, fluorine is introduced into the semiconductor substrate without damaging the gate oxide film due to the ion implantation of fluorine, and the fluorine is diffused in the subsequent thermal process to diffuse the gate. The interface state of the lower SiO ₂ -Si interface is inactivated,
1 / f noise is that to reduce.

[0011]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS First Embodiment A first embodiment in which the present invention is applied to a CCD type solid-state imaging device will be described with reference to FIGS. FIG. 1 is a cross-sectional view showing a manufacturing process of the first embodiment.
Corresponds to the section BB 'of FIG. FIG. 2 is a graph showing a noise spectrum of a first-stage source follower using the MOS transistor manufactured by the manufacturing process of FIG.

In this embodiment, the overall configuration and the output circuit configuration are the same as those shown in FIGS. 9 and 10, respectively. Also, the cross-sectional structure is the same as that of FIG. 11 except that fluorine is implanted in the source / drain diffusion layer 4. Further, the operation is performed in the same manner as in the related art. Hereinafter, the manufacturing process of this embodiment will be described with reference to FIG. In FIG. 1, 1
5 and 9 is similar to FIG. 1 1, 6 photodiode n layer, 7 CCDn layer, 8 photoresist film, 10 is a second layer aluminum light shielding. P well 2 on n-type substrate 1
Double well 3, CCD n layer 7, polysilicon gate 5,
Photodiode n layers 6 are sequentially formed. Next, a photoresist film 8 is formed in all regions except for a region where a drain and a source of a MOS transistor constituting an output circuit are formed,
After impurities are implanted to form the n tens diffusion layer 4, a photoresist film 8 of the same over as a mask, fluorine is ion implantation (FIG. 1 (a), (c) ). Thereafter, P layers on the surface of the photodiode, a first layer aluminum 9 for wiring, and a second layer aluminum 10 for light shielding are sequentially formed (FIG. 1).
(B) , (d) ).

FIG. 2 shows a MOS formed by fluorine implantation as described above.
One example in which the 1 / f noise reduction effect of a first-stage source follower using a transistor is measured. Implanting 1E16 / cm ² of fluorine reduces 1 / f noise to about 1/3.

According to the present embodiment, by implanting fluorine into the source / drain of the MOS transistor constituting the output circuit of the CCD type image pickup device, the 1 / f noise is reduced and the CCD type solid-state having a high signal-to-noise ratio is obtained. An image sensor can be realized. Further, by implanting fluorine simultaneously with the formation of a high concentration n + layer only in the output circuit portion, 1 / f noise of the output circuit can be reduced without damaging the photodiode. Further, by implanting fluorine into the source / drain after forming the gate, 1 / f noise can be reduced without damaging the gate oxide film.

Second Embodiment In the first embodiment, the drain and the source constituting the output circuit are formed of a high-concentration single-diffusion layer. However, the breakdown voltage of the MOS transistor is increased so that a short-channel transistor can be used. There are various variants for The present invention is applicable regardless of the configuration of the drain source diffusion layer. FIG. 3 is a cross-sectional view taken along the line AA ′ of FIG. 10 showing a manufacturing process when the present invention is applied to the offset drain structure described in FIG. 13 of Japanese Patent Application No. 2-41078 as one example . FIG. In the drawing, 1 to 5 are the same as those in FIG. 1, 32 is an offset drain diffusion layer formed at a fixed distance from the polysilicon gate 5, and 31 is provided between the diffusion layer 32 and the polysilicon gate 5. A lower concentration impurity layer having the same polarity as that of the diffused layer 33, 34 is a photoresist film.
Hereinafter, the manufacturing process of this embodiment will be described. After the polysilicon gate 5 is formed, phosphorus is ion-implanted using the photoresist film 33 and the polysilicon gate 5 as a mask to form a low-concentration impurity layer 31. Thereafter, using the same photoresist film as a mask, fluorine is used. Is ion-implanted ( FIG . 3A). Then, the polysilicon gate 5
And a photoresist film 34 formed at a distance of only X
Is used as a mask to implant As to form the offset drain diffusion layer 32 ( FIG. 3B ).

According to the present embodiment, thermal noise is reduced by using a MOS transistor having a high withstand voltage and a short channel transistor can be used, and 1 / f noise reduction similar to the first embodiment can be achieved. The noise can be reduced in the output circuit of the CCD solid-state imaging device. In addition, the above-mentioned first and second
In the embodiment, fluorine is implanted using a photoresist film for impurity implantation for forming the source and drain of the MOS transistor as a mask. However, pattern formation for limiting the implantation of fluorine to the formation region of the output circuit may be performed. good.

Further, in the above-described first and second embodiments, the case where the MOS transistor constituting the output circuit is an n-channel transistor has been described, but the same applies to the case where the MOS transistor is a p-channel transistor.

In the first and second embodiments described above,
The case where the first-stage source follower driver transistor 92 is of an enhancement type and the first-stage source follower load transistor 93, the next-stage source follower driver transistor 94, and the next-stage source follower load transistor 95 are of the depletion type has been described. The same applies regardless of the combination of transistor types.

In the first and second embodiments described above,
MOS is provided in the p well 2 and the p + double well 3 of the n-type substrate 1.
Although the case where a transistor is formed was described, the present invention
It goes without saying that the present invention can be carried out without depending on the substrate structure.

In the first and second embodiments described above,
Although the case of the source follower has been described, the present invention has the same effect in other circuit configurations such as an inverter.

[0021]

[0022]

Third Embodiment The reduction of 1 / f noise is necessary not only for the CCD type imaging device but also for the overall noise reduction of a solid-state imaging device incorporating an amplifier for detecting and amplifying optical signal charges. This embodiment is an invention of a line-amplification MOS type image sensor described in the Technical Report of the Institute of Television Engineers of Japan, Vol. 14, No. 16, pp. 25-30 (1990.2.) Is applied. FIG. 4 is an overall configuration diagram of a line amplification MOS type imaging device, FIG. 5 is a cross-sectional view of a p-channel MOS transistor showing a manufacturing process of the first embodiment, and a sectional view taken along line AA 'of FIG. 4, and FIG. N-channel M made by manufacturing process
4 is a graph showing a noise spectrum of an OS transistor. 4, reference numeral 41 denotes a photodiode for performing photoelectric conversion; 42, a vertical switch which is opened and closed by a vertical scanning circuit 48; 47, a vertical signal line; 43, a row amplifier for detecting and amplifying a potential change of the vertical signal line; CDS circuit that holds the signal at 1 after removing reset noise from the output, 4
Reference numeral 5 denotes a horizontal switch that is opened and closed by a horizontal scanning circuit 46. The row amplifier 43 and the CDS circuit 44 have an n-channel M
It is composed of an OS transistor and a p-channel MOS transistor. The signal charge photoelectrically converted by the photodiode 41 is read out to the vertical signal line 47 through the vertical switch 42 opened by the selection signal of the vertical scanning circuit 48, and the potential change of the vertical signal line due to the signal charge at this time is detected by the row amplifier. It is amplified by 43 and temporarily held after the reset noise is removed by the CDS circuit 44. Next, the horizontal switch 45 is sequentially opened and closed by the selection signal of the horizontal scanning circuit, and the signal is read out of the element.

The n-channel MOS transistor and the p-channel MOS transistor constituting this element are formed by the manufacturing steps shown in FIG. The left and right diagrams of FIG. 5 respectively show the P-channel MOS transistor and the A-channel transistor of FIG.
The manufacturing process of A 'part is shown. In the figure, 51 is an n-type substrate, 52 is an n-well, 53 is a p-well, 54 is a photodiode n-layer, 55 is a source / drain diffusion layer of an n-channel MOS transistor, and 56 is a LOCO for element isolation.
An S oxide film, 57 is a polysilicon gate, 58 and 59 are photoresist films, and 60 is a source / drain diffusion layer of a P-channel MOS transistor. On an n-type substrate 51, an n-well 52, a P-well 53, a LOCOS oxide film 56, a photodiode n-layer 54, and a polysilicon gate 57 are sequentially formed. Next, a photoresist film 58 is formed on the n-type photodiode 54 and the n-well 52 which is a formation region of the pMOS transistor, and after an impurity for forming the n-ten diffusion layer 55 is implanted, the same photoresist film 58 is as a mask, fluorine is ion implantation (FIG. 5 (a), (c) ). Thereafter, a photoresist film 59 is formed.
Is formed on the n-type photodiode 54 and the p-well 53, which is a region for forming the nMOS transistor, and is implanted with impurities for forming the p-ten diffusion layer 60. Then, fluorine is doped using the same photoresist film 59 as a mask. It is ion-implanted (FIG. 5 (b), (d) ). Note that the source / drain diffusion layer of the n-channel MOS transistor is n
The ten diffusion layers 55 are formed at the same time.

FIG. 6 shows an example in which the effect of reducing the 1 / f noise of the n-channel MOS transistor by the above-described fluorine implantation is measured. The amount of implanted fluorine ions is 5E14
/ Cm2 to 2E16 / cm2. As the amount of fluorine implanted increases, 1 / f noise decreases. However, if the amount of implantation exceeds 1E16 / cm 2, the 1 / f noise tends to increase on the contrary due to damage caused by the implantation.
Indicated . In this measurement example, 1 / f noise can be reduced by about 1/10 by implanting fluorine of 1E16 / cm 2.

As described above, according to the present embodiment, the n-channel M that forms the row amplifier 43 and the CDS circuit 44
By implanting fluorine into the source and drain of the OS transistor and the p-channel MOS transistor, 1 /
It is possible to realize a line amplification type solid-state imaging device having a reduced f-noise and a high signal-to-noise ratio. Further, the photodiode n
The layer is not implanted with fluorine and does not damage the photodiode. Further, by implanting fluorine into the source / drain after forming the gate, 1 / f noise can be reduced without damaging the gate oxide film.

Fourth Embodiment In the third embodiment, fluorine is also applied to the vertical scanning circuit 48, horizontal scanning circuit 46, vertical switch 42, and horizontal switch 45. However, the 1 / f generated at these locations
Noise has no bearing on the performance of the device. Rather,
Damage due to fluorine implantation can have a negative effect. FIG. 7 shows a row amplifier 43 and a CDS circuit 4 for detecting, amplifying and transmitting fluorine as signal charges in order to avoid this adverse effect.
It is a top view which shows the Example limited to 4 and driving in. In the figure, 41 to 48 are the same as in FIG. 5, and 61 indicates a fluorine-implanted region. Hereinafter, the manufacturing process will be described. As shown in FIG. 5, after the n + diffusion layer 55 and the p + diffusion layer 60 are formed, a photoresist film is formed in all regions except the region 61, and fluorine is ion-implanted only in the row amplifier 43 and the CDS circuit 44. Is done.

According to the present embodiment, the vertical scanning circuit 48, the horizontal scanning circuit 46, the vertical switch 42, and the horizontal switch 45
Fluorine is implanted into the row amplifier 43 and the CDS circuit 44 without damaging the line amplifier, thereby realizing a line amplification type solid-state imaging device having a high signal-to-noise ratio.

Further, in the third and fourth embodiments, the MOs constituting the row amplifier 43 and the CDS circuit 44 are provided.
Although the case where the S transistor has both the n-channel transistor and the p-channel transistor is described, the same applies to the case where only the n-channel transistor or only the p-channel transistor is used.

It is needless to say that the present invention can be implemented without depending on the substrate structure or the specific circuit configuration of the row amplifier 43 and the CDS circuit 44.

Fifth Embodiment This embodiment is directed to a pixel amplification type element in which an amplifier is provided for each photoelectric conversion element, which is a kind of solid-state image pickup device with built-in amplifier.
It is an example to which the present invention is applied. The pixel amplifying type element of this embodiment is described in Proceedings 3-4 of the National Convention of the Institute of Television Engineers of Japan, 5
1-52 (1986.7). In FIG.
2 illustrates a circuit configuration of a pixel. In the figure, reference numeral 71 denotes an amplifying MOS transistor; 72, a photodiode for performing photoelectric conversion;
Is a selection switch, and 74 is a switch for resetting the photodiode 72. The signal charge photoelectrically converted by the photodiode 72 is amplified and output by the amplification MOS transistor 71 when the switch 73 is turned on. Thereafter, when the switch 74 is turned on, the signal charge of the photodiode 72 is reset. Fluorine is implanted into the source / drain diffusion layers of the MOS transistors provided at the A and B terminals in the figure by performing pattern formation in the same manner as in the fourth embodiment.

According to the present embodiment, it is possible to realize a pixel amplification type solid-state image pickup device having a MOS transistor having a high signal-to-noise ratio with a reduced 1 / f noise as an amplification transistor. Furthermore, no fluorine is implanted in the photodiode n layer, and the photodiode is not damaged. Further, by implanting fluorine into the source / drain after forming the gate, 1 / f noise can be reduced without damaging the gate oxide film.

[0033]

[0034]

[0035]

According to the present invention, a CCD type solid-state imaging device, a line amplification MOS type imaging device, a MOS transistor constituting an amplifier for detecting and amplifying an optical signal of a pixel amplification imaging device or 1 / f of a junction type field effect transistor. Noise power can be reduced to about 1/10 without damaging the photoelectric conversion element.
And a solid-state imaging device having a high signal-to-noise ratio can be realized.

[0036]

[Brief description of the drawings]

FIG. 1 is a cross-sectional view of a portion corresponding to FIGS. 10A-A 'and 9B-B', showing a manufacturing process of an embodiment of a CCD type imaging device of the present invention.

FIG. 2 is an initial source follower noise spectrum showing the effect of the present invention.

FIG. 3 is a cross-sectional view of a part corresponding to FIG. 10A-A 'showing a manufacturing process of another embodiment of the CCD type imaging device of the present invention.

FIG. 4 is an overall configuration diagram of a line amplification MOS type imaging device.

FIG. 5 is a cross-sectional view of a p-channel MOS transistor and a sectional view of FIG. 4A-A 'showing a manufacturing process of one embodiment of the line amplification MOS type image pickup device of the present invention.

FIG. 6 is a noise spectrum of an n-channel MOS transistor showing the effect of the present invention.

FIG. 7 is a plan view showing another embodiment of the line amplification MOS type imaging device of the present invention.

FIG. 8 is a circuit configuration diagram showing one embodiment of a pixel amplification type imaging device of the present invention.

FIG. 9 is an element configuration diagram of a conventional CCD type imaging element.

FIG. 10 is a circuit configuration diagram of an output circuit of the CCD type imaging device of FIG. 9;

FIG. 11 is a sectional structural view taken along the line AA ′ of FIG. 10;

[Explanation of symbols]

1,51 ... n-type substrate, 2,53 ... p well, 3 ... double well, 4,55 ... n + diffusion layer, 5,57 ... polysilicon gate, 6,54 ... photodiode n layer, 7 ... CCDn
Layers, 8, 33, 34, 58, 59 ... photoresist film, 9
... first layer aluminum, 10 ... second layer aluminum for light shielding, 31 ... low concentration impurity layer, 32 ... offset drain diffusion layer, 4
1, 72, 81 photodiode, 42 vertical switch, 43 row amplifier, 44 CDS circuit, 45 horizontal switch, 46 horizontal scanning circuit, 47 vertical signal line, 51
... n-type substrate, 52 ... n well, 56 ... LOCOS oxide film, 60 ... p + diffusion layer, 61, A, B ... fluorine implantation region, 71 ... amplification MOS transistor, 73 ... selection switch, 74 ... reset switch , 82 ... Vertical CC
D, 83: horizontal CCD, 84: output circuit, 91: reset transistor, 92: initial stage source follower driver transistor, 93: initial stage source follower load transistor, 94: next stage source follower driver transistor, 95: next stage source follower load transistor .

──────────────────────────────────────────────────続 き Continuing on the front page (72) Inventor Toshiaki Sano 3681 Hayano Mobara City, Chiba Prefecture Within Hitachi Device Engineering Co., Ltd. (56) References JP-A-1-243462 (JP, A) JP-A-64-32640 (JP, A) JP-A-2-266565 (JP, A) (58) Fields investigated (Int. Cl. ⁷ , DB name) H01L 21/336 H01L 21/339 H01L 27/14 H01L 27/146 H01L 27/148 H01L 29/762 H01L 29/78 H04N 5/335

Claims (2)

(57) [Claims] A photodiode group is formed on a semiconductor substrate.
Generated by photoelectric conversion by the photodiode.
It is composed of MOS transistors that amplify signal charges
Forming an amplified amplifier; and
Forming a photoresist film;
Using the above photoresist film as a mask for the source and drain of the
And a step of implanting fluorine ions
Of manufacturing a solid-state imaging device. (2) The fluorine ion implantation step is 5E14 /
cm ^Two From 2E16 / cm ^Two Fluorine ions in the range of
A method for manufacturing a solid-state imaging device, which comprises: