JPH07297287A - Integrated circuit - Google Patents

Abstract

PURPOSE:To use an arbitrary number of function circuits out of a plurality of function circuits with the same function and at the same time reduce the number of function control terminals. CONSTITUTION:2<n-1> function circuits 2-8 out of a plurality of function circuits 2-8 formed separately on a same chip are grouped into function circuit parts 10A-10C consisting of 2<0>, 2<1>... 2<n-1> function circtuits 2, 3, 4, and 5-8 and function control terminals P2, P8, and P20 shared by each function circuit are given, one to each part, to the function circuit parts l0A-10C for distributing a total of n parts, thus using an arbitrary number of up to 2<n-1> function circuits 2-8 and at the same time achieving an integrated circuit where the total number of terminals can be reduced by 2<n>-1-n as compared with be ore.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an integrated circuit, and can be applied, for example, to a standard logic integrated circuit in which a plurality of the same logic circuits are arranged on the same chip.

[0002]

2. Description of the Related Art Conventionally, there is a standard logic integrated circuit of this type in which a plurality of logic circuits capable of suppressing power consumption when not in use are arranged. As shown in FIG. 2, a standard logic integrated circuit (hereinafter referred to as a standard logic IC) 1 is formed on one semiconductor chip and includes seven separate inverter circuits 2 to 2.
8 are arranged. Further, the standard logic IC 1 includes the input / output terminals of the inverter circuits 2 to 8 and the power suppressing terminals P ₁ to
_{P 3, P 4 ~P 6 ......} P 19 ~P 21 are arranged respectively. The user can select arbitrary power suppression terminals P ₂ , P _5, ...
By using P ₁₇ and P ₂₀ , the power consumption of the entire standard logic IC1 and the power consumption of the entire device using the standard logic IC1 have been reduced.

When using, for example, four inverter circuits 2 to 5 out of the seven inverter circuits 2 to 8, the user needs to limit the power control terminals P ₁₄ and P of the three inverter circuits 6 to 8 that are not used. ₁₇ , switches the logic level given to P ₂₀ . As a result, the power consumption of the inverter circuits 6 to 8 is suppressed by, for example, disconnecting the power source of the inverter circuits 6 to 8.

[0004]

However, in the standard logic IC 1 having the above-mentioned configuration, in order to achieve the usage method of separately suppressing the power consumption of the unused inverter circuit among the inverter circuits 2 to 8, seven power suppressing terminals are provided. Was needed. In addition, 21 terminals were required in total, including these 7 power suppression terminals.

Generally, in a standard logic IC having 2 ⁿ -1 separate logic circuits having a power consumption suppressing function, 2 ⁿ -1 power suppressing terminals are required. As a result, when logic circuits each having m functional terminals such as input / output terminals in addition to the power suppression terminal are separately arranged in the standard logic IC, the total number of IC terminals (pins) is m (2 ⁿ
This is a very large number of −1) + (2 ⁿ −1).

Therefore, the package of the standard logic IC is [m
There has been a problem that (2 ⁿ -1) + (2 ⁿ -1)] IC terminals are arranged and the size is increased. Similarly, in the chip layout in which the standard logic IC1 is formed, the number of pads for outputting the input / output terminals increases. As a result, the size of the chip is increased accordingly, the number of chips formed on the semiconductor wafer is limited, and the theoretical yield is lowered. This drawback becomes remarkable as the pad area becomes relatively large as the process rule of the IC becomes finer.

The present invention has been made in consideration of the above points, and an integrated circuit capable of using an arbitrary number of functional circuits among a plurality of functional circuits having the same function and reducing the number of function control terminals. Is to propose.

[0008]

In order to solve such a problem, in the present invention, functional circuits 2 to 2 having the same function are provided.
Integrated circuit 1 in which a plurality of 8 are separately formed on a semiconductor chip
0, 2 ⁿ -1 functional circuits 2 to 8 among the plurality of functional circuits are grouped into 20 ⁰ , 2 ¹ ... 2 ⁿ -1 groups, respectively. Function control terminals P ₂ and P that commonly control the functions of all the functional circuits grouped into the functional circuit units 10A to 10C.
₈ and P ₂₀ should be placed one each.

[0009]

Of the plurality of functional circuits 2-8 separately formed on the same chip, 2 ⁿ -1 functional circuits 2-8 are set to 2 ⁰ , 2
¹ ... 2 ^n-1 functional circuits 2, 3 and 4, 5 to 8 are divided into functional circuit units 10A to 10C, and the functional control terminals P ₂ and P are shared by each functional circuit group.
_8, giving one the P ₂₀ to each of the functional circuit portion 1OA - 1OC, Yotsute that total to n number distribution, with may use any number of functional circuits 2-8 to -1 2 ⁿ , The total number of terminals can be reduced by 2 ⁿ -1-n compared with the conventional one.

[0010]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment of the present invention will be described in detail below with reference to the drawings.

In FIG. 1 in which parts corresponding to those in FIG. 2 are designated by the same reference numerals, 10 indicates a standard logic IC formed on one semiconductor chip as a whole, and the logic circuit sections 10A to
10C is arranged.

The logic circuit section 10A is composed of one inverter circuit 2 and is provided with a power suppressing terminal P ₂ . The logic circuit section 10B is composed of two inverter circuits 3 and 4, and the power suppression terminal P ₈ is shared by the inverter circuits 3 and 4. The logic circuit section 10C includes four inverter circuits 5-5.
In this case, the power suppression terminal P ₂₀ is shared by the inverter circuits 5 to 8.

The logic circuit sections 10A to 10C are individually set to the active state by changing the logic levels of the power suppressing terminals P ₂ , P ₈ and P ₂₀ . As a result, one, two, and four inverter circuits are simultaneously set to the active state.

In the above configuration, the inverter circuits 2 to
When using one inverter circuit of 8, the user selects only the power suppression terminal P _2, to change the logic level. When using two inverter circuits, the user selects only the power suppression terminal P ₈ and changes this logic level. Similarly, when using three, four, five, six, and seven inverter circuits, respectively, the user has
₂ and P ₈ , P ₂₀ , P ₂ and P ₂₀ , P ₈ and P ₂₀ , P ₂
, And the combination of P ₈ and P ₂₀ is sequentially selected to change its logic level. As a result, any number of inverter circuits from 1 to 7 can be set to the active state.

The inverter circuit, respectively ^{2 0, 2 1 ...... 2 n} -1 pieces of the thus 2 ⁿ -1 pieces which are separately formed on one chip by (n = 3 next seven pieces in this case) Only n (here, n = 3) power suppression terminals that are sequentially shared by (1, 2, and 4 here) are arranged. Thereby, the user can select any number of inverter circuits up to 2 ⁿ -1 (here, 7) by combining and selecting n power control terminals in any order.

When the inverter circuits 2 to 8 each have m input / output terminals (m = 2 in this case), the total number of terminals is m (2 ⁿ -1) + n. The number of terminals is (m + 1) (2 ⁿ −1) − because the total number of terminals in the related art is m (2 ⁿ −1) + (2 ⁿ −1).
Decrease by {m (2 ⁿ -1) + n} = 2 ⁿ -1-n. Therefore, here, the number of terminals is reduced by 4 from the conventional one, and the total number of terminals is 17. Similarly, m = 3, n = 5
, The number of terminals is (3 + 1) (2 ⁵ −1) − {3
(2 ⁵ −1) +5} = 124−98 = 26 is reduced.

According to the above construction, 2 ⁿ − of the plurality of inverter circuits 2 to 8 separately formed on the same chip.
One inverter circuit 2 to 8 is grouped into logic circuit sections 10A to 10C composed of 2 ⁰ , 2 ¹ ... 2 ^n-1 inverter circuits 2, 3 and 4, 5 to 8, and each inverter circuit is divided into groups. Power suppression terminal P ₂ shared by
1 P _8, P ₂₀ in each of the logic circuit portion 10A~10C
By providing a total of n pieces, an arbitrary number of inverter circuits can be used up to 2 ⁿ -1 pieces, and
The total number of terminals can be reduced by 2 ⁿ -1-n compared to the conventional one.

Since the total number of terminals can be further reduced, the package of the standard logic IC 10 can be made even smaller.

Further, also in the chip layout of the standard logic IC 10, the number of output pads is reduced by 2 ⁿ -1-n. As a result, the increase in the chip area due to the increase in the number of output pads can be suppressed, and the chip area can be further reduced. Therefore, the standard logic IC 1 formed on the semiconductor wafer
The theoretical yield of 0 chips can be increased.

In the above-described embodiment, 2 ⁿ -1 (here, 7) inverter circuits 2 to 8 are respectively provided.
⁰ , 2 ^1, ... 2 ^n-1 (here, 1, 2, 4) groups are divided into n groups (here, n = 3) of power suppression terminals, but the present invention has been described. is not limited to this, 2 when ⁿ grouping inverter circuits other than the amino -1, first 2 ⁿ -1 pieces of the inverter circuit 2 ^0,
2 ¹ ... Group into 2 ^n-1 pieces. Thereafter, among the remaining inverter circuits, 2 ^k -1 inverter circuits may be grouped again into 2 ⁰ , 2 ^1, ... 2 ^k -1. However, n> k. Further, if there is a surplus, the same procedure may be used for grouping. In this case also, the same effect as described above can be obtained.

Further, in the above-mentioned embodiment, the case where the present invention is applied to the standard logic IC 10 formed with 2 ⁿ -1 (here, 7) inverter circuits 2 to 8 has been described. The present invention is not limited to this, and can be applied to the case where circuits other than the inverter circuit are simultaneously formed on the chip on which a plurality of inverter circuits are formed.

Further, in the above-mentioned embodiments, the case where the inverter circuits 2 to 8 are formed and the power suppressing terminal for suppressing the power consumption is arranged is described, but the present invention is not limited to this, and other than the inverter circuit. For example, a plurality of circuits having an arbitrary function such as a logic circuit and an operational amplifier may be formed. In addition to the power suppression function, a function arbitrarily determined by the user, such as turning on / off a signal, may be controlled.

[0023]

As described above, according to the present invention, 2 ⁿ -1 of a plurality of functional circuits separately formed on the same chip.
Each functional circuit is grouped into a functional circuit section consisting of 2 ⁰ , 2 ¹ ... 2 ^n-1 functional circuits, and a functional control terminal shared by each functional circuit group is 1 in each functional circuit section. By giving a total of n pieces, 2 ⁿ -1
It is possible to realize an integrated circuit in which an arbitrary number of functional circuits up to the number of terminals can be used and the total number of terminals can be reduced by 2 ⁿ -1-n compared with the conventional one.

[Brief description of drawings]

FIG. 1 is a connection diagram showing a standard logic integrated circuit according to an embodiment of an integrated circuit according to the present invention.

FIG. 2 is a connection diagram showing a conventional standard logic integrated circuit.

[Explanation of symbols]

1,10 ...... standard logical IC, 2 to 8 ...... inverter circuit, 1OA - 1OC ...... logic circuit section, P _2, P _{5,
P 8, P 11, P 14} , P 17, P 20 ...... power suppression pin.

Claims (4)

[Claims] 1. An integrated circuit in which a plurality of functional circuits having the same function are separately formed on a semiconductor chip, wherein 2 ⁿ -1 functional circuits of the plurality of functional circuits are respectively 2 ⁰ , 2 ^1. ...... ^One function control terminal for commonly controlling the above-mentioned functions of all the above-mentioned functional circuits grouped into the functional circuit section is provided to each of the plurality of functional circuit sections divided into 2 ^n-1 groups. An integrated circuit characterized by: 2. The integrated circuit according to claim 1, wherein the functional circuit is a logic circuit. 3. The integrated circuit according to claim 1, wherein the functional circuit is an operational amplifier circuit. 4. The integrated circuit according to claim 1, 2 or 3, wherein the function is control of power consumption of the functional circuit.