JPH07297116A - Exposing method for resist - Google Patents

Abstract

PURPOSE:To suppress fluctuation in the line width of pattern by suppressing the standing wave effect due to the fluctuation in the thickness of resist caused by the level difference at a recess in the underlying layer. CONSTITUTION:A resist is exposed by displacing patterns 25, 27 by a distance proportional to the distance between a chip 26 and the center of a wafer 23 in the direction departing therefrom. Even if the displacement of resist in a recess 13 is small for a chip 26 close to the center of the wafer 23 but it is large for a chip 26 remote therefrom due to the centrifugal force of spin coating, the area of the pattern 25 being exposed at the thick resist part is limited for any chip 26.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a resist exposure method for forming a desired pattern on a chip when manufacturing a semiconductor device.

[0002]

2. Description of the Related Art Due to the demand for multi-functionalization of LSIs, in recent years, it has been possible to mount a memory such as a DRAM on an ASIC.
SI is being integrated into one chip. However, since the capacitor forming the memory cell portion of the DRAM has a larger step than the peripheral circuit portion and the ASIC portion of the DRAM, if the peripheral circuit portion and the ASIC portion and the memory cell portion are formed on the same plane, As the step coverage of the upper layer wiring becomes low, AS
It is difficult to manufacture ICs with high yield.

Therefore, as shown in FIG.
The step 12 is provided on the surface of the
3, a memory cell portion 14 is formed inside the peripheral portion 3, and a peripheral circuit portion 15 and an ASIC portion (not shown) are formed outside the step 12.
The memory cell portion 14 and the peripheral circuit portion 15 and the like are made flat when the capacitor 16 is formed in the memory cell portion 14.

By the way, in order to pattern the insulating film 17 for element isolation, the gate electrode 18, etc. in the recess 13, it is necessary to expose the resist 21 (FIG. 4B). Can cause a phenomenon called standing wave effect. That is, as shown in FIG. 4B, when the resist 21 is applied on the patterning target film 22 and the resist 21 is exposed to the light 23, the light 23 is reflected on the surface of the patterning target film 22 or the like, thereby causing interference. Occurs.

As a result, the line width of the resist 21 after development periodically varies with respect to the film thickness of the resist 21, and as shown in FIG. 4A, the line width of the patterned film 22 to be patterned. Also varies periodically with respect to the film thickness of the resist 21. As the film thickness of the resist 21, normally, as shown in FIG. 4A, the patterned film 22 to be patterned is formed against the fluctuation of the film thickness of the resist 21.
A film thickness A with a small variation in the line width of is selected.

As shown in FIG. 5A, when the width S of the recess 13 formed on the wafer 23 is very wide, the cross-sectional shape of the resist 21 follows the cross-sectional shape of the recess 13, so that the recess 13 is formed. In the inside and near the step 12, the resist 21 has a thicker film thickness B than the outside of the recess 13 and the center of the recess 13. Therefore, in this case, the step 12 of the recess 13
The standing wave effect occurs in the region of width a '.

That is, when the insulating film 17 for element isolation, the gate electrode 18, etc. are patterned in the recess 13, the step 1
Due to the standing wave effect caused by 2, the line widths of the insulating film 17, the gate electrode 18, and the like greatly vary near the step 12. In FIG. 5, the patterning target film 22 on the wafer 23 is not shown in order to make the drawing easy to see.
In the following description, the difference between the film thickness A and the film thickness B is the light 23.
It is assumed that it is a half cycle of the wavelength of.

On the other hand, as shown in FIG. 6, when the resist 21 is applied to the wafer 23, the spin coating for applying the resist 21 while rotating the wafer 23 is generally performed. A centrifugal force 24 acts on 21. Therefore, as shown in FIG. 5B, the resist 21 flows to the outer peripheral side of the wafer 23, and the width of the region of the recess 13 where the standing wave effect occurs is wider than a ′ on the central side of the wafer 23. It becomes a and becomes b which is narrower than a'on the outer peripheral side,
Directionality occurs in the standing wave effect.

Therefore, as shown in FIG. 7, due to the relationship between the distance from the step 12 and the line width of the patterned film 22 to be patterned, the direction 1 from the center of the wafer 23 to the outer circumference and the direction from the outer circumference to the center of the wafer 23. A difference in width c occurs between the direction 2 and the direction 2.

The variation in the line width of the film-to-be-patterned 22 due to lithography is caused by the performance of the device or the like ± f.
And ± g due to the standing wave effect as described above, the overall variation of the line width is f + g. Therefore,
Since f is automatically determined according to the performance of the device and the like when the allowable overall variation in line width is determined, g due to the standing wave effect is inevitably determined as an acceptable value.

As a result, as shown in FIG. 8, in order to keep the standing wave effect within ± g, the patterns formed in the recess 13 are formed from the step 12 on the central side and the outer peripheral side of the wafer 23, respectively. It is necessary to separate them by a distance of d, e or more. Then, conventionally, as shown in FIG. 9, in order to keep the line width in the pattern 25 formed in the recess 13 within a desired variation at any position of the wafer 23, the pattern 2
5 was separated from the step 12 by the maximum distance d.

FIG. 10 shows a standing wave effect produced when the step 12 of the semiconductor device shown in FIG. 3 is 0.3 μm and the insulating film 17 for element isolation is patterned to have a line width of 0.6 μm. The actual measurement data is shown. FIGS. 10A and 10B respectively show the case where the antireflection film is not provided on the insulating film 17 and the case where the antireflection film is provided. The line width variation is smaller when the antireflection film is provided. , The standing wave effect itself and its period are the same.

If it is necessary to suppress the line width variation due to the standing wave effect to 0.03 μm, even if an antireflection film is used, at least from FIG. It is necessary to perform patterning separately from the step 12 by 12 μm in the direction 1 and 8 μm in the direction 2 shown in FIG. Therefore, in the conventional example shown in FIG. 9, the pattern 25 is separated from the step 12 by 12 μm.

[0014]

However, if the pattern 25 formed in the recess 13 is separated from the step 12 by the maximum distance d at any position of the wafer 23 as in the conventional example shown in FIG. Although the line width variation due to the standing wave effect can be kept within a desired value, the interval between the patterns becomes wide and a highly integrated semiconductor device cannot be manufactured.

[0015]

According to a first aspect of the present invention, there is provided a resist exposure method, wherein at least the resist 21 applied to a wafer 23 including a chip 26 having a recess 13 in a base 11 is coated with a resist 21.
In the method of exposing a resist in which the pattern 25 included in the concave portion 13 is exposed, the pattern 25 is set to the center of the base 11 by a distance proportional to the distance from the center of the wafer 23 to the chip 26. The exposure is performed by displacing in the opposite direction.

The resist exposure method according to claim 2 is the same as the resist exposure method according to claim 1, wherein the distance between the step 12 of the recess 13 and the pattern 25 is the wafer 2
The average value (d + e) / 2 of the maximum distance d and the minimum distance e within which the standing wave effect is within the allowable range in the direction of connecting the center of 3 and the chip 26 is used.

The resist exposing method according to claim 3 is the resist exposing method according to claim 1 or 2, wherein the pattern 25 is a pattern of an element having a convex portion.

[0018]

According to the resist exposure method of claim 1, the base 11
The amount of displacement (α, β) between the concave portion 13 and the pattern 25 included in the concave portion 13 is small for the chip 26 close to the center of the wafer 23, and is far from the center of the wafer 23.
Then big.

As a result, the amount of displacement of the resist 21 in the recess 13 is closer to the center of the wafer 23 due to the centrifugal force generated by spin coating, as compared with the case where there is no centrifugal force.
6 is small and the chip 26 far from the center of the wafer 23 is large, the area of the pattern 25 exposed in the thick portion of the resist 21 is small in any chip 26. Therefore, the standing wave effect due to the variation in the film thickness of the resist 21 due to the step 12 of the recess 13 can be suppressed.

In the resist exposure method according to the second aspect, the distance d between the step 12 of the recess 13 of the underlayer 11 and the pattern 25 included in the recess 13 is the maximum distance d within which the standing wave effect is within the allowable range. In comparison with the case where any of the chips 26 is adopted, the above-mentioned interval and thus the pattern 25,
The spacing between 27 may be small.

In the resist exposure method of the third aspect, since the element having the convex portion is formed in the concave portion 13 of the base 11, the entire chip 26 is flat even if the element having the convex portion is formed. .

[0022]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment of the present invention applied to exposure of a resist when manufacturing an ASIC having a memory will be described below with reference to FIGS. In this embodiment,
As shown in FIG. 1A, the wafer 23 is divided into a plurality of chips 26.
Then, ASICs are manufactured on these chips 26.

By the way, since there is a relation of a '= (a + b) / 2 between FIGS. 5 (a) and 5 (b), the resist 2
8 shows the standing wave effect when the centrifugal force 24 does not act on 1.
The distance to separate the pattern 25 formed in the recess 13 from the step 12 in order to keep the distance within ± g of (d +
e) / 2. Therefore, the distances d and e shown in FIG.
Compared to the case where the centrifugal force 24 does not act on the resist 21,
Both are shifted by (d−e) / 2.

On the other hand, the centrifugal force 24 shown in FIGS. 5 and 6 is balanced with the resistance force and surface tension due to the viscosity of the resist 21,
Generally, when the mass is m, the distance from the center of circular motion is r, and the angular velocity is ω, the centrifugal force is expressed as mrω ² . For this reason, the distances d and e shown in FIG. 8 are deviated from the wafer 23 by an amount different from that in the case where the centrifugal force 24 does not act on the resist 21.
It is expected to be proportional to the distance r from the center of.

Therefore, the center of the wafer 23 is the origin (0,
0), the position of the chip 26 at an arbitrary point P is (x,
y), the radius of the wafer 23 is R, and P is the outermost circumference of the wafer 23.
X direction and y in the chip 26 on the same radius as the point
If the values of (d−e) / 2 in the direction are α ₀ and β ₀ , respectively,
When the distances d and e shown in FIG.
1 in the x direction and y as compared to the case where the centrifugal force 24 does not act on 1.
As shown in FIG. 1 (b), the amounts of deviations α and β in the directions are α = α ₀ x / R and β = β ₀ y / R, respectively.

Therefore, in the present embodiment, first, the chip 26
Pattern 2 of the memory cell portion 14 formed in the concave portion 13 of
5 as the distance to be separated from the step 12 (d + e)
/ 2 is set, and as shown in FIG. 1C, the pattern 27 and the pattern 25 including the peripheral circuit section 15 and the ASIC section are set.
Is exposed with the chip 26 displaced in the x direction and the y direction by α and β, respectively.

FIG. 2 shows a sequence of step-and-repeat exposing all the chips 26 on the wafer 23 using the reduction projection exposure apparatus. As shown in FIG. 2, the exposure is performed by moving the stage to the exposure position obtained by adding the displacement amount to the alignment position according to the coordinates of the chip 26 to be exposed.

When the above embodiment is applied to the data shown in FIG. 10, the pattern 2 in the conventional example shown in FIG.
Although 5 is separated from the step 12 by 12 μm, only 10 μm is required in this embodiment. Therefore, the maximum amount of displacement that should be added to the alignment position during exposure is 2 μm.

[0029]

According to the resist exposure method of the first aspect, since the standing wave effect due to the variation of the resist film thickness due to the step of the depression of the base can be suppressed, the variation of the line width of the pattern is small. Semiconductor devices can be manufactured with high yield.

In the resist exposure method according to the second aspect of the present invention, the gap between the step of the underlying recess and the pattern included in the recess, and hence the interval between the patterns, may be small, so that a highly integrated semiconductor device can be manufactured. You can

In the resist exposure method according to the third aspect, since the entire chip is flat even when the element having the convex portion is formed, the step coverage of the upper layer wiring is high, and the semiconductor device can be manufactured with a high yield. You can

[Brief description of drawings]

1A and 1B show an embodiment of the present invention, in which FIG. 1A is a plan view of a wafer, FIG. 1B is a diagram for explaining a displacement amount of an exposure pattern, and FIG. 1C is a chip and an exposure pattern. It is a plan view showing the positional relationship of.

FIG. 2 is a flowchart showing an exposure sequence of one embodiment.

FIG. 3 is a side sectional view of a semiconductor device to which the invention of the present application can be applied.

4A and 4B show a standing wave effect, where FIG. 4A is a graph showing the relationship between resist film thickness and line width, and FIG. 4B is a side sectional view for explaining the principle of the standing wave effect. is there.

FIG. 5 is a side cross-sectional view showing the relationship between the step and the shape of the resist, FIG. 5A shows the case where the resist is not spin-coated.
(B) shows the case where the resist is spin-coated.

FIG. 6 is a plan view showing spin coating of a resist.

FIG. 7 is a graph showing the directionality of a standing wave effect.

FIG. 8 is a graph showing a method for making the standing wave effect within an allowable range.

FIG. 9 is a plan view showing a conventional example of the invention of the present application.

FIG. 10 shows a variation in line width due to a standing wave effect, and (a) is a graph when an antireflection film is not used,
(B) is a graph when an antireflection film is used, and (c) is a plan view showing the directionality of the standing wave effect.

[Explanation of symbols]

 11 semiconductor substrate 12 step 13 recess 21 resist 23 wafer 25 pattern 26 chip

Claims (3)

[Claims] 1. A method of exposing a resist, which is applied to a wafer including a chip having a concave portion as a base, in at least a pattern included in the concave portion, the method being proportional to a distance from a center of the wafer to the chip. The resist exposure method, wherein the exposure is performed by displacing the pattern with respect to the base in a direction opposite to the center by a distance of 2. An average value of a maximum distance and a minimum distance in which a standing wave effect is within an allowable range in a direction connecting a center of the wafer and the chip, as an interval between the step of the recess and the pattern. The method of exposing a resist according to claim 1, wherein: 3. The method of exposing a resist according to claim 1, wherein the pattern is a pattern of an element having a convex portion.