JPH07296585A - Multi-port memory - Google Patents

Abstract

PURPOSE:To reduce power consumption in a write port by activating a memory cell selecting sub-word line even when both of a write enable signal and a chip enable signal are effective. CONSTITUTION:A sub-word line control means consisting of NOR gates 320-1 to m, 330-1 to m and a read/write control circuit 190 are provided in a memory array of two port memory. Two input NOR gate 193 in the circuit 190 outputs a high level signal when both of a chip selection signal CSN and the write enable signal WEN are a low level, and a write mode signal WMODE is outputted from a driver 196. The WMODE is supplied to the gates 320-1 to m, 330-1 to m through inverters 340, 350, and writing sub-word lines 325-1, 335-1 are activated, and memory cell group 301-1 to m, 302-1 to m are selected. Thus, a memory cell current at a writing time flows only in a write period, and current consumption is reduced.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor memory device,
In particular, it relates to a technique for reducing power consumption of a multi-port memory.

2. Description of the Related Art FIG. 5 is a block diagram of a 2-port memory. When writing data, an address signal is applied to the writing word line XW to write the writing data Din into a predetermined memory cell in the memory, and when reading data, an address signal is sent to the reading word line XR. Is applied to output read data Do from the memory cell.

FIG. 6 is a circuit diagram of the above-mentioned two-port memory. Reference numerals 501 to 50n and the like are 1-bit memory cells, which are 2-port memory cells each having one read port and one write port. Since each 2-port memory cell operates in the same manner, the memory cell 5 will be described below.
The operation No. 01 will be described as an example. The memory cell 501 has two inverters 5 whose inputs are connected to the outputs of the other.
It includes a flip-flop composed of 31, 532 and stores 1-bit data.

At the time of writing data, a write amplifier 526
Generates write data by the write data Din and the internal write pulse WEP, and uses this to write common data line 52.
Output to 5. 521 and 522 are write data lines Wd,
A load MOS transistor provided between Wdn and the power supply Vcc. The write data output to the write common data line 525 is output to the write data lines wd and wdn by the column selection switches 523 and 524 controlled by the column selection signal YW1. The inverter 53 via the write access transistors 551 and 552 controlled by the address signal from the source line XW1.
Write data D to a flip-flop composed of 1,532
written in.

When reading data, the read word line X is used.
The signal of the flip-flop is read through the read access transistors 541 and 542 controlled by the address signal applied to R1 and read data lines rd and rdn.
And further outputs this signal to the read common data line 515 through the column selection switches 513 and 514 controlled by the column selection signal YR1. Sense amplifier 51
Reference numeral 6 amplifies the minute signal on the read common data line 515 and outputs a logic level signal Do.

In the conventional two-port memory described above, when it is accessible from the outside, that is, when both the read address decoder and the write address decoder are operating, the write word line is used. XW1-XWm and XR1
Each of XRm to XRm is in the selected state. X
When W1 is in the selected state, the cell current Im is equal to the power supply Vcc.
Flows from the memory cell 501 to the memory cell 501 via the load MOS 521 and the access transistor 551. Same word line XW1
A similar cell current Im also flows through the other memory cells 502 and the like connected to.

FIG. 7 shows an operation time chart of the 2-port memory. CSN is a chip selection signal and selects a chip at a low level. Ai is an address signal. W
EN is a write enable signal, which is in a write operation mode at a low level. WWL is a word line signal for a write port, and a memory cell is selected at a high level. WEP
Is an internal write pulse made from WEN which, when high, writes the write data Din to the selected memory cell. Further, ΣIm is the total sum of the memory cell currents of the write port.

[0007]

FIG. 8 shows the memory cell current .SIGMA. Of the write port corresponding to the chip select signal CSN.
It is a state diagram of Im. This memory cell current is originally C
It flows only during the write cycle period when SN is at the low level "0", and is unnecessary in other periods. However, in the conventional two-port memory, as shown in FIG. 8, the memory cell current and the unnecessary current flow in the read cycle and the idle cycle other than the write cycle, unnecessarily increasing the power consumption. It was It is an object of the present invention to provide a multi-port memory with reduced unnecessary power consumption.

[0008]

In order to solve the above-mentioned problems, a read port, a write port, a memory cell array in which a plurality of memory cells are arranged in an array, and a read / write control circuit are provided. In a multi-port memory, a sub port for selecting a memory cell of a write port only when both a write enable signal and a chip enable signal are valid.
Sub-word line control means for activating the line is provided. Further, the subword line control means is provided for each predetermined number of memory cell groups. Further, the read / write control circuit uses the write enable signal and the chip enable signal to determine the decoder control signals for the write port and the read port, the internal write pulse signal, and the subword. The control signal of the line control means is generated.

[0009]

The sub-word for selecting the memory array according to the present invention described above.
The drain line control means acts so that the current flows only in the selected memory cell only during the write cycle period and does not flow during the read cycle or idle cycle period. Further, since the control signal of the subword line acts on the subword line control means, it does not affect the operation delay of the row address decoder.

[0010]

1 is a block diagram of a two-port memory according to the present invention. In the memory array 101, a plurality of memory cells are arranged in an array. The write port row decoder 110 selects the write row address of the memory array 101 in response to the input of the row address WXA. Similarly,
The write port column decoder 120 has a column address WYA.
The column selection switch 130 is controlled in response to the input of to select the write column address of the memory array 101. The write amplifier 140 writes the write data Din in the selected memory cell. WEP is an internal write pulse.

The row decoder 150 of the read port selects the read row address of the memory array 101 according to the input of the row address RXA. Similarly, the read port column decoder 160 controls the column selection switch 170 in response to the input of the column address RYA to select the read column address of the memory array 101. The sense amplifier 180 amplifies the signal read from the memory array 101 and outputs a logic level signal Do.

In the present invention, the subword line control means is provided in the memory array 101 of the above-mentioned two-port memory 100, and the decoder control signals C1 and C1 are supplied in response to the chip selection signal CSN and the write enable signal WEN. C2, internal write pulse WEP, and write mode signal WMOD
A read / write control circuit that outputs E is provided. This W
The MODE signal is a signal newly provided to reduce the power consumption of the write port. FIG. 2 is a circuit diagram of an embodiment of the read / write control circuit 190. The inverter 191 is a decoder control signal C1 obtained by inverting the chip selection signal CSN.
And the row decoder 110 of the write port is operated only when the chip select signal CSN is at a low level.

The inverter 192 is a chip selection signal CSN.
And outputs the internal control signal C2, which is the inverse of the above, and only when the chip select signal CSN is at a low level, the row decode of the read port is performed.
The da 150 is operated. The 2-input NOR gate 193 is
When both the chip select signal CSN and the write enable signal WEN are low level, a high level signal is output, and the driver 196 outputs this signal as a write mode signal WMODE. The delay circuit 194 is a 2-input NOR gate.
The output of the gate 193 is delayed by a predetermined time corresponding to the delay time from the address input in the decoding system to the completion of selection of the memory array. The AND gate 195 is a delay circuit 194.
The internal write pulse WEP is generated by the logical sum of the output of the above and the output of the 2-input NOR gate 193.

FIG. 3 shows an embodiment of the row address selection unit of the 2-port memory according to the present invention. 301-1 and 301-2
~ 301-m and 302-1, 302-2 to 302-
n is a 2-port memory cell. The write port row decoder 310 outputs the decode signal of the write address WXA to the write main word line 315. The row decoder 360 of the read port outputs the decode signal of the read address RXA to the read main word line 365.

The signal on the read main word line 365 is inverted in polarity by the inverter 370 and sent to the read subword line 375, and the memory cell groups 301-1 to 301-1.
The selection signal is 301-m. Similarly, the polarity of the signal on the read main word line 365 is inverted by the inverter 380 and sent to the read subword line 385 to select the memory cell groups 302-1, 302-2 to 302-m. Become a signal. Note that the row decoders 310 and 360 generally have a multi-stage configuration when the number of inputs increases in proportion to the memory capacity.

NOR gate (subword line control means) 3
The main word line 315 for direct writing is connected to one input of 20-1 and the inverted signal of the write mode signal WMODE is connected to the other input via the inverter 340, and its output is written. Sent to the subword line 325-1 for memory cell groups 301-1 and 301-2 to 301-m.
Etc. are selected. Similarly, the main gate for writing is connected to one input of the NOR gate (sub-word control means) 330-1.
It is directly connected to the write line 315, and the other input is connected to the inverted signal of the write mode signal WMODE via the inverter 350, and its output is the write subword line 335-.
1 to the memory cell groups 302-1, 302-2 to 30
Select 2-n.

Other NOR gates 320-m, 330-m
And so on. That is, the main word line of the other row is connected to one of the inputs, and the WM is connected to the other input.
The inverted signal of the ODE signal is connected, and the memory cell groups of the other rows are connected to the respective outputs.

FIG. 4 is an operation time chart of the 2-port memory according to the present invention. A high level of the chip selection signal CSN gives a non-selection state, and a low level thereof gives a selected state. Ai
Is an address signal. Write enable signal WEN
Becomes the write operation mode at a low level. The VMODE signal is the output of driver 196 of FIG. 2 and is in write mode at high level. Sub-word line signal W of write port
WL selects a memory cell at a high level and deselects it at a low level. Similar to FIG. 2, the internal write pulse signal WEP is made up of the chip enable signal and the write enable signal WEN, and when it is at a high level, the write data Din is written in the selected memory cell.

In the conventional device shown in FIG. 7, the sum ΣIm of the memory cell currents of the write port continues to flow while the subword line signal WWL is at a high level. On the other hand, in the present invention, the subword line signal WWL is kept at a low level except in the write cycle, so that ΣIm flows only during the period when the subword line signal WWL is at a high level. That is, in the lead cycle and idle cycle, the above Σ
Since Im does not flow, the period during which the sum ΣIm of the memory cell currents of the write port flows is greatly shortened, and power consumption can be reduced.

The ratio of the current flowing through the memory cell during the write cycle period TW is t2 / TW when the time width of the write mode signal WMODE is t2. As another method of making the memory cell current of the write port zero except the time t2, the write mode signal W is input to the input of the decoder 310 of FIG.
Add the inverted signal of MODE to add the decoder to WMODE
A method of operating only during the period is considered. However, with this method, the WM
Decoder 310 until the ODE signal goes high.
Does not work, so there is a problem in that the write cycle must be lengthened accordingly. On the other hand, in the present invention, since the write mode signal is input to the subword control means, the operation of the decoder is not affected and the write cycle time does not become long.

Further, in FIG. 3, the inverters 340 and 3 are provided.
50 is replaced with a 2-input gate, a WMODE signal is applied to one input of each 2-input gate, and memory cell groups 301-1 and 301-2 to 301-m and a memory cell group are applied to the other input. By applying a group selection signal for collectively controlling selection of the cells 302-1, 302-2 to 302-n, it is possible to control activation and deactivation of the subword line for each memory cell group. The power consumption can be further reduced. Further, in the embodiment of the present invention described above, the case where the number of write ports is one has been described, but the present invention can be similarly applied to the case where there are a plurality of write ports, and the consumption is proportional to the number of ports. The power can be further reduced.

[0022]

According to the present invention, it is possible to provide a two-port memory in which the power consumption of the write port is reduced by causing the memory cell current at the write time to flow only during the write period.

[Brief description of drawings]

FIG. 1 is a circuit diagram of a two-port memory embodiment according to the present invention.

FIG. 2 is a read / write control circuit according to the present invention provided in the two-port memory circuit of FIG.

3 is a circuit diagram of an embodiment of a row address selection unit in the 2-port memory of FIG.

FIG. 4 is an operation time chart of the two-port memory shown in FIG.

FIG. 5 is a block diagram of a conventional 2-port memory.

FIG. 6 is a circuit diagram of a conventional 2-port memory.

FIG. 7 is an operation time chart of the 2-port memory shown in FIG.

FIG. 8 is an operation state diagram of a conventional two-port memory.

[Explanation of symbols]

101 ... Mori array, 110, 150 ... Row decoder, 1
20, 160 ... Column decoders, 130, 170 ... Column selection switches, 140, 526 ... Write amplifiers, 180, 51
6 ... Sense amplifier, 190 ... Read / write control circuit,
191, 192 ... Inverter, 193 ... NOR gate,
194 ... Delay circuit, 195 ... AND gate, 196 ... Driver circuit, 301-1 to 301-m ... Memory cell, 3
02-1 to 301-n ... Memory cells, 501 to 50n ...
Memory cells 515 ... Common data line for reading 525 ...
Common data line for writing.

 ─────────────────────────────────────────────────── ─── Continuation of the front page (72) Inventor Kei Kato 5-20-1 Kamimizumoto-cho, Kodaira-shi, Tokyo Inside the Semiconductor Division, Hitachi, Ltd. (72) Hiroaki Ogawa 3-chome, Saiwaicho, Hitachi, Ibaraki 2-1 Hitachi Engineering Co., Ltd.

Claims (3)

[Claims] 1. A multi-port memory comprising a read port, a write port, a memory cell array in which a plurality of memory cells are arranged in an array, and a read / write control circuit. A multiport memory comprising subword control means for activating a memory cell selecting subword line of a write port when both of the chip enable signals are valid. 2. The multiport memory according to claim 1, wherein the subword control means is provided for each of a predetermined number of memory cell groups. 3. The read / write control circuit according to claim 1, wherein the read / write control circuit comprises decoder control signals for a write port and a read port, based on a write enable signal and a chip enable signal. A multiport memory, wherein an internal write pulse signal and a control signal of the memory array selecting subword line control means are generated.