JP3309908B2 - Semiconductor storage device - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to a semiconductor memory device, and more particularly to a static random access memory.

[0002]

2. Description of the Related Art Referring to FIG. 7, a semiconductor memory device according to the prior art 1 includes a plurality of memory cells 104 (1, 1),.
.. 104 (1, N),..., 104 (M, 1),
.., 104 (M, N), each of which includes a plurality of memory cells 104 (1, j) to 104 (M, j) (1 ≦ j ≦ N)
(N is a natural number) bit line pairs 105 connected to
(1) to 105 (N), M (M is a natural number) words each connected to a plurality of memory cells 104 (i, 1) to 104 (i, N) (1 ≦ i ≦ M) in each row Line 106 (1)
To 106 (M), arbitrarily selected memory cell 104
A sense amplifier 102 that reads a logical value stored in (i, j), and an arbitrarily selected memory cell 104 (i, j).
j) that writes a logical value to the bit line pair 105 (j) arbitrarily selected from the N bit line pairs 105 (1) to 105 (N). It includes column selection circuits 501 (1) to 501 (N) connected to the write driver 103. The column selection circuit 501 (j) has one bit line pair 105 (j).
And two PMOS transistors MP
(J), MPB (j) and two NMOS transistors MN (j), MNB (j). The PMOS transistor MP (j) is a selection transistor for reading, and the NMOS transistors MN (j) and MNB (j)
Is a select transistor for writing. The drain terminal of the PMOS transistor MP (j) and the drain terminal of the NMOS transistor MN (j) are connected to the bit line 105a.
(J) and the PMOS transistor MPB (j)
And the drain terminal of the NMOS transistor MNB (j) are connected to the bit line 105b (j).
The gate terminals of the PMOS transistors MP (j) and MPB (j) are connected to a read column select line 502 (j), and the gate terminals of the NMOS transistors MN (j) and MNB (j) are connected to a write column select line. 503 (j). PMOS transistors MP (j), MPB
The source terminal (j) is connected to the input terminal of the sense amplifier 102 by the read bit common bit line pair 504a, 504b.
, And an NMOS transistor MN (j),
The source terminal of MNB (j) is connected to the output terminal of the write driver 103 via the write common bit line pair 505a, 505b.

Next, an arbitrarily selected memory cell 104
The operation when data is read from (i, j) will be described.

By activating the word line 106 (i) (1 ≦ i ≦ M), all the bit line pairs 105 (1) to 105 (1) to
At 105 (N), memory cells 104 (i, 1) to 104
The data in (i, N) is output. at the same time,
Read column select lines 502 (1) to 502 which were at the High potential in the non-selection state before the read operation
In (M), the read column select line 502 (j) is set to L
By setting the potential to the ow potential, the PMOS transistors MP (j) and MPB (j) in the column selection circuit 501 (j) are turned on, whereby the bit line pair 105a is set.
(J), 105b (j) and the sense amplifier 102 are electrically connected via a read common bit line pair 504a, 504b. After a certain time, the column selection line 502 (j)
At the High potential, the bit line pair 105a
(J) and 105b (j) are separated from the sense amplifier 102, and then the sense amplifier 102 is activated and the word line 106 (i) is deactivated at the same time. The sense amplifier 102 includes a read common bit line pair 504a, 50
It amplifies the potential difference maintained by the floating capacitance between 4b and outputs the amplification result.

Next, an arbitrarily selected memory cell 104
The operation for writing data to (i, j) will be described.

In a non-selected state before a write operation, Lo
The write column selection line 503 (1)-
Of the 503 (N), the write column selection line 503
(J) is High potential. As a result, the NMOS transistors MN (j) and MNB (j) become conductive, and the bit line pair 105a (j) and 105b (j) and the write driver 103 connect the write common bit line pair 505a and 50b.
5b are electrically connected. At the same time, the write driver 103 is activated, and the bit line pair 105a (j),
One of the lines 105b (j) is set to a low potential. At this time, the data is written into the memory cell (i, j) by activating the word line 106 (i).

Referring to FIG. 8, the semiconductor memory device according to Conventional Example 2 differs from the semiconductor memory device according to Conventional Example 1 in the configuration of write column select lines 503 (1) to 503.
(N) is replaced with the write line 607, and a NOR gate 606 (j) for calculating the NOR of the read column select line 502 (j) and the write line 607 is added to the column select circuit 601 (j). Then, the NOR gate 606 (j)
Of the NMOS transistors MN (j) and MNB
This is the point connected to the gate terminal of (j). Column selection circuit 6
At 01, the NOR gate of the read column select line 502 (j) and the write line 607 is taken by the NOR gate 606 (j), and the output line of the NOR gate 606 (j) is set to the write column select line 608 (j). ).

The semiconductor memory device according to Conventional Example 2 is different in operation from the semiconductor memory device according to Conventional Example 1 in that a write line 607 is set to a High potential at the time of a read operation, and an arbitrarily selected memory cell (i, The point is that the write line 607 is set to the low potential and the read column select line 502 (j) is set to the low potential during the operation of writing data to j). In addition, arbitrarily selected memory cells (i,
j), the PMOS transistor M
Although P (j) and MPB (j) also conduct at the same time, the conduction does not affect the write operation because the sense amplifier 102 is not activated.

[0009]

The problem of the conventional semiconductor memory device is that the hardware scale of the column selection circuit for selecting the bit line and the column selection line increases.

In the conventional example 1 shown in FIG. 7, in order to select any one bit line pair 105 (j) from the bit line pairs 105 (1) to 105 (N) during the read operation, N
The read column selection lines 502 (1) to 502 (N) are required, and the bit line pair 105 (1) is used during a write operation.
１０５105 (N), any one bit line pair 105
In order to select (j), N write column select lines 503 (1) to 503 (N) are required.
N selection lines are required.

In the conventional example 2 shown in FIG. 8, the number of transistors per bit line pair is four transistors constituting the NOR gate 606 (j) and the PMOS transistor MP
(J), two MPB (j), PMOS transistors MN
(J) and two MNB (j), for a total of eight, for a total of 8N for all columns.

An object of the present invention is to provide a semiconductor memory device in which both the read operation and the write operation are speeded up and the hardware scale for column selection is reduced.

[0013]

According to the present invention, there is provided a semiconductor memory device comprising: a plurality of memory cells arranged in a matrix; a plurality of word lines each connected to a plurality of memories in each row;
A plurality of column bit line pairs each connected to a plurality of memories in each column; a write driver for writing data to any of the plurality of memory cells; and reading data from any of the plurality of memory cells Amplifier, a write common bit line pair connected to the write driver, a read common bit line pair connected to the sense amplifier, a column bit line pair of each column, and the write common bit line pair. A plurality of column selection circuits connected to the bit line pair and the read common bit line pair; and a plurality of column selection lines each connected to the column selection circuit of each column. Is a first first conductivity type transistor;
A second first-conductivity-type transistor, a first second-conductivity-type transistor, and a second second-conductivity-type transistor; and a drain of the first first-conductivity-type transistor;
The drain of the first second conductivity type transistor is connected to one line of a column bit line pair of a corresponding column,
The drain of the first conductivity type transistor and the drain of the second second conductivity type transistor are connected to the other line of the pair of column bit lines of the corresponding column, and the drain of the first first conductivity type transistor A source, a gate of the first second conductivity type transistor, a source of the second first conductivity type transistor, and a gate of the second second conductivity type transistor are connected to a column selection line of the corresponding column. And the gate of the first first conductivity type transistor is connected to one of the write common bit line pairs, and the gate of the second first conductivity type transistor is connected to the write common bit line. The source of the first second conductivity type transistor is connected to the other line of the line pair, the source of the first second conductivity type transistor is connected to one line of the read common bit line pair, and the source of the second second conductivity type transistor is connected. Characterized in that it is connected to the other line of the common bit line pair for the read.

Further, in the semiconductor memory device according to the present invention, in the semiconductor memory device described above, a word line corresponding to an input row address value among the plurality of word lines and an input signal among the plurality of column selection lines are provided. A first activating means for simultaneously activating a column selection line corresponding to a value of a column address is further provided.

Further, the semiconductor memory device according to the present invention, in the above-mentioned semiconductor memory device, further comprises a first deactivating means for deactivating a column selection line activated by the first activating means. It is characterized by the following.

Further, in the semiconductor memory device according to the present invention, the semiconductor memory device further includes a second activating means for activating the sense amplifier after the deactivating means deactivates a column selection line. It is characterized by having.

Further, in the semiconductor memory device according to the present invention, in the semiconductor memory device described above, the word line is deactivated when or after the column selection line is deactivated by the first deactivating means. And a second deactivating means.

Further, in the semiconductor memory device according to the present invention, in the semiconductor memory device described above, a word line corresponding to an input row address value among the plurality of word lines and an input signal among the plurality of column selection lines are input. A column select line corresponding to a column address value is simultaneously activated, and a line corresponding to a specified logical value of the write common bit line pair is set to a first logical value level. It is characterized by further comprising means.

Further, in the semiconductor memory device according to the present invention, in the semiconductor memory device described above, the line on the side corresponding to the designated logical value of the write common bit line pair by the writing means is the first line. When the logical value level is set, a write assisting means for setting a line of the write common bit line pair that is not the side corresponding to the specified logical value to a second logical value level is further provided. Features.

Further, in the semiconductor memory device according to the present invention, in the semiconductor memory device described above, the plurality of memory cells, the plurality of word lines, the plurality of column bit line pairs, the write driver, and the sense A plurality of sets each including an amplifier, the pair of write common bit lines, the pair of read common bit lines, the plurality of column selection circuits, and the plurality of column selection lines are provided.

[0021]

Next, embodiments of the present invention will be described with reference to the drawings.

Referring to FIG. 1, a first embodiment of the semiconductor memory device includes a plurality of memory cells 104 (1, 1),.
104 (1, N),..., 104 (M, 1),.
, 104 (M, N), each of which is connected to a plurality of memory cells 104 (1, j) to 104 (M, j) (1 ≦ j ≦ N) in each column (N is a natural number) Bit line pair 105
(1) to 105 (N), M (M is a natural number) words each connected to a plurality of memory cells 104 (i, 1) to 104 (i, N) (1 ≦ i ≦ M) in each row Line 106 (1)
To 106 (M), arbitrarily selected memory cell 104
A sense amplifier 102 that reads a logical value stored in (i, j), and an arbitrarily selected memory cell 104 (i, j).
j) that writes a logical value to the bit line pair 105 (j) arbitrarily selected from the N bit line pairs 105 (1) to 105 (N). A column selection circuit 101 (1) to 101 (N) connected to the write driver 103, a row decoder 200 for decoding the input encoded row address 201 and activating the word line 106 (j) corresponding to the decoding result; A column decoder 301, a sense amplifier 102, a write driver 103, and a row decoder 20 for decoding an input encoded column address 301 and activating a column selection line 107 (j) corresponding to the decoding result.
0, the timing of the column decoder 300 is
02, 403, and 404. One column selection circuit 101 (j) is provided for one bit line pair 105 (j), and the PMOS transistors MP (j), MPB (j), and the NMOS transistor MN
(J), MNB (j). The PMOS transistors MP (j) and MPB (j) are selection transistors for reading, and the NMOS transistors MN (j) and MN
B (j) is a select transistor for writing. P
Drain terminal of MOS transistor MP (j) and NMO
The drain terminal of S transistor MN (j) is bit line 1
05a (j) and the PMOS transistor MPB
(J) Drain terminal and NMOS transistor MNB
The drain terminal of (j) is connected to the bit line 105b (j). PMOS transistors MP (j), MPB
(J) Gate terminal and NMOS transistor MN
(J), the source terminal of MNB (j)
(J). PMOS transistor MP (j),
The source terminal of MPB (j) is connected to the input terminal of the sense amplifier 102 via the read common bit line pair 108a, 108b. NMOS transistor MN
(J), the gate terminal of MNB (j) is connected to the output terminal of the write driver 103 via the write common bit line pair 109a, 109b.

Referring to FIG. 2, a second embodiment of the semiconductor memory device is the same as the first embodiment shown in FIG.
One or a plurality thereof are arranged in the column direction, and the array unit 100
Column selection lines 107 (1) to 107 (N) are connected to each other. Word lines 106 (1) to 106 (N)
Are driven by the row decoder 200 and the column selection lines 107
(1) to 107 (N) are driven by the column decoder 205. The control unit 500 controls the timing of each unit similarly to the control unit 400. For example, although each bit of the same address is allocated to each array unit 100, a bit of a different address may be allocated to each array unit, and the control unit 500 controls activation of each array unit.

Referring to FIG. 3, a first embodiment of the sense amplifier 102 is a latch type sense amplifier, which uses a read common bit line pair 108a, 108b as an input / output line and an activation signal line 304. Is activated when the signal has a logical value High.

Referring to FIG. 4, in a second embodiment of the sense amplifier 102, the differential sense amplifier 401 and the write driver outputs 109a and 109b are used as inputs and the inputs 108a and 108b of the sense amplifier 401 are connected to the power supply. It is constituted by PMOS transistors 402 and 403 for controlling conduction, and outputs a valid logical value to the output line 12 when the activation signal line 304 has a logical value of High.

Next, in the first embodiment of the semiconductor memory device, a row address 201 and a column address 301 which take arbitrary values
The operation at the time of reading data from the memory cell 104 (i, j) determined by the above will be described with reference to FIG.

First, at time t1, when the row decoder 200 activates the word line 106 (i) to the High potential, the data written in the memory cells 104 (i, 1) to 104 (i, N) becomes a bit. Line pair 105 (1) to 105
(N). At the same time, in a non-selected state before the column decoder 300 performs a write operation, one column select line 107 of all the column select lines that have been at the High potential.
(J) is activated to a low potential. With this, PMO
The S transistors MP (j) and MPB (j) become conductive, and the selected bit line pair 105 (j) and the sense amplifier 102
Are connected to the read common bit line pair 108a, 1
08b. At time t2 after a certain time, the column decoder 300 sets the column selection line 107 (j) to H
By deactivating to the high potential, the bit line pair 10
After disconnecting 5 (j) from the sense amplifier 102, the control unit 400 activates the activation signal line 304 to a High potential to activate the sense amplifier 102. Further, at time t2, the row decoder 200 sets the word line 106
(I) is deactivated to a low potential. However, word line 1
06 (i) may be deactivated to a Low potential after time t2. The sense amplifier 102 amplifies the potential difference between the read common bit line pair 108a and 108b, and outputs an amplification result.

Next, in Embodiment 1 of the semiconductor memory device, a row address 201 and a column address 301 which take arbitrary values
Referring to FIG. 6, an operation when writing data of a specified logical value to the memory cell 104 (i, j) determined by the above will be described.

First, at time t3, in a non-selection state before the column decoder 300 performs a write operation, one column selection line 107 of all the column selection lines having the High potential has been set.
(J) is activated to a low potential. With this, NMO
The source potentials of the S transistors MN (j) and MNB (j) become Low potential. At the same time, the write driver 103
, One of the write common bit line pairs 109a and 109b, which had a low potential before the write operation, is set to one of the lines 109a or 109b corresponding to the logical value of the write data.
By setting the potential to high, the NMOS transistor M
N (j), one transistor M of MNB (j)
Conduction is performed between the source and the drain of N (j) or MNB (j). Thereby, the NMOS transistor MN (j)
Of the bit line 1
05a (j) changes from the High potential to the Low potential, and the bit line 105b (j) maintains the High potential. On the other hand, when the source-drain of the NMOS transistor MNB (j) conducts, the bit line 105b (j) changes from the high potential to the low potential, and the bit line 105a
(J) maintains the High potential. At time t3, the row decoder 200 further sets the word line 106 (i) to Hig.
Activating the memory cell 104 (i,
Data writing to j) is performed. The writing ends at time t4 after a certain time, and the writing driver 103
The row decoder 200 and the column decoder 300 deactivate the signal line activated at the time t3.

In the write operation, the source and drain of the PMOS transistors MP (j) and MPB (j) connected to the selected bit line pair 105 (j) conduct simultaneously, but the activation signal of the sense amplifier 102 is activated. Line 304
Is not activated, the conduction is made to the bit line 105a.
There is no effect on the operation of pulling (j) or 105b (j) to the low potential.

Conversely, the sense amplifier 10 shown in FIGS.
By using 2, the other bit line 105b (j) or 105a (j) paired with the bit line 105a (j) or 105b (j) pulled down to the Low potential can be fixed at the High potential. Thereby, bit line pair 1
05 (j) has a High potential, and the other has a Low potential.
A potential can be given, so that a writing operation can be performed stably.

That is, in the sense amplifier shown in FIG.
One of the sense amplifier input / output lines 108a and 108b
ow potential, the PMOS transistors 13 and 14
Is connected to the power supply, and the other of the sense amplifier input / output lines 108a and 108b has the High potential. Also, P connected to the selected bit line pair 105 (j)
The source and drain of the MOS transistors MP (j) and MPB (j) are simultaneously conducting. Therefore, the bit line 105a (j) or 105b pulled down to the low potential
The other bit line 105b (j) or 105a (j) paired with (j) is set to High potential.

In the sense amplifier shown in FIG. 4, the logic values of the write common bit lines 109a and 109b are inverted by inverters 404 and 405, and the PMOS transistor 40
2, 403 is input. Therefore, the sense amplifier input line 108a or 108b on the opposite side of the write common bit line 109a or 109b having the High potential is set to H level.
It can be fixed at the high potential. The source and drain of the PMOS transistors MP (j) and MPB (j) connected to the selected bit line pair 105 (j) are simultaneously conducting. Therefore, the other bit line 105b (j) or 105a paired with the bit line 105a (j) or 105b (j) pulled down to the Low potential.
(J) becomes High potential.

The conductivity types of the transistors of the above embodiment may be all inverted. That is, the PMOS transistor may be replaced with an NMOS transistor, and the NMOS transistor may be replaced with a PMOS transistor.

[0035]

As described above, according to the present invention, a column select line for reading and a column select line for writing can be commonly used. By using them in common, the number of column selection lines can be increased from 2N to N as compared with the conventional example 1 shown in FIG.
There is an effect that can be reduced by half to books Further, as compared with the conventional example 2 shown in FIG. 8, there is an effect that the number of transistors per column selection circuit can be reduced by half from eight to four.

[Brief description of the drawings]

FIG. 1 is a circuit diagram showing Embodiment 1 of a semiconductor memory device according to the present invention.

FIG. 2 is a block diagram showing a second embodiment of the semiconductor memory device according to the present invention;

FIG. 3 is a circuit diagram showing a second embodiment of the sense amplifier according to the present invention;

FIG. 4 is a circuit diagram showing a second embodiment of the sense amplifier according to the present invention;

FIG. 5 is a timing chart at the time of a read operation of the first embodiment of the semiconductor memory device according to the present invention;

FIG. 6 is a timing chart at the time of a write operation of the first embodiment of the semiconductor memory device according to the present invention;

FIG. 7 is a circuit diagram showing a semiconductor memory device according to Conventional Example 1.

FIG. 8 is a circuit diagram showing a semiconductor memory device according to Conventional Example 2.

[Explanation of symbols]

MN (1) to MN (N), MNB (1) to MNB (N)
NMOS transistors MP (1) to MP (N), MPB (1) to MPB (N)
PMOS transistor 101 Column selection circuit 102 Sense amplifier 103 Write driver 104 (1, 1) to 104 (M, N) Memory cell 105 (1) to 105 (N) Bit line pair 106 (1) to 106 (M) Word line 107 (1) to 107 (N) Column selection lines 108a, 108b Common bit lines for reading 109a, 109b Common bit lines for writing 200 Row decoder 300 Column decoder 400 Control unit

Claims (8)

(57) [Claims] 1. A plurality of memory cells arranged in a matrix, a plurality of word lines each connected to a plurality of memories in each row, and a plurality of column bits each connected to a plurality of memories in each column. A line pair, a write driver for writing data to any of the plurality of memory cells, a sense amplifier for reading data from any of the plurality of memory cells, and a write common connected to the write driver A bit line pair; a read common bit line pair connected to the sense amplifier; and a plurality of each connected to the column bit line pair of each column, the write common bit line pair, and the read common bit line pair. And a plurality of column selection lines each connected to the column selection circuit of each column. The column selection circuit of each column includes a first first conductivity type transistor, a second A first conductivity type transistor, a first second conductivity type transistor, a second second conductivity type transistor,
A drain of the first first conductivity type transistor and a drain of the first second conductivity type transistor are connected to one line of a column bit line pair of a corresponding column, The drain of the one-conductivity-type transistor and the drain of the second second-conductivity-type transistor are connected to the other line of the column bit line pair of the corresponding column, and the source of the first first-conductivity-type transistor A gate of the first second conductivity type transistor, a source of the second first conductivity type transistor, and a gate of the second second conductivity type transistor are connected to a column selection line of the corresponding column. The gate of the first first conductivity type transistor is connected to one of the write common bit line pairs, and the gate of the second first conductivity type transistor is connected to the write common bit line. The source of the first second conductivity type transistor is connected to one line of the read common bit line pair, and the source of the second second conductivity type transistor is connected to the read line. A semiconductor memory device connected to the other line of the common bit line pair. 2. The semiconductor memory device according to claim 1, wherein a word line corresponding to an input row address value among said plurality of word lines, and an input column address value among said plurality of column selection lines. A semiconductor memory device, further comprising a first activating means for simultaneously activating a column selection line corresponding to. 3. The semiconductor memory device according to claim 2, further comprising: a first deactivating means for deactivating a column selection line activated by said first activating means. Semiconductor storage device. 4. The semiconductor memory device according to claim 3, further comprising a second activating means for activating said sense amplifier after said deactivating means deactivates a column selection line. Semiconductor storage device. 5. The semiconductor memory device according to claim 3, wherein a word line is deactivated when or after a column selection line is deactivated by said first deactivating means. 2. A semiconductor memory device further comprising: 2 deactivating means. 6. The semiconductor memory device according to claim 1, wherein a word line corresponding to an input row address value among said plurality of word lines and said plurality of column selection lines are connected to each other. And simultaneously activating the column selection line corresponding to the input column address value, and setting the line of the write common bit line pair corresponding to the specified logical value to the first logical value level. A semiconductor memory device further comprising a writing unit. 7. The semiconductor memory device according to claim 6, wherein a line on a side corresponding to a specified logical value of said write common bit line pair is set to a first logical value level by said writing means. A write assisting means for setting a line on the side of the write common bit line pair that is not the side corresponding to the specified logical value to a second logical value level Storage device. 8. The semiconductor memory device according to claim 1, wherein said plurality of memory cells, said plurality of word lines, said plurality of column bit line pairs, and said write driver are provided. The sense amplifier, the common bit line pair for writing, the common bit line pair for reading, the plurality of column selection circuits, and the plurality of column selection lines.
A semiconductor memory device comprising a plurality of sets.