JP3291117B2 - Semiconductor storage device - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor memory device, and more particularly to a technology for reducing power supply noise at the time of writing data to the semiconductor memory device, for example, a technology effective when applied to an SRAM (static random access memory). .

[0002]

2. Description of the Related Art SRAM as an example of a semiconductor memory device
(Static random access memory) includes a memory cell array in which a plurality of static memory cells are arranged in a matrix. The memory cell array is usually formed in units called a plurality of memory mats or a plurality of memory blocks. The selection terminal of the memory cell is coupled to a word line for each row direction (row direction), and the data input / output terminal of the memory cell is coupled to a complementary data line (also referred to as a complementary bit line) for each column direction (column direction). Is done. Each of the complementary data lines is commonly connected to a complementary common data line via a column switch coupled to the complementary data line on a one-to-one basis.

An address signal input from the outside is transmitted to a row address decoder and a column address decoder via an address buffer arranged correspondingly. Based on the decode output of the row address decoder,
When the word line corresponding to the input address signal is driven to the selected level, all the memory cells connected to this word line are selected. Further, the column switch is turned on based on the decode output of the column address decoder, and the selected memory cell is conducted to the complementary common data line. When write data is supplied from the outside, a complementary common data line is driven in accordance with the write data, and charge information corresponding to the data is accumulated in a predetermined memory cell via the complementary data line selected by the column address.

[0004] As an example of a document describing SRAM, there is an "LSI Handbook (p.500-)" issued by Ohmsha on November 30, 1984.

[0005]

A data line load element for precharging the data line is coupled to the data line.
The data line is precharged to a predetermined potential level via the data line load element. Considering the case where the data line is pulled down to a low level for data writing, it is advantageous to increase the impedance of the data line load element in terms of speeding up the writing. However, if the impedance of the data line load element is changed at once in units of memory mats or memory blocks, SRAM
In some configurations, the number of data line load elements becomes enormous, and the power supply voltage level fluctuates greatly instantaneously due to a transient current when driving the data line load elements. This fluctuation becomes power supply noise and adversely affects the operation of each unit. A low power supply voltage is advantageous for speeding up the memory.
When a transistor is used, the amplitude of the voltage applied to the gate of the data line load MOS transistor becomes small under a low power supply voltage. Need to be larger. When the gate width of the MOS transistor is increased as described above, the gate capacitance is increased, so that a larger transient current flows due to the impedance control as described above. Further, during the high-speed write operation, the transient current flows in a short time, so that the power supply noise is further increased.

An object of the present invention is to provide a technique for reducing power supply noise.

The above and other objects and novel features of the present invention will become apparent from the description of the present specification and the accompanying drawings.

[0008]

The following is a brief description of an outline of a typical invention among the inventions disclosed in the present application.

That is, to selectively control the impedance of a corresponding data line load element based on a column selection signal for selecting a column system and a write enable signal for instructing data writing to a memory cell. The semiconductor memory device is configured by providing the data line load control circuit.

In addition to the column selection signal for column selection and the write enable signal for instructing data writing to the memory cell, the corresponding data is also taken into account in consideration of the data to be written to the memory cell. A data line load control circuit for selectively controlling the impedance of the line load element is provided.

At this time, based on a plurality of write recovery elements for performing write recovery, a write recovery signal for instructing this write recovery operation, and a column selection signal for selecting a column system, a corresponding write operation is performed. A write recovery control circuit for selectively controlling the operation of the recovery element can be provided.

Further, as a write recovery control circuit for selectively controlling the operation of the write recovery element, in addition to a write recovery signal for instructing a write recovery operation and a column selection signal for selecting a column system, , The write data to the memory cell can be considered.

[0013]

According to the above-mentioned means, the data line load control circuit does not control the data line load element impedance in units of memory mats or memory blocks all at once, but on the basis of the column selection signal and the write enable signal. A corresponding data line load element is selectively controlled.
This reduces the number of simultaneously driving elements of the data line load elements, and achieves a reduction in power supply noise caused by driving the data line load elements by reducing the transient current. At this time, selectively controlling the impedance of the corresponding data line load element with reference to the write data to the memory cell in addition to the column selection signal and the write enable signal can be performed by simultaneously driving the data lines. By further reducing the number of load elements, a current change when driving the data line load elements is reduced.

The write recovery control circuit selectively controls the operation of the corresponding write recovery element based on the write recovery signal and the write enable signal. To reduce power supply noise.
At this time, by selectively controlling the impedance of the corresponding write recovery element by referring to the write data to the memory cell in addition to the write recovery signal and the column selection signal, the simultaneous recovery of the write recovery signal The number of elements is further reduced to reduce a change in current during write recovery.

[0015]

FIG. 5 shows a computer system including an SRAM according to an embodiment of the present invention. This system includes a CPU (central processing unit) 401, a DRAM control unit 403, an SRAM 406,
A ROM (read only memory) 405, a peripheral device control unit 407, a display system 410, and the like are connected to each other so that signals can be exchanged. The CPU 401 is a logical core of the present system, and mainly performs address designation, information reading and writing, data operation, instruction sequence, acceptance of interrupt, activation of information exchange between a storage device and an input / output device, and the like. It has functions and is composed of various parts such as an arithmetic control part, a bus control part and a memory access control part. As an internal storage device, a DRAM 402 controlled by the DRAM control unit 403, an SRAM 406 used as a main memory, a backup control unit 404 for controlling backup of the SRAM 406, a ROM 4
05 is provided. The ROM 405 stores a program that does not require rewriting. Peripheral device controller 407
Although it is not particularly limited, it functions as an interface of a peripheral device such as an external storage device 408 exemplifying a magnetic storage device and an input device exemplifying a keyboard (KB) 409. The display system 410 includes a VRAM (video random access memory) and a control circuit therefor, and display data transferred via the system bus 400 is synchronized with the CRT display device 412 to display the display device. 412. Further, a power supply unit 411 is provided, and various voltages generated here are supplied to each unit of the present system.

FIG. 6 shows the overall structure of the SRAM 406. This SRAM is not particularly limited,
1Mbit SRAM with 32kword x 32bit configuration
It is formed on one semiconductor substrate such as a single crystal silicon substrate by a known semiconductor integrated circuit manufacturing technique. In FIG. 6, reference numeral 31 denotes a memory cell array in which a plurality of static memory cells are arranged in a matrix.
The selection terminal of the memory cell is coupled to a word line for each row direction, and the data input / output terminal of the memory cell is coupled to a complementary data line (also referred to as a complementary bit line) for each column direction. Numeral 34 denotes a column system peripheral circuit. The column system peripheral circuit 34 includes a plurality of data line load circuits coupled to complementary data lines, a differential amplifier circuit for amplifying memory cell data, and a column system selection circuit. It includes a column selection circuit and the like. Each complementary data line has a one-to-one
Are connected in common to a complementary common data line via a plurality of column switches coupled by.

Externally input addresses X0 to X7
Are transmitted to the X-decoder and driver 30 via a buffer (not shown) arranged correspondingly. The addresses Y0 to Y6 are transmitted to the Y decoder and driver 32 via buffers (not shown) arranged corresponding to the addresses. A word line corresponding to an input address signal is driven to a selected level based on an output signal of X decoder and driver 30. When a predetermined word line is driven, all the memory cells connected to this word line are selected. In addition, the Y decoder and driver 32 turns on a column switch corresponding to the address signal supplied thereto to make the corresponding complementary data line conductive to the complementary common data line. The memory cell data is output to the output circuit 3
External output is enabled via the terminal 5. This output data is
Although not particularly limited, it has a 32-bit configuration,
Do31. The write circuit 33 receives a write control signal WTP for controlling a write pulse width and write data Di0 to Di31. When write data Di0 to Di31 are applied from the outside, a complementary common data line is driven in accordance with the write data, whereby charge information corresponding to the data is supplied to a predetermined memory cell via the complementary data line selected by the address signal. Is accumulated.

FIG. 1 shows the memory cell array 50 of FIG.
6 and a detailed configuration example in the vicinity thereof. FIG. 1 shows only a circuit corresponding to one set of complementary common data lines 20 and 21, but a circuit having the same configuration is actually
It is formed corresponding to the number of simultaneous output bits (32 bits in this embodiment). Also, one set of common data lines 20,
21, a plurality of sets of complementary data lines are provided. In FIG. 1, among the plurality of complementary data lines,
Complementary data lines indicated by 12a and 13a and 12b and 1
The complementary data line indicated by 3b is representatively shown.
The complementary data lines 12a and 13a are connected via a column switch 22a, and the complementary data lines 12b and 13b are connected via a column switch 22b.
21. Column switch 2
2a and 22b respectively constitute a part of the column peripheral circuit 34 shown in FIG. 6, and their operations are selectively controlled by column selection signals 6a and 6b output from the Y decoder and driver 32, respectively. The common data lines 20, 21 are connected to the write circuit 3 shown in FIG.
3 are coupled, and the complementary common data lines 20 and 21 are driven by the write driver 5. Complementary data lines 12a and 13a are coupled to data input / output terminals of representatively shown memory cells 1a and 1b. Select terminals of memory cells 1a and 1b are coupled to word line 3 for each row direction. When word line 3 corresponding to an input address signal is driven to a selected level based on the output signals of X decoder and word driver 30 shown in FIG. 6, all memory cells 1a, 1b coupled to this word line are driven. Is selected. When the column selection signal 6a or 6b is set by the Y decoder and driver 32 shown in FIG. 6, the corresponding column switch 22a or 22b is turned on, so that the complementary data line 12a, 13a or 12b, 13b becomes common data. Connected to lines 20,21. When write data is supplied via write driver 5, complementary common data lines 20 and 21 are driven in accordance with the write data, and a charge corresponding to the data is supplied to a predetermined memory cell via the complementary data line selected by the address signal. Information is accumulated. Data read from the memory cells 1a and 1b to the complementary data lines 12a and 13a and 12b and 13b, respectively, are amplified by the differential amplifier circuits 2a and 2b, respectively, and then output to the external circuit via the output circuit 35. Is done.
Although not particularly limited, the differential amplifier circuits 2a and 2b are configured by differentially coupling bipolar transistors, and the operation thereof is controlled by column selection signals 6a and 6b, respectively. For example, when the column selection signal 6a is set at a high level, the differential amplifier circuit 2a is selectively activated, and when the column selection signal 6b is set at a high level, the differential amplifier circuit 2b is selected. Activated.

The complementary data lines 12a and 13a have
Data line load circuits 24a and 25a for precharging the complementary data lines 12a and 13a are provided. Similarly, data for precharging the complementary data lines 12b and 13b are provided in the complementary data lines 12b and 13b. Line load elements 24b and 25b are provided. The data line load circuits 24a, 25a, 24b, 25b are, but not limited to, two p-channel MOS transistors connected in parallel to each other. For example, as representatively shows a configuration example of the data line load elements 24b and 25a, the p-channel type MOS transistors 8a and 8p
The data line load element 24b is formed by connecting the channel type MOS transistor 48a in parallel, and the data line load element 2 is formed by connecting the p channel type MOS transistor 9a and the p channel type MOS transistor 49a in parallel.
5a is formed. In the data line load circuit 24a,
The drain electrodes of the p-channel MOS transistors 8a and 48a are connected to the data line 12a, and the source electrodes are connected to the power supply Vdh. The gate electrode of the p-channel MOS transistor 48a is coupled to the power supply Vdl. In the data line load element 25a, the drain electrodes of the p-channel MOS transistors 9a and 49a are coupled to the data line 13a, and the source electrode is a power supply Vdh.
Is combined with Further, the gate electrode of p-channel MOS transistor 49a is coupled to power supply Vdl. Here, when the high-potential-side power supply voltage of ECL (emitter-coupled logic) is 0 V and the low-potential-side power supply Vee is -4 V,
The potential of the power supply Vdh is -1.5 V,
The potential of dl is -3.3 V, and the voltage is lowered to improve the memory operation speed. On the other hand, gate electrodes of p-channel MOS transistors 8a and 9a are coupled to data line load control circuits 26a and 26b, respectively. The data line load control circuit 26a receives the data from the data line load circuit 24a based on the column selection signal 6a, the write enable signal 7 for instructing data writing to the memory cell, and the write data Di to the memory cell. The impedance is selectively controlled, and although not particularly limited, a column selection signal 6a, a write enable signal 7,
It is configured by an AND circuit for obtaining a logical AND with the write data Di to the memory cell. Similarly, the data line load control circuit 27a includes a column selection signal 6a, a write enable signal 7 for instructing data writing to a memory cell, and write data Di * (a logically inverted signal of Di) to the memory cell. Based on the data line load element 25a
, And is constituted by an AND circuit for obtaining the logical product of the column selection signal 6a, the write enable signal 7, and the write data Di * to the memory cell. That is, the p-channel MOS transistor 8a is controlled by the logical product output of the column selection signal 6a, the write enable signal 7, and the write data Di to the memory cell, and the p-channel MOS transistor 9a is controlled by the column selection signal 6a. , A write enable signal 7 and a logical product output of the write data Di * to the memory cell.

The data line load elements 24b and 25b coupled to the data lines 12b and 13b have the same configuration as the data line load circuits 24a and 25a. A data line load control circuit 2 for controlling the data line load element 24b.
6b is a logical product circuit for obtaining a logical product of a column selection signal 6b, a write enable signal 7 for instructing data writing to the memory cell, and write data Di to the memory cell. Load element 25b
Is obtained by ANDing the column selection signal 6b, the write enable signal 7 for instructing data writing to the memory cell, and the write data Di * to the memory cell. And a logical AND circuit.

FIG. 2 shows the operation timing of the main part of the circuit of this embodiment. In FIG. 1, the word line 3 is driven to the selected level, the memory cell 1a is selected by the column selection signal 6a, and the data line 12a is further lowered to the low level by the write data Di. Consider writing.

The write driver 5 controls the common data line 2
When 0 is reduced to the write level, the write enable signal 7 is set to the high level. Input data Di
Is high, the column selection signal 6a is high, and the write enable signal 7 is high. When the logical product condition of the data line load control circuit 26a is satisfied, the output control signal 28a becomes low. To a high level. As a result, the p-channel MOS transistor 8a as a data line load element is turned off, so that the impedance between the source and the drain increases. p-channel type MOS transistor 48a
Is fixed to be always on in order to prevent data line floating, but since the p-channel MOS transistor 8a connected in parallel to it is turned off, as a result, the impedance of the data line load circuit 24a becomes p-channel. This is larger than when the type MOS transistor 8a is on. As such, the data line load circuit 24a
Is increased, the data line 12a is easily lowered to a low level.
Speeding up of data writing such that 2a is at a low level is achieved. In such data writing, since the data line 13a paired with the data line 12a is not pulled down to a low level, it is not necessary to change the impedance of the data line load circuit 25a coupled to the data line 13a. Therefore, in the present embodiment, in the data line load circuit control, by checking input data for writing, the impedance of the data line load circuit corresponding to the other data line of the complementary data line pair is not changed. I have to. That is, in the case of the above example, in the data line load control circuit 27a, since Di * (the logically inverted signal of Di) is at the low level, the output control signal 29a, which is the logical product thereof, remains at the low level. Therefore, the corresponding p-channel type MOS
Transistor 9a is kept on.
When the column selection signal 6a is set to the high level and the column switch 22a is turned on, the other column switches sharing the common data lines 20, 21 are not turned on. For example, when the column selection signal 6a is set to a high level, the column selection signal 6b is set to a low level, so that the data line load control circuit 26b,
Since the output control signals 28b and 29b of the signal line 27b are at a low level, the impedance of the data line load circuits 24b and 25b is not changed. That is, the p-channel MOS transistors included in the data line load circuits 24b and 25b continue to be in the ON state because the control signals 28b and 29b are at the low level.

Next, consider the case where the write enable signal 7 is changed from high level to low level. As described above, the memory cell 1a is selected by the column selection signal 6a, and the data line 12 is further selected by the write data Di.
When writing data to the memory cell 1a by lowering the a side to a low level, the common data line 20,
Out of a plurality of data lines sharing the data line 21
Since the impedance of only the data line load circuit 24a is controlled to be high in order to easily lower only the data line load circuit 24a to the low level, when the write enable signal 7 is changed from the high level to the low level,
The impedance of only a is controlled to be low. That is, when the write enable signal 7 is changed from high level to low level, the output control signal 28a of the data line load control circuit 26a is changed from high level to low level, thereby turning off the p-channel MOS transistor 8a. To the ON state, and the logics of the output control signals of the other data line load control circuits such as the data line load control circuits 27a, 26b, 27b are not changed.

According to the above embodiment, the following functions and effects can be obtained. (1) As shown in FIG. 2, the data line load control circuit 2
At the timing a when the output control signal 28a of 6a rises, a transient current for charging the p-channel MOS transistor 8a as a data line load element flows from the high potential side power supply, so that noise is generated in the high potential side power supply. Cheap. At the timing b when the output control signal 28b falls, contrary to the above case, a transient current for discharging the accumulated charge of the p-channel MOS transistor 8a as the data line load element flows into the low potential side power supply. Therefore, noise is likely to occur in the low potential side power supply. Here, in the method of simultaneously changing the impedance of the data line load element in units of memory mats or memory blocks, power supply noise is generated by a transient current when driving a data line load in a data write operation to a memory cell. In particular, under a low power supply voltage, the amplitude of the voltage applied to the gate of the data line load MOS transistor also becomes small. Therefore, it is necessary to increase the gate width of the data line load MOS transistor to obtain the required data line amplitude. As a result, the gate capacitance increases and a larger transient current flows.

On the other hand, according to the above embodiment, in the data writing, only the data line which needs to be pulled down to the low level controls the impedance of the data line load circuit corresponding to the data line. Since the number of p-channel MOS transistors as data line load elements that are simultaneously driven during data writing can be greatly reduced, the number of simultaneously driven p-channel MOS transistors can be reduced.
The total sum of the gate capacitances of the channel type MOS transistors can be greatly reduced. As a result, the transient current for driving the data line load can be reduced, so that the power supply noise can be reduced. That is, although the voltage is lowered to improve the operation speed of the memory and the gate width of the p-channel MOS transistor as the data line load element is increased in order to obtain the required data line amplitude, they are driven simultaneously. Since the number of data line load elements is reduced, power supply noise caused by impedance control of the data line load circuit can be reduced. Also, the current consumption can be reduced by greatly reducing the number of p-channel MOS transistors as data line load elements that are simultaneously driven during data writing.

(2) Since a high-speed write operation can be performed under such a low power supply voltage and power supply noise can be suppressed, a data in which such an SRAM is mounted as a main memory, a cache memory, or the like. In the processing device, the reliability of stored data can be improved by improving the memory access speed by the CPU 401 and reducing noise.

FIG. 3 shows an SRA according to another embodiment of the present invention.
An example of the main configuration of M is shown. In FIG. 3, FIG.
Those having the same functions as those shown in FIG. In this embodiment, a p-channel MOS transistor is used as a data line load element as in the case of the above-described embodiment, and the data line is pulled up to a potential in a read state immediately after writing, thereby achieving a so-called write recovery. Write recovery circuit 42a for performing
43a, 42b, 43b and the write recovery circuit 4
Recovery control circuits 40a, 41a, 40b, 41b for controlling 2a, 43a, 42b, 43b are provided. Although the write recovery circuit is not particularly limited,
It is composed of a bipolar transistor that can operate at high speed. As representatively shown, the write recovery circuit 4
The emitter electrodes of the npn-type bipolar transistors 44a and 45a forming the 2a and 43a are coupled to the data lines 12a and 13a, respectively, and the collector electrode is coupled to a high-potential-side power supply (ground line). The write recovery control circuit is configured by an AND circuit for obtaining the logical product of the write recovery signal 4, the column selection signal 6a or 6b, and the data Di or Di *.

FIG. 4 shows the operation timing of the main part of the circuit of this embodiment. The complementary data lines 12a and 13a
Data line load circuits 24a and 25a for precharging the complementary data lines 12a and 13a are provided. Similarly, the complementary data lines 12b and 13b are provided for precharging the complementary data lines 12b and 13b. Data line load elements 24b and 25b are provided, and only the data lines that need to be pulled down to a low level in data writing are controlled by controlling the impedance of the corresponding data line load circuit. The reduction in the number of p-channel MOS transistors as data line load elements that are simultaneously driven during data writing is the same as in the above embodiment.

The output signals of the recovery control circuits 40a, 41a, 40b, and 41b are supplied to write recovery circuits 42a, 43a, 42b, and 43b for immediately pulling up the data lines to the read state immediately after the data writing. 46a, 47a, 46b and 47b are input. The write recovery signal 4 is generated in response to the rising edge of the write enable signal 7 in order to quickly raise the data line to the potential in the read state. The column selection signal 6a is selected, and the data line 12 is used to write the input data Di.
Since a is lowered to the low level, only the output control signal 46a of the recovery control circuit 40a is changed. Accordingly, only the bipolar transistor 44a as the write recovery circuit 42a coupled to the data line 12a is turned on for the write recovery operation. In other words, immediately after data writing such that the data line 12a is lowered to the low level, only the data line 12a needs write recovery, and the other data lines 13a, 12b, 13b, etc. need write recovery. , The write recovery control circuits 40a, 41a,
In spite of the fact that the write recovery signal 4 is set to the high level with respect to 40b, 41b, the write recovery control circuits 41a, 40b, 41b do not turn on the bipolar transistors as write recovery elements. This is because the write recovery control circuit 41a has the input data Di * at low level, the write recovery control circuit 40b has the column selection signal 6b at low level, and the write recovery control circuit 41b has the column selection signal 6b and the input data Di *. This is because both Di * are at the low level. Similarly, when data writing is performed such that the data line 13a is pulled down to a low level, only the write recovery circuit 43a coupled to the data line 13a is turned on, and the other write recovery circuits are turned on. Not done.

When an enormous number of write recovery elements are simultaneously driven for write recovery immediately after data writing, a transient current flows as in the case of impedance control of a data line load circuit, thereby causing power supply noise. May occur. However, in this embodiment, in order to drive a bipolar transistor as a write recovery element, a logical product of a write recovery signal, a column selection signal, and an input data line is obtained. Only the bipolar transistor corresponding to the data line selected for data writing pulls the corresponding data line to the potential in the read state at high speed, and the bipolar transistor as the other write recovery element is turned on. Not driven. As described above, by selectively driving the bipolar transistors for write recovery, the number of bipolar transistors that are simultaneously driven in write recovery can be reduced. Therefore, write recovery can be performed in units of memory mats or memory blocks. The transient current caused by the write recovery operation can be reduced as compared with the case where the bipolar transistors as the use elements are simultaneously driven and controlled. Therefore, as in the case of driving the data line load element, the power supply noise can be suppressed by reducing the instantaneous fluctuation of the power supply voltage level due to the transient current. That is, in the circuit of the present embodiment, in data writing, only the data lines that need to be pulled down to the low level are controlled by controlling the impedance of the corresponding data line load circuit, thereby simultaneously driving the data line loads. The transient current is suppressed by reducing the number of p-channel MOS transistors as elements, and in the case of write recovery, the transient current is suppressed by reducing the number of simultaneously driven bipolar transistors. In addition, power supply noise due to impedance control of a data line load circuit and a write recovery operation can be reduced.

The invention made by the inventor has been specifically described based on the embodiments. However, it is needless to say that the present invention is not limited to the embodiments and can be variously modified without departing from the gist of the invention. No.

For example, in the above embodiment, the input data Di and Di * are taken in the data line load control circuits 26a, 27a, 26b and 27b, but this can be omitted. That is, in the above-described embodiment, a three-input AND circuit is applied as the data line load control circuits 26a, 27a, 26b, and 27b. However, this is a two-input AND circuit and takes in the input data Di and Di *. May be omitted. In this case, the write enable signal 7
And the column selection signal 6a (or 6b). By involving the column selection signal in the data line load control, at least the data line load element corresponding to the data line in the column non-selected state is obtained. Since impedance control does not need to be performed, the number of simultaneously driven data line load elements is reduced, and the total sum of gate capacitances of simultaneously driven p-channel MOS transistors can be reduced. As in the case of the above embodiment, the power supply noise can be reduced by reducing the transient current for driving the data line load.

Further, in the above embodiment, in order to drive a bipolar transistor as a write recovery element, a logical product of a write recovery signal, a column selection signal, and an input data line is obtained. When obtaining the product, the input data Di and Di * may be omitted. For example, the write recovery control circuits 40a, 41a, 40b, 41b shown in FIG.
Are respectively constituted by two-input AND circuits, and each of them can be configured to obtain the logical product of the write recovery signal and the column selection signal. Even in such a case, by involving the column selection signal in the write recovery control, it is not necessary to control the operation of at least the write recovery element corresponding to the data line in the column non-selected state. By reducing the number of elements, power supply noise can be reduced by reducing the transient current for driving the data line load, as in the case of the above embodiment.

In the above embodiment, the case where the write port and the read port are separated has been described. However, the write port and the read port can be shared. In other words, in reading the memory cell data, the memory data read to the data line is transmitted to the common data lines 20 and 21 via the column switch, and the external output of the memory cell data is transmitted via the input / output external terminal. It may be performed. Even in such a configuration, as described above, by selectively controlling the impedance of the data line load element and selectively controlling the operation of the write recovery element, the same operation as in the above-described embodiment can be achieved. The effect can be obtained.

In the above description, the case where the invention made by the present inventor is mainly applied to a single-chip SRAM, which is the field of application as the background, has been described. However, the present invention is not limited to this. The present invention can also be applied to an SRAM built in a data processing device such as a chip microcomputer.

The present invention can be applied on the condition that at least a data line load element for precharging the data line is included.

[0037]

The effects obtained by typical ones of the inventions disclosed in the present application will be briefly described as follows.

That is, the data line load control circuit selectively controls the corresponding data line load element based on the column selection signal and the write enable signal, thereby changing the current change when driving the data line load element. And power supply noise caused by driving the data line load element can be reduced. Also, by selectively controlling the impedance of the corresponding data line load element by referring to the write data to the memory cell in addition to the column selection signal and the write enable signal, the data line selectively controlled is provided. By further reducing the number of load elements, a change in current when driving the data line load elements can be reduced.

When write recovery is performed immediately after writing data, a write recovery control circuit is provided to selectively control the operation of the corresponding write recovery element based on the write recovery signal and the column selection signal. Thus, a change in current during write recovery is reduced, and power supply noise is reduced. At this time, by selectively controlling the impedance of the corresponding write recovery element by referring to the write data to the memory cell in addition to the write recovery signal and the column selection signal, the write control is selectively performed. By further reducing the number of recovery elements, it is possible to reduce a change in current during write recovery.

[Brief description of the drawings]

FIG. 1 is a block diagram of a main part configuration of an SRAM according to an embodiment of the present invention.

FIG. 2 is an operation timing chart of a main part of the SRAM.

FIG. 3 is a block diagram of a main part configuration of an SRAM according to another embodiment of the present invention.

FIG. 4 is an operation timing chart of a main part of an SRAM according to another embodiment of the present invention.

FIG. 5 is a block diagram illustrating a configuration example of a data processing device including the SRAM.

FIG. 6 is an overall configuration block diagram of the SRAM.

[Explanation of symbols]

 1a memory cell 1b memory cell 2a differential amplifier circuit 2b differential amplifier circuit 3 word line 5 write driver 8a p-channel MOS transistor 9a p-channel MOS transistor 12a data line 12b data line 13a data line 13b data line 20 common data line 21 Common data line 22a Column switch 22b Column switch 24a Data line load circuit 24b Data line load circuit 25a Data line load circuit 25b Data line load circuit 26a Data line load control circuit 26b Data line load control circuit 27a Data line load control circuit 27b Data Line load control circuit 30 X decoder and driver 31 Memory cell array 32 Y decoder and driver 33 Write circuit 34 Column peripheral circuit 35 Output circuit 40a Write recovery control circuit Road 41a Write recovery control circuit 40b Write recovery control circuit 41b Write recovery control circuit 42a Write recovery circuit 43a Write recovery circuit 42b Write recovery circuit 43b Write recovery circuit 44a Bipolar transistor 45a Bipolar transistor 48a P-channel MOS transistor 49a P-channel MOS transistor 402 DRAM 403 DRAM control unit 404 Backup control unit 405 ROM 406 SRAM 407 Peripheral device control unit 408 External storage device 409 Keyboard 410 Display system 411 Power supply unit 412 Display device

────────────────────────────────────────────────── ─── Continuing on the front page (72) Inventor Sosuke Tsuji 5-20-1, Josuihonmachi, Kodaira-shi, Tokyo Inside Hitachi Super LSI Engineering Co., Ltd. (56) References JP2 -9088 (JP, A) JP-A-4-76894 (JP, A) JP-A-62-245592 (JP, A) JP-A-64-46288 (JP, A) JP-A-62-99976 (JP, A) JP-A-2-146183 (JP, A) (58) Fields investigated (Int. Cl. ⁷ , DB name) G11C 11/41

Claims (3)

(57) [Claims] A plurality of data lines coupled to data input / output terminals of a memory cell; and a plurality of data line load elements provided corresponding to the data lines for precharging the corresponding data lines. A semiconductor memory device including a column switch for selectively coupling the plurality of data lines to a common data line based on a column selection signal for column system selection, wherein the column selection signal;
A data line load control circuit for selectively controlling the impedance of a corresponding data line load element based on a write enable signal for instructing data writing to the memory cell and data to be written to the memory cell. A semiconductor memory device comprising: A plurality of data lines provided for the plurality of data lines for performing write recovery by driving the data lines to a potential level in a memory cell data read state immediately after writing data to the memory cells; Based on the write recovery element, the write recovery signal for instructing the write recovery operation, the column selection signal, and the write data to the memory cell, the operation of the corresponding write recovery element is selectively controlled. the semiconductor memory device according to claim 1 Symbol placement and a write recovery control circuit for. 3. The write recovery signal according to claim 2 , wherein
3. The semiconductor memory device according to claim 2, wherein the semiconductor memory device is generated according to an edge of the enable signal .